200924128 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種增層線路板之製作方法，尤 指-種以雙介電層支撐之單層圖案化線路結構為美 完成-半導料層㈣基板結構之增層線路板 方法。 【先前技術】 ^ 一/ 録板之製作上，其製作方式通常 '、核、基板開始，、經過鑽孔、電鍍金屬、A 雙面線路製作等方々…上 基孔及 式，元成一雙面結構之内層核心 ’之後再經由-料增層製程 板。如第3 2圖所示，m ^日訂裝暴 面示意圖。首先，準備其:為：有核層封裝基板之剖 心基板“係由二：、基板其中，該核 此芯層8 1丄表面^ 心層8 11及形成於 8 H 路層8 12所構成，且該芯層 連接該芯層個電鍍導通孔8 13,可藉以 丄丄表面之線路層8 1 2。 8 圖3 3〜第3 6圖所示’對該核心基板 ^开Γ層製程。首先，係於該心基板8 1 表面形成一第—介雷 土低〇丄 面並形成有複數^ 且該第—介電層8 2表 1 2 ;之德， 開口8 3 ’以露出該線路層§ 層8 2外露之^無電電鑛與電鑛等方式於該第一介電 卜路之表面形成—晶種層δ4，並於該晶種層 200924128 84上形成1案化阻層85，且其圖案化阻層85 中並有複數個第二開口 8 6 ’以露出部份欲形成圖案 化線路之晶種層8 4 ;接著，利用電狀方式於該第 一開口 8 6中形成-第-圖案化線路層8 7及複數個 導電盲孔8 8 ’並使其第一圖案化線路層8 7得以透 過該複數個導電盲孔8 8與該核心基板8丄之線路層 8 1 2做電性導通，然後再進行移除該圖案化阻層8 5與蝕刻，待完成後係形成-第-線路增層結構8a。 同樣地係、可於該第—線路增層結構8 &之最外 層表面再運用相同之方式形成—第二介電層8 9及__ 第二圖案化線路層9 Q之第二線路增層結構8 b，以逐 步增層方式形成-多層封裝基板。然:而，此種製作方 法有佈線密度低'層數多及流程複雜等缺點。 另外，亦有利用厚銅金屬板當核心材料之方法， 可於經過餘刻及塞孔等方式完成一内層核心板後，再 經由一線路增層製程以完成一多層封裝基板。如第3 7圖〜第39圖所示，其係為另一有核層封裝基板之 剖面示意圖。首先’準備一核心基板9丄，該核心基 板9 1係由一具預定厚度之金屬層利用蝕刻與樹脂塞 孔9 1 1以及鑽孔與電鍍通孔g丄2等方式形成之單 層銅核心基板9 1 ;之後，利用上述線路增層方式， 於泫核心基板9 1表面形成一第一介電層9 2及一第 一圖案化線路層9 3，藉此構成一具第—線路增層結 200924128 構9 a。該法亦與上述方法相同，係可再利 增層f式於該第一線路增層結構9a之最外層表2 成一第二介電層94及一室-国奋 面也 ^ h 第—圖案化線路層9 5，# 1 ::=路增層結構9b，以逐步增層方式： 心基板製作不易，且亦與上述方法相同，具有佈2 度低及流程複雜等缺點。^ 使用者於實際使用時之所需。 /套付合 【發明内容】 :發明之主要目的係在於，可完成一半導體多層 結構，可有效改善超薄核層基板板彎翹問題 及簡化傳統增層線路板之製作流程。 數夕^明之次要目的係在於，可依實際需求形成雙 之封裝基板’並可有效達到降低成品板厚度及 減> 製作成本之目的。 你古2達、乂上之目的’本發明係一種增層線路板之製 首先係以光學微影及蝕刻之方式於一雙面 製作一單層線路’藉此以做為增層結構之電性 =签，、之後再於該單層線路連接塾關合之方式形 ，增層線路，以形成一具三層金屬結構之電路 其中兩層係已完成圖案化線路且已透過複數個 玫孔而產生電性連接。接著，再於該第一增層線 路、、°構上形成第二增層線路，同時使原未圖案化線路 200924128 ’成為一具圖案化線路且200924128 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a build-up circuit board, and more particularly to a single-layer patterned circuit structure supported by a double dielectric layer for the US-finished-semiconductor Material layer (4) Method of layering circuit board of substrate structure. [Prior Art] ^ One / the production of the recording board, its production method is usually ', nuclear, substrate start, through drilling, electroplating metal, A double-sided line production, etc....Base hole and style, Yuan into a double-sided The inner core of the structure is then passed through the material build-up process board. As shown in Figure 3, the m ^ day is equipped with a schematic diagram of the storm. First, it is prepared: the core substrate of the core layer package substrate is “two: the substrate, the core, the core layer 8 1丄 surface layer 8 11 and the 8 H layer 8 12 are formed. And the core layer is connected to the core layer of the plating vias 8 13 and the wiring layer 8 1 2 of the surface can be formed. 8 FIG. 3 3 to FIG. 3 show the process of opening the layer to the core substrate. First, a first-throic low-lying surface is formed on the surface of the core substrate 8 1 and a plurality of the first dielectric layer 8 2 is formed, and the opening 8 3 ′ is exposed to expose the line. Layer § layer 8 2 exposed ^ no electric ore and electric ore, etc. form a seed layer δ4 on the surface of the first dielectric channel, and form a resist layer 85 on the seed layer 200924128 84, And a plurality of second openings 8 6 ′ are formed in the patterned resist layer 85 to expose a portion of the seed layer 8 4 to form a patterned line; and then formed in the first opening 86 by an electrical method - a first patterned circuit layer 87 and a plurality of conductive vias 8 8 ′ and having the first patterned wiring layer 8 7 transparent to the plurality of conductive vias 8 8 and the core substrate The circuit layer 8 1 2 of the 8 做 is electrically conductive, and then the patterned resist layer 8 5 is removed and etched, and after completion, the - first line build-up structure 8a is formed. - the outermost surface of the line build-up structure 8 & is formed in the same manner - the second dielectric layer 8 9 and the second patterned layer 9 Q of the second patterned build layer 8 b are gradually increased The layer method forms a multi-layer package substrate. However, this method has the disadvantages of low wiring density, large number of layers, and complicated process. In addition, there is also a method of using a thick copper metal plate as a core material, which can be passed through the After completing an inner core plate by means of plugging, etc., a multi-layer package substrate is completed through a line build-up process. As shown in Figures 37 to 39, it is another core-layer package substrate. Schematic diagram of the cross section. First, a core substrate 9 is prepared. The core substrate 9 1 is formed by a metal layer having a predetermined thickness by etching and a resin plug hole 9 1 1 and a hole and a plated through hole g丄2. a layer of copper core substrate 9 1; thereafter, using the above-mentioned line build-up method, A first dielectric layer 92 and a first patterned circuit layer 9 are formed on the surface of the core substrate 91, thereby forming a first line-increasing junction 200924128. The method is also the same as the above method. , can be further increased layer f in the outermost layer of the first line build-up structure 9a 2 into a second dielectric layer 94 and a room - Guo Fen face ^ h first - patterned circuit layer 9 5, # 1 ::= Road-addition layer structure 9b, in a step-by-step layering manner: The core substrate is not easy to fabricate, and is also the same as the above method, and has the disadvantages of low cloth 2 degree and complicated process. ^ User needs in actual use. [Summary] The main purpose of the invention is to complete a semiconductor multilayer structure, which can effectively improve the bending problem of the ultra-thin core substrate plate and simplify the production process of the conventional build-up circuit board. The secondary purpose of the number of eves is that the double package substrate can be formed according to actual needs, and the purpose of reducing the thickness of the finished board and reducing the manufacturing cost can be effectively achieved. The purpose of your invention is to create a layered circuit board by optical lithography and etching. This is used as a layered structure. Sex = sign, and then in the single-layer line connection, the layer is formed to form a circuit with a three-layer metal structure, two of which have completed the patterned circuit and have passed through the plurality of holes And an electrical connection is made. Then, a second build-up line is formed on the first build-up line and the structure, and the original unpatterned line 200924128 ’ becomes a patterned line.
導通，藉此以完成一無核層多層封裝基板。 之金屬層形成第三增層線路 電性導通之四層基板，並？ 【實施方式】 請參閱『第1圖〜第3 1圖』所示，係分別為本 發明之製作流程示意圖、本發明之雙面基板剖面示意 圖、本發明之兩層基板（一）剖面示意圖、本發明之 兩層基板（二）剖面示意圖、本發明之兩層基板（三） 剖面示意圖、本發明之兩層基板（四）剖面示意圖、 本發明之二層基板（五）剖面示意圖、本發明之三層 基板（六）剖面示意圖、本發明之三層基板（七）剖 面示意圖、本發明之三層基板（八）剖面示意圖、本 發明之三層基板（九）剖面示意圖、本發明之三層基 板（十）剖面示意圖、本發明之三層基板（十一）剖 面示意圖、本發明之四層基板（一）剖面示意圖、本 發明之四層基板（二）剖面示意圖、本發明之四層基 板（三）剖面示意圖、本發明之四層基板（四）剖面 示意圖、本發明之四層基板（五）剖面示意圖、本發 明之四層基板（六）剖面示意圖、本發明具圖案化及 電性連接之四層基板（七）剖面示意圖、本發明之置 200924128 晶側與球側線路層（一）剖面示意圖、本發明之置晶 側與球側線路層（二）剖面示意圖、本發明之置晶側 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 與球側線路層（三）剖面示意圖、本發明之上下兩層 線路增層結構（―）剖面示意圖 曰 線路增層結構（二）剖面示意圖 線路增層結構（三）剖面示意圖 線路增層結構（四）剖面示意圖 、線路增層結構（五）剖面示意圖 線路增層結構（六）剖面示意目 : = :(七)剖面示意圖及本發明之上= 線路增層結構（八）丨 #一_^ 如圖所示：本發明 糸種田層線路板之製作方法，其至少包括下列步驟： 基板10:如第2圖所示，選擇 -金屬w/1電°31、一第—金屬層3 2及-第 一金屬層33之雙面基板工； (B )貼合第一、二阻層1 1 :如第3圖所干 該f面基板之第-金屬層32上貼合：第：阻 二f蓋狀^於该雙面基板之第二金屬層3 3上以完 王覆蓋狀貼s —第二阻層3 5 ; (C) 形成複數個第一開口 1 2 ··如第4圖所干 以曝光及顯影之方式扃 4 S斤不， 第一開口 3 β e 3 4上形成複數個 弟開36，以顯露其下之第—金屬層32 ; (D) 移除第一金屬層1 3 :如第5圖所示，以 200924128 金屬層3 =之方式移除該第—開σ36下方之第— )形成苐一線路層丄4 ··如 除該第一阻層及哕筮_„ β 吊b圖所示，移 具有作為電性連接墊^ a 金屬層形成一 设免之第—線路層3 7 ; (F)形成二層結構之電路基板 所示，於該第一後蹊展Q π 13 ·如第7圖 琛路層37及該第一介雷 接壓合或貼合一與哕 電層31上直 兴„哀第一介電層3 1相同 層38及一第二全屬』之第二介電 木—|屬層3 9 ’形成一二屏姓4故 基板2a; 小取一層結構之電路 (G)形成複數個第二開口工6 :如 =:孔之方式於該第三金屬層39與該第二：電 二 形成禝數個第二開口 4 0，以顯露其下之第 表路層37之第-面3 7a，其中，該複數個第二開 口 4 0係可先做開銅窗後再經由雷射鑽孔 接以雷射鑽孔之方式形成； 係直 (H)無電電鍍與電鍍第四金屬層17:如第9 圖所示，以無電電鍍與電鍍之方式於複數個第二開口 中及該第-線路層37與該第三金屬層39上形成一 第四金屬層4 1，其中，該第四金屬層4丄係做為與 5玄第一線路層3 7之電性連接用，且層與層之間之連 接係由電鑛之複數個第一雷射盲孔4 6所導通； 200924128 ("貼合第三、四阻層18 :如第1〇圖所示， 分別於該第四金屬層41上貼合 及於該第二金屬層33上以完全覆蓋狀貼合2 層 4 3 ; ^ 1 (J)形成複數個第三開口19:如 示，以曝光及顯影之方式在該第三阻 數個第三開口 44,以顯露其下之第四金屬2層上成複 (K)移除第三、四金屬 示，以姓刻之方式移㈣第如第12圖所 屬们9與第四金屬層開口44下方之第三金 基板以案化::及電性連接之三層 至此C屬層形成一第三線路層45， 兩層具圖案化線路及電性連接之三 (M)壓合第三介電層及第五金屬層2 2 1 4圖所#，於該第三線路層4 5及該第二介 8上再壓合-第三介電層47及—第五金屬層48 曰； 一（N)形成複數個第四、五開口 2 3 :如第丄5 圖所不，以雷射鑽孔之方式分別於t亥第二金屬層3 3 與2第一介電層3 1上形成複數個第四開口 4 9 ’以 顯露其下已圖案化之第一線路層3 7之第二面3 了 200924128 第五金屬層48與該第三介電…上形 五開口 5◦，以顯露其下已圖案化之第三 線路層4 5，其中，該複數個第四、五開口 4 9、$ 0係可先做開銅窗後再經由雷射鑽孔、亦或係直接以 雷射鑽孔之方式形成； (〇)無電f鍍與f鍍第六、七金屬層24:如 二二所：’以無電電鍍與電鍍之方式分別於複數 =開口中及該第二金屬層33上形成一第六金屬 複數個第五開口中及該第五金屬層4 -第七金屬層52,其中，層與層之間之連 =由電鍍之複數個第二、三雷射盲孔53、“所 (Ρ)貼合第五、六阻層25:如第丄了圖所示， /刀別於該第六金屬層51上貼合一第五阻層55，以 及於該第七金屬層52上貼合一第六阻層56 ; (Q)形成複數個第六、七開口 2 6 :如第1 8 圖所示’以曝光及顯影之方式分別於該第五阻層55 ::成複數個第六開口57，以顯露其下之第六金屬 曰5 1，以及於該第六阻層5 6上形成複數個第七開 口 5 8 ’以顯露其下之第七金屬層5 2 ; (R)移除第二、五、六、七金屬層2 7 :如第 1 9圖所示，以㈣之方式分別移除該第六開口 5 7 下方之第二金屬層3 3與第六金屬層5 1，以及移除 12 200924128 該第七開口58下方之第五金屬層48與第七金屬層 5 2; (S)完成四層具圓案化線路及電性連接之四層 基板2 8 .如第2 〇圖所示，分別移除該第五阻層， 使該第二、六金屬層形成一已圖案化之第二線路層5 9 ’以及移除該第六阻層，使該第五、七金屬層形成 -已圖案化之第四線路層6 〇。至此完成—四層具圖 案化線路及電性連接之四層基板3，並可選擇直接進 行步驟（丁）或步驟（U); (T )進行置晶側與球側線路層電性連接墊製作 2 9 ·進行-置晶側與球側線路層電性連 其至少包含下列步驟： t 1：>塗覆第-、二防焊層291:如第2 1圖所示’分別於該第二線路層59與該第-介電声 二 m-層絕緣保護用之第—防焊層61，以J 於㈣四線路層60與該第三介電層47上 一 層絕緣保護用之第二防焊層6 2 ; y 2)形成複數個第八、九開口2” ：女 所示’以曝光及顯影之方式分別在該 =:形成複數個第八開口63，以及在該第: 防¥曰6 2上形成複數個第九開D 6 4。藉此 線路增層結構作為電性連接墊； S ”、、與 13 200924128 路層2 ( 1 3)完成具完整圖案化之置晶側與球側線 口 6 9 3 ·如第2 3圖所示，分別於複數個第八開 開口 6: = :第：阻障層65 ’以及於複數個第九 蚊圖安Γ 阻障層6 6。於此，獲得具完 多屠^之置晶側與球側線路層，形成一四層無核層 6係可為鎳金層。，-、肩層65、6 亦可亍(上S、)下，之線路增層結構製作3 ◦: 屏之蠄 四層基板上直接進行上、下兩 胃之線路増層結構製作，其至少包含下列步驟： 4圖所= = 五介電層301 :如第2 第—線路層5 Θ與該第一介電層 3 1上直接壓合或貼 以層 第四線路層60與該第三介電J =二及於該 合一第五介電層68，· 層47上直接壓合或貼 如第2=)-形成複數個第十、十-開口 3〇2: 電声6 7上π:、:Γ雷射鑽孔之方式分別於該第四介 第：二二T 十開°69,以顯露其下之 第-線路層5 9，以及於該第 數個第十-開口 70，以顯露二電層68上形成複 〇,其中，該複數個第十：十：下之第四線路層6 做開鋼窗後再經由雷射鑽孔、亦係先 之方式形成； 次係直接以雷射鑽孔 14 200924128 (u3)形成第—、二晶種層303 :如第2 6圖所示’以無電電鍍與電鍍之方式分別於該第四介 電層67與複數個第十開口69表面形成一第—晶種 層7 1 ’以及於五介電層6 8與複數個第十一開 口 70表面形成一第二晶種層72，其中，該第一、 二晶種層7 1、7 2係可為金屬銅層； (U 4 )貼合第七、八阻層3 〇 4 :如第2 7 圖所示’分別於該第-晶種層7 :上貼合—第七阻層 73，以及於該第二晶種層72上貼合—第八阻声^ 4 ; 曰, u )形成複數個第十二、十三開口 3 〇 如第2 8圖所示，以曝光及顯影之方式分別於該第七 第十二開口 7 ς ;=二=;::=_個 (h 並顯露該第 .^U6)無電錢與仙n九金屬 6 .如第29圖所示，以無電電鍍與電鍍之方 八 別於複數個第十二開口中之第一晶種層^ 工，分 第八金屬層77，以及於複數個第二 形成— 不丁二開口中之坌一 晶種層72上形成一第九金屬層了8; — :如第3 〇 以分別顯露 (u7)移除第七、八阻層3q7 圖所示’移除該第七阻層及該第八阻層， 其下之第一、二晶種層7 1、7 2 ;以及 15 200924128 (u 8)形成具圖案化線路及電性連接之六層 基板3 〇 8 :如第3 1圖所示，以蝕刻之方式分別^ 除戎顯露之第一晶種層，並使該第四介電層6 7上之 第 BB種層及弟八金屬層形成一第五線路層79，以 及移除該顯露之第二晶種層，並使該第五介電層6 8 上之第二晶種層及第九金屬層形成一第六線路層8 〇。於此，獲得上下各一層之線路增層結構，形成一 具圖案化線路及電性連接之六層基板5。 本發明亦可在此六層基板之結構上繼續增加線路 增層結構，以形成具更多雙數多層之封裝基板；亦或 可直接進行該步驟（T)之置晶側與球側線路層電性 連接墊製作。 五介電層3 8、4 7 其中，該第 7、6 8 係可為 ABF ( Ajinomoto Build-up Film )、笨 裱^烯（BenZOCyCl〇_buthene，BCB)、雙馬來亞醯胺^ 二氮雜苯樹脂（Bismaleimide Triazine, BT )、環氧樹脂 板（FR4、FR5 )、聚醯亞胺（p〇iyimide，）、聚四氟 乙烯（Poly(tetra-f丨oroethy丨ene)，PTFE)或環氧樹脂及 玻螭纖維所組成之一者；該第一〜八阻層3 43 5、 4 2、4 3、5 5、5 6、7 3、7 4亦可以印刷或 旋轉塗佈之方式所為之乾膜或顧之高感光性光阻； 該第—〜九金屬層32、33、39、41、48、 51 ' 52、77 ' 78係可為銅或其它等效金屬； 16 200924128 該第—〜七金屬層3 2、3 3、3 9、4 1、4 8、 52及該第-、二晶種層了1、72之移除方 >係可為蝕刻或其它等效方法；該第—〜 4、35、42、43、55、56、73、；2 移除方法係可為剥離或其它等效方法。 當本發明於運用時，係先以光學微影及蝕刻之方 式於-雙面基板上製作一單層線路，藉此以做為增層 結構之電性連接塾，之後再於該單層線路連接塾以壓 =之方式形成第一增層線路’以形成一具三層金屬結 之電路板，且其中兩層係已完成圖案 過複數個電鍍盲孔而產生電性連接。接著，再於^ 一增層線路結構上形成第二增層線路，同時使原未圖 案化線路之金屬層#彡& $ ’、 蜀嘈办成弟二增層線路，成為一且 化線路且電性導通之四芦 勹圖案 層基板，並可進一步以該四層 :反之上 '下層分別做為增層結構之電性連接墊，亦 或係作為置晶側與球側之完整線路， 側、球側及中間各声之古斗日^ 逆茌，、置曰日 埋孔所導通。藉此:使：:::！複數個電鑛盲孔或 所製作之半導體多層封裝基板結構，係可 =r:=—_ 之封裝基板，進上=貧除需求形成雙數多層 製作成本之目;ί有效達到降低成品板厚度及減少 17 200924128 綜上㈣，本發㈣—種，可有収善 種缺點，係可完成一半導體多層封裝基板結構，包Γ 兩層具圖案化線路及已完成圖案化線路製程之置晶側 與球側線路層等雙數多層結構’可有效改善超薄核層 基板板彎起問題及簡化傳統增層線路板之製作流程， 係-個可依實際需求形成雙數多層之封裝基板，並可 有效達到降低成品板厚度及減少製作成本之目的，進 而使本發明之産生能更進步、更實用、更符合使用者 =所須，確已符合發明專财請之要件，爰依 專利申請。 惟以上所述者，僅為本發明之較佳實施例而已， 當不能以此限定本發明實施之範圍；&，凡依本發明 申請專利範®及發明說明書内容所作之簡單的等效變 化與修飾’皆應仍屬本發明專利涵蓋之範圍内。 200924128 【圖式簡單說明】 第1圖，係本發明之製作流程示意圖。 第2圖’係本發明之雙面基板剖面示意圖。 第3圖，係本發明之兩層基板（一）剖面示意圖。 第4圖’係本發明之兩層基板（二）剖面示意圖。 第5圖’係本發明之兩層基板（三）剖面示意圖。 第6圖’係本發明之兩層基板（四）剖面示意圖。 第7圖’係本發明之三層基板（五）剖面示意圖。 第8圖，係本發明之三層基板（六）剖面示意圖。 第9圖，係本發明之三層基板（七）剖面示意圖。 第1 0圖’係本發明之三層基板（八）刮面示意圖。 第1 1圖’係本發明之三層基板（九）剖面示意圖。 第1 2圖’係本發明之三層基板（十）剖面示意圖。 第1 3圖’係本發明之三層基板（十一）剖面示意圖。 第1 4圖’係本發明之四層基板（一）剖面示意圖。 第1 5圖’係本發明之四層基板（二）剖面示意圖。 第1 6圖’係本發明之四層基板（三）剖面示意圖。 第1 7圖，係本發明之四層基板（四）剖面示意圖。 第1 8圖’係本發明之四層基板（五）剖面示意圖。 第1 9圖’係本發明之四層基板（六）剖面示意圖。 19 200924128 第2 0圖，係本發明之四層基板（七）剖面示意圖。 第2 1圖，係本發明之置晶側與球側線路層（一）剖 面示意圖。 第2 2圖，係本發明之置晶側與球側線路層（二）剖 面示意圖。 第2 3圖，係本發明之實施置晶側與球側線路層（三） 剖面示意圖。 第2 4圖，係本發明之上下兩層線路增層結構（一） 剖面示意圖。 第2 5圖，係本發明之上下兩層線路增層結構（二） 剖面示意圖。 第2 6圖，係本發明之上下兩層線路增層結構（三） 剖面示意圖。 第2 7圖，係本發明之上下兩層線路增層結構（四） 剖面示意圖。 第2 8圖，係本發明之上下兩層線路增層結構（五） 剖面示意圖。 第2 9圖，係本發明之上下兩層線路增層結構（六） 剖面示意圖。 第3 0圖，係本發明之上下兩層線路增層結構（七） 剖面示意圖。 第3 1圖，係本發明之上下兩層線路增層結構（八） 20 200924128 剖面示意圖。 第3 2圖，係習用有核層封裝基板之剖面示意圖。 第3 3圖’係f用之實施線路增層（-)剖面示意圖。 第3 4圖’係習用之實施線路增層（二)剖面示意圖。 第3 5圖係驾用之實施線路增層（三）剖面示意圖。 第36圖’係、習用之實施線路增層（四）剖面示意圖。 第3 7圖’係另一習用有核屌 力〜層封裝基板之剖面示意圖。 第3 8圖，係習用之第一绩玫 弟線路增層結構剖面示意圖。 第3 9圖，係習用之第二路掸 【主要元件符號說明】 g層結構剖面示意圖。 (本發明部分） 步驟（A)〜（U) 11〜 2 9 3 3 0 8 步驟（tl)〜（t3) 29l 步驟（ul)〜（u8) 3〇1 雙面基板1 三層基板2a、2b 四層基板3 四層無核層多層封裝基板4 六層基板5 第一介電層3 1 第一、二金屬層32、33 200924128 第一、二阻層34、35 第一開口 3 6 第一線路層3 7 第一、二面 37a、37b 第二介電層3 8 第三金屬層3 9 第二開口 4 0 第四金屬層4 1 第一雷射盲孔4 6 第三、四阻層42、43 第三開口 4 4 第三線路層4 5 第三介電層4 7 第五金屬層4 8 第四、五開口 49、50 第六、七金屬層51、52 第二、三雷射盲孔5 3、54 第五、六阻層5 5、56 第六、七開口 57、58 第二、四線路層59、60 22 200924128 第一、二防焊層61、62 第八、九開口 6 3、6 4 第一、二阻障層6 5、66 第四、五介電層67、68 第十、十一開口 69、70 第一、二晶種層71、72 第七、八阻層7 3、74 第十二、十三開口 7 5、7 6 第八、九金屬層77、78 第五、六線路層79、80 (習用部分） 第一、二線路增層結構8 a、8 b 核心基板8 1 芯層8 1 1 線路層8 1 2 電鍍導通孔813 第一、二介電層8 2、8 9 第一、二開口 83、86 晶種層8 4 圖案化阻層8 5 23 200924128 第一、二圖案化線路層8 7、9 0 導電盲孔8 8 第一、二線路增層結構9 a、9 b 核心基板9 1 樹脂塞孔9 1 1 電鍍通孔9 1 2 第一、二介電層9 2、9 4 第一、二圖案化線路層93、95 24Turning on, thereby completing a coreless multi-layer package substrate. The metal layer forms a four-layer substrate electrically connected to the third build-up line, and? [Embodiment] Please refer to FIG. 1 to FIG. 3, which are schematic diagrams showing a manufacturing process of the present invention, a schematic cross-sectional view of a double-sided substrate of the present invention, and a schematic cross-sectional view of a two-layer substrate (1) of the present invention. A schematic view of a two-layer substrate (2) of the present invention, a schematic view of a two-layer substrate of the present invention, a cross-sectional view of a two-layer substrate of the present invention, a cross-sectional view of a two-layer substrate of the present invention, a cross-sectional view of a two-layer substrate of the present invention, and a present invention. Schematic diagram of three-layer substrate (six), cross-sectional view of three-layer substrate (seven) of the present invention, cross-sectional view of three-layer substrate (eight) of the present invention, cross-sectional view of three-layer substrate (nine) of the present invention, and third aspect of the present invention Schematic diagram of a layer substrate (ten), a schematic view of a three-layer substrate (11) of the present invention, a schematic view of a four-layer substrate of the present invention, a schematic view of a four-layer substrate of the present invention, and a four-layered structure of the present invention Schematic diagram of a substrate (3), a schematic view of a four-layer substrate (four) of the present invention, a schematic view of a four-layer substrate of the present invention (V), and a fourth aspect of the present invention Schematic diagram of a layer substrate (six), a schematic diagram of a four-layer substrate (seven) having a patterned and electrically connected structure according to the present invention, a schematic diagram of a cross section of the crystal side and a ball-side wiring layer (a) of the present invention, and a crystal of the present invention. Schematic diagram of the side and ball side circuit layer (2), the crystal side of the present invention, the upper and lower layers of the present invention, the upper and lower layers of the present invention, the upper and lower layers of the present invention, the upper and lower layers, and the lower and lower layers of the present invention. Schematic diagram of the upper and lower layers and the ball-side circuit layer (3), the upper and lower layers of the present invention, the layered structure (-), the cross-sectional structure of the line, the line-added structure (2), the cross-section, the line, the layer-added structure (3) Structure of the build-up structure (IV) Schematic diagram of the profile, structure of the line-added structure (5) Schematic diagram of the cross-section of the line (6) Section of the section: =: (7) Schematic diagram of the section and above the invention = Line-added structure (8) #一_^ As shown in the figure, the method for manufacturing the seed layer circuit board of the present invention comprises at least the following steps: Substrate 10: As shown in Fig. 2, select - metal w/1 electricity °31, a double-sided substrate of the first metal layer 3 2 and the first metal layer 33; (B) a first and second resist layer 1 1 bonded to the first metal layer 32 of the f-plane substrate as shown in FIG. Lamination: the second resistance layer is formed on the second metal layer 3 3 of the double-sided substrate, and the second resist layer 3 5 is attached to the king cover layer; (C) a plurality of first openings 1 2 are formed. ·· As shown in Fig. 4, the exposure and development method is 扃4 S kg, and a plurality of brothers 36 are formed on the first opening 3 β e 3 4 to reveal the underlying metal layer 32; (D) Removing the first metal layer 13: as shown in FIG. 5, removing the first under the first-opening σ36 by the metal layer 3 = 200924128 to form a first circuit layer 丄4 ·· The resist layer and the 哕筮 _ _ β hang b diagram, the shift has a metal layer formed as an electrical connection pad - a circuit layer 3 7; (F) a circuit board forming a two-layer structure, After the first post-expansion Q π 13 · as shown in FIG. 7 , the sluice layer 37 and the first slab bonding or lamination are the same as the first dielectric layer 3 1 Layer 38 and a second full-scale second dielectric wood - genus layer 3 9 'Forms a second screen last name 4 substrate 2a; a small layer of structure circuit (G) forms a plurality of second openings 6 : such as =: holes in the third metal layer 39 and the second: electricity two Forming a plurality of second openings 40 to expose a first surface 37a of the underlying surface layer 37, wherein the plurality of second openings 40 are first opened by a copper window and then passed through a laser drill The hole is formed by laser drilling; straight (H) electroless plating and electroplating of the fourth metal layer 17: as shown in FIG. 9, in the second opening and the electroless plating and electroplating a fourth metal layer 4 1 is formed on the circuit layer 37 and the third metal layer 39. The fourth metal layer 4 is electrically connected to the 5th first circuit layer 37, and the layer is The connection between the layers is conducted by a plurality of first laser blind holes 46 of the electric ore; 200924128 (" fitting the third and fourth resist layers 18: as shown in the first figure, respectively Bonding on the four metal layers 41 and adhering the second metal layer 33 to the second metal layer 33 in a completely covered manner; ^ 1 (J) forming a plurality of third openings 19: as shown, by exposure and development The third resistance is a plurality of third openings 44 to reveal the fourth metal layer underneath to form a complex (K) to remove the third and fourth metal displays, and to move by the last name (4) as shown in FIG. The third gold substrate under the opening and the fourth metal layer opening 44 is formed by: three layers electrically connected to the C-type layer to form a third circuit layer 45, and the two layers are patterned and electrically connected. (M) press-bonding the third dielectric layer and the fifth metal layer 2, and then re-compressing the third dielectric layer 47 and the second dielectric layer 47 and a fifth metal layer 48 曰; a (N) forming a plurality of fourth and fifth openings 2 3 : as shown in Fig. 5, in the manner of laser drilling, respectively, in the second metal layer 3 3 and 2 A plurality of fourth openings 4 9 ′ are formed on a dielectric layer 3 1 to expose a second surface 3 of the patterned first circuit layer 37 7200924128, a fifth metal layer 48 and the third dielectric layer Forming five openings 5◦ to reveal the patterned third circuit layer 45, wherein the plurality of fourth and fifth openings 4 9 and $ 0 can be opened by a copper window and then drilled through a laser. Or direct laser Drilling is formed; (〇) electroless f plating and f plating sixth and seventh metal layers 24: as in the second: 'in electroless plating and electroplating in the plural = opening and the second metal layer 33 Forming a sixth metal plurality of fifth openings and the fifth metal layer 4 - the seventh metal layer 52, wherein the connection between the layers = a plurality of second and third laser blind holes 53 by electroplating, "The fifth layer and the sixth resist layer 25 are attached to each other. As shown in the figure, a fifth resist layer 55 is attached to the sixth metal layer 51, and the seventh metal layer is bonded to the seventh metal layer 51. 52 is attached to a sixth resist layer 56; (Q) forming a plurality of sixth and seventh openings 2 6 : as shown in FIG. 18 'by exposure and development respectively on the fifth resist layer 55 :: a plurality of sixth openings 57 to expose the sixth metal ruthenium 5 1 therebelow and a plurality of seventh openings 5 8 ′ formed on the sixth resistive layer 56 to expose the seventh metal layer 5 2 therebelow; (R) removing the second, fifth, sixth, and seventh metal layers 2 7 : as shown in FIG. 9 , removing the second metal layers 3 3 and 6 below the sixth opening 5 7 in the manner of (4) Metal layer 5 1, and removed 12 200924128 The fifth metal layer 48 and the seventh metal layer 5 2 under the seventh opening 58; (S) completing four layers of a four-layer substrate with a rounded circuit and electrical connection. 8 as shown in Fig. 2 The fifth resist layer is removed, the second and sixth metal layers are formed into a patterned second circuit layer 5 9 ', and the sixth resist layer is removed to form the fifth and seventh metal layers. - The patterned fourth circuit layer 6 〇. So far - four layers of patterned circuit and electrically connected four-layer substrate 3, and can be directly carried out step (D) or step (U); (T) for the crystal side and ball side circuit layer electrical connection pad Fabrication 2 9 · Performing - the crystallizing side and the ball side circuit layer are electrically connected to at least the following steps: t 1: > coating the first and second solder mask 291: as shown in Fig. 2, respectively The second circuit layer 59 and the first solder mask layer 61 for the first-dielectric acoustic two m-layer insulation protection are provided with a layer of insulation protection on the (four) four-circuit layer 60 and the third dielectric layer 47. The second solder mask layer 6 2 ; y 2) forms a plurality of eighth and nine openings 2": the female shows 'in the form of exposure and development respectively in the =: forming a plurality of eighth openings 63, and in the first: ¥曰6 2 forms a plurality of ninth openings D 6 4. By means of the line build-up structure as an electrical connection pad; S ”,, and 13 200924128 road layer 2 (1 3) complete the patterned side with a complete pattern And the ball side line port 6 9 3 · as shown in Fig. 2 3, respectively, in the plurality of eighth opening openings 6: = : the first: the barrier layer 65 'and the plurality of ninth mosquitoes 66. Here, the crystallized side and the ball side circuit layer having the complete masses are obtained, and a four-layer non-nuclear layer is formed to form a nickel-gold layer. , -, the shoulder layer 65, 6 can also be 亍 (upper S,), the line build-up structure is made 3 ◦: The screen is made on the four-layer substrate directly on the upper and lower stomach lines, at least The following steps are included: 4 Figure == Five dielectric layers 301: as the second first - circuit layer 5 Θ is directly pressed or bonded to the first dielectric layer 3 1 and the fourth wiring layer 60 and the third Dielectric J = 2 and on the fifth dielectric layer 68, the layer 47 is directly pressed or pasted as the second =) - forming a plurality of tenth, ten - openings 3 〇 2: electroacoustic 6 7 The π:,: Γ laser drilling method is respectively in the fourth medium: two two T ten open ° 69 to reveal the next - the circuit layer 5 9, and the tenth - opening 70 To form a reticular layer on the second electrical layer 68, wherein the plurality of tenth: ten: the fourth circuit layer 6 is formed by opening a steel window and then being drilled by a laser, which is also formed first; The first and second seed layers 303 are formed directly by the laser drilling 14 200924128 (u3): as shown in FIG. 26, the fourth dielectric layer 67 and the plurality of tenth portions are respectively electrolessly plated and plated. The surface of the opening 69 forms a first - a seed layer 7 1 ′ and a second seed layer 72 formed on the surface of the fifth dielectric layer 68 and the plurality of eleventh openings 70 , wherein the first and second seed layers 7 1 , 7 2 a metal copper layer; (U 4 ) is bonded to the seventh and eighth resist layers 3 〇 4 : as shown in FIG. 2 7 'attached to the first seed layer 7 : a seventh resist layer 73 , and The second seed layer 72 is bonded to the eighth sound-blocking layer 4; 曰, u) to form a plurality of twelfth and thirteenth openings 3, as shown in Fig. 28, respectively, by exposure and development The seventh twelfth opening 7 ς ;= two =;::=_ (h and revealing the first. ^U6) no electricity and fairy n nine metal 6. As shown in Figure 29, with electroless plating and plating The eighth layer is formed by the first seed layer layer of the plurality of twelfth openings, divided into the eighth metal layer 77, and formed on the first seed layer 72 of the plurality of second forming-not-two openings a ninth metal layer is 8; - : as in the third 〇 to reveal (u7) respectively, the seventh and eighth resistive layers 3q7 are removed as shown in the figure of 'removing the seventh resistive layer and the eighth resistive layer, First and second seed layers 7 1 , 7 2 ; and 15 200924128 (u 8) a six-layer substrate with patterned lines and electrical connections 3 〇8: as shown in FIG. 31, the exposed first seed layer is removed by etching, and the fourth dielectric layer is made 7 7 Forming a fifth circuit layer 79 on the BB layer and the eighth layer, and removing the exposed second seed layer, and the second seed layer and the fifth layer on the fifth dielectric layer The nine metal layers form a sixth circuit layer 8 〇. Here, the line build-up structure of each of the upper and lower layers is obtained, and a six-layer substrate 5 having a patterned line and an electrical connection is formed. The invention can also continue to increase the line build-up structure on the structure of the six-layer substrate to form a package substrate with more double-numbered layers; or directly perform the silicon-side and ball-side circuit layers of the step (T) Made of sexual connection pads. Five dielectric layers 3 8 and 4 7 wherein the seventh and sixth systems can be ABF (Ajinomoto Build-up Film), BenzoCyCl〇_buthene (BCB), and Bismaleamine II. Amine benzene resin (Bismaleimide Triazine, BT), epoxy resin sheet (FR4, FR5), polyfluorene (p〇iyimide), polytetrafluoroethylene (Poly(tetra-f丨oroethy丨ene), PTFE) Or one of epoxy resin and glass fiber; the first to eight resistive layers 3 43 5, 4 2, 4 3, 5 5, 5 6 , 7 3, 7 4 can also be printed or spin coated The dry film or the high sensitivity photoresist of the method; the first to the nine metal layers 32, 33, 39, 41, 48, 51 '52, 77 '78 may be copper or other equivalent metal; 16 200924128 The first to the seventh metal layers 3 2, 3 3, 3 9 , 4 1 , 4 8 , 52 and the first and second seed layers 1, 72 removed side > may be etching or other equivalent Method; the first to ~ 4, 35, 42, 43, 55, 56, 73,; 2 removal method can be stripping or other equivalent methods. When the present invention is applied, a single layer line is formed on the double-sided substrate by optical lithography and etching, thereby using the electrical connection port as a build-up structure, and then on the single-layer line. The connection layer is formed by pressing the first build-up line to form a circuit board having three metal layers, and two of the layers have been patterned to form a plurality of plated blind holes to make an electrical connection. Then, a second build-up line is formed on the layer structure of the build-up layer, and at the same time, the metal layer #彡& $' of the original unpatterned line is formed into a second layer of the line, and becomes a line. And electrically conducting the four reed pattern layer substrate, and further adopting the four layers: on the contrary, the upper layer is respectively used as an electrical connection pad of the build-up structure, or is used as a complete line of the crystallized side and the ball side. The side of the ball, the side of the ball and the middle of the sound of the ancient day ^ reverse 茌, set the hole buried in the day. Take this: Make ::::! A plurality of electric ore blind holes or a fabricated semiconductor multi-layer package substrate structure, which is a package substrate of =r:=-_, which is required to form a plurality of multi-layer fabrication costs; ί effectively reduces the thickness of the finished board and Decrease 17 200924128 In summary (4), this issue (4) - can provide a variety of shortcomings, can complete a semiconductor multi-layer package substrate structure, including two patterned circuits and the patterned side of the patterned circuit process The double-layered structure such as the ball-side circuit layer can effectively improve the bending problem of the ultra-thin core substrate plate and simplify the production process of the conventional layer-added circuit board, and can form a plurality of multi-layer package substrates according to actual needs, and can effectively achieve The purpose of reducing the thickness of the finished board and reducing the production cost, so that the production of the invention can be more advanced, more practical, more in line with the user = required, has indeed met the requirements of the invention of the special wealth, according to the patent application. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; & simple equivalent changes made in accordance with the contents of the present invention and the description of the invention And the modifications 'should be within the scope of the invention patent. 200924128 [Simplified description of the drawings] Fig. 1 is a schematic diagram of the production process of the present invention. Fig. 2 is a schematic cross-sectional view showing a double-sided substrate of the present invention. Fig. 3 is a schematic cross-sectional view showing a two-layer substrate (1) of the present invention. Fig. 4 is a schematic cross-sectional view showing a two-layer substrate (2) of the present invention. Fig. 5 is a schematic cross-sectional view showing a two-layer substrate (3) of the present invention. Fig. 6 is a schematic cross-sectional view showing a two-layer substrate (four) of the present invention. Fig. 7 is a schematic cross-sectional view showing a three-layer substrate (f) of the present invention. Figure 8 is a schematic cross-sectional view of a three-layer substrate (six) of the present invention. Figure 9 is a schematic cross-sectional view showing a three-layer substrate (seven) of the present invention. Fig. 10 is a schematic view showing the shaving surface of the three-layer substrate (eight) of the present invention. Fig. 1 is a schematic cross-sectional view showing a three-layer substrate (nine) of the present invention. Fig. 2 is a schematic cross-sectional view showing a three-layer substrate (ten) of the present invention. Fig. 1 is a schematic cross-sectional view showing a three-layer substrate (11) of the present invention. Fig. 14 is a schematic cross-sectional view showing a four-layer substrate (1) of the present invention. Fig. 15 is a schematic cross-sectional view showing a four-layer substrate (2) of the present invention. Fig. 16 is a schematic cross-sectional view showing a four-layer substrate (3) of the present invention. Figure 17 is a schematic cross-sectional view of a four-layer substrate (four) of the present invention. Figure 18 is a schematic cross-sectional view of a four-layer substrate (f) of the present invention. Figure 19 is a schematic cross-sectional view of a four-layer substrate (six) of the present invention. 19 200924128 Figure 20 is a schematic cross-sectional view of a four-layer substrate (seven) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystal side and the ball side wiring layer (1) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystal side and the ball side wiring layer (2) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystallizing side and the ball side wiring layer (3) in the practice of the present invention. Figure 24 is a schematic cross-sectional view of the two-layer line build-up structure (1) above and below the present invention. Figure 25 is a schematic cross-sectional view of the two-layer line build-up structure (2) above and below the present invention. Figure 26 is a schematic cross-sectional view of the three-layer line build-up structure (3) above and below the present invention. Figure 27 is a schematic cross-sectional view of the two-layer line build-up structure (4) above and below the present invention. Figure 28 is a schematic cross-sectional view of the two-layer line build-up structure (5) above and below the present invention. Figure 29 is a schematic cross-sectional view of the two-layer line build-up structure (6) above and below the present invention. Figure 30 is a schematic cross-sectional view of the two-layer line build-up structure (7) above and below the present invention. Figure 31 is a schematic diagram of a cross-sectional structure of the upper and lower layers of the present invention (8) 20 200924128. Figure 3 is a schematic cross-sectional view of a conventional nuclear-coated substrate. Figure 3 3 is a schematic diagram of a cross-sectional (-) cross-section of the line. Figure 3 is a schematic view of the cross-section of the circuit (2). Figure 35 is a schematic diagram of the cross-section of the circuit (3). Figure 36 is a schematic cross-sectional view of the line-adding layer (4). Figure 7 is a schematic cross-sectional view of another conventional nucleating force ~ layer package substrate. Figure 38 shows a schematic diagram of the structure of the first layer of the Meixian line. Figure 39 shows the second way of the 掸 [Description of the main components] Schematic diagram of the g-layer structure. (Part of the Invention) Step (A) to (U) 11 to 2 9 3 3 0 8 Step (tl) to (t3) 29l Step (ul) to (u8) 3〇1 Double-sided substrate 1 Three-layer substrate 2a, 2b four-layer substrate 3 four-layer coreless multi-layer package substrate 4 six-layer substrate 5 first dielectric layer 3 1 first and second metal layers 32, 33 200924128 first and second resistance layers 34, 35 first opening 3 6 a circuit layer 3 7 first, two sides 37a, 37b second dielectric layer 3 8 third metal layer 3 9 second opening 4 0 fourth metal layer 4 1 first laser blind hole 4 6 third, fourth resistance Layer 42, 43 third opening 4 4 third wiring layer 4 5 third dielectric layer 4 7 fifth metal layer 4 8 fourth, fifth opening 49, 50 sixth, seventh metal layer 51, 52 second, three thunder Blind hole 5 3, 54 fifth, sixth resistive layer 5 5, 56 sixth, seventh opening 57, 58 second, fourth circuit layer 59, 60 22 200924128 first and second solder mask 61, 62 eighth, nine Openings 6 3, 6 4 first and second barrier layers 6 5, 66 fourth and fifth dielectric layers 67, 68 tenth, eleven openings 69, 70 first and second seed layers 71, 72 seventh, eighth Resistive layer 7 3, 74 12th, thirteenth opening 7 5, 7 6 eighth, nine metal layer 77, 78 Fifth and sixth circuit layers 79, 80 (conventional part) First and second line build-up structure 8 a, 8 b Core substrate 8 1 Core layer 8 1 1 Circuit layer 8 1 2 Plating via 813 First and second Electrical layer 8 2, 8 9 First and second openings 83, 86 Seed layer 8 4 Patterned resist layer 8 5 23 200924128 First and second patterned circuit layers 8 7 , 9 0 Conductive blind holes 8 8 First and second Line build-up structure 9 a, 9 b core substrate 9 1 resin plug hole 9 1 1 plated through hole 9 1 2 first and second dielectric layers 9 2, 9 4 first and second patterned circuit layers 93, 95 24