TW200921773A - Method for producing a semiconductor wafer with a polished edge - Google Patents

Method for producing a semiconductor wafer with a polished edge Download PDF

Info

Publication number
TW200921773A
TW200921773A TW097143873A TW97143873A TW200921773A TW 200921773 A TW200921773 A TW 200921773A TW 097143873 A TW097143873 A TW 097143873A TW 97143873 A TW97143873 A TW 97143873A TW 200921773 A TW200921773 A TW 200921773A
Authority
TW
Taiwan
Prior art keywords
polishing
edge
polished
semiconductor wafer
sided
Prior art date
Application number
TW097143873A
Other languages
English (en)
Chinese (zh)
Inventor
Klaus Roettger
Werner Aigner
Makoto Tabata
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of TW200921773A publication Critical patent/TW200921773A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
TW097143873A 2007-11-15 2008-11-13 Method for producing a semiconductor wafer with a polished edge TW200921773A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102007056122A DE102007056122A1 (de) 2007-11-15 2007-11-15 Verfahren zur Herstellung einer Halbleiterscheibe mit polierter Kante

Publications (1)

Publication Number Publication Date
TW200921773A true TW200921773A (en) 2009-05-16

Family

ID=40576892

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097143873A TW200921773A (en) 2007-11-15 2008-11-13 Method for producing a semiconductor wafer with a polished edge

Country Status (7)

Country Link
US (1) US20090130960A1 (de)
JP (1) JP2009124153A (de)
KR (1) KR20090050939A (de)
CN (1) CN101434047A (de)
DE (1) DE102007056122A1 (de)
SG (1) SG152978A1 (de)
TW (1) TW200921773A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393183B (zh) * 2009-06-24 2013-04-11 Siltronic Ag 雙面拋光半導體晶圓的方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010162624A (ja) * 2009-01-13 2010-07-29 Ebara Corp 研磨装置および研磨方法
DE102009030295B4 (de) * 2009-06-24 2014-05-08 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
DE102009030294B4 (de) * 2009-06-24 2013-04-25 Siltronic Ag Verfahren zur Politur der Kante einer Halbleiterscheibe
DE102009030296B4 (de) * 2009-06-24 2013-05-08 Siltronic Ag Verfahren zur Herstellung einer epitaxierten Siliciumscheibe
DE102009051008B4 (de) * 2009-10-28 2013-05-23 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
DE102010014874A1 (de) * 2010-04-14 2011-10-20 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
JP2012009550A (ja) * 2010-06-23 2012-01-12 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2012019126A (ja) * 2010-07-09 2012-01-26 Disco Abrasive Syst Ltd ウエーハの加工方法
DE102013204839A1 (de) * 2013-03-19 2014-09-25 Siltronic Ag Verfahren zum Polieren einer Scheibe aus Halbleitermaterial
DE102013210057A1 (de) 2013-05-29 2014-12-04 Siltronic Ag Verfahren zur Politur der Kante einer Halbleiterscheibe
CN104526493A (zh) * 2014-11-18 2015-04-22 天津中环领先材料技术有限公司 一种单晶硅晶圆片边缘抛光工艺
CN108214110A (zh) * 2016-12-14 2018-06-29 有研半导体材料有限公司 一种硅抛光片边缘加工工艺

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3828176B2 (ja) 1995-02-28 2006-10-04 コマツ電子金属株式会社 半導体ウェハの製造方法
TW308561B (de) * 1995-08-24 1997-06-21 Mutsubishi Gum Kk
JP2000077372A (ja) * 1998-08-31 2000-03-14 Sumitomo Metal Ind Ltd 気相成長用半導体ウェーハの製造方法
JP2000114216A (ja) * 1998-10-01 2000-04-21 Sumitomo Metal Ind Ltd 半導体ウェーハの製造方法
DE10007390B4 (de) 1999-03-13 2008-11-13 Peter Wolters Gmbh Zweischeiben-Poliermaschine, insbesondere zur Bearbeitung von Halbleiterwafern
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
US6514423B1 (en) 2000-02-22 2003-02-04 Memc Electronic Materials, Inc. Method for wafer processing
JP2006142388A (ja) 2004-11-16 2006-06-08 Nihon Micro Coating Co Ltd 研磨テープ及び方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393183B (zh) * 2009-06-24 2013-04-11 Siltronic Ag 雙面拋光半導體晶圓的方法

Also Published As

Publication number Publication date
DE102007056122A1 (de) 2009-05-28
JP2009124153A (ja) 2009-06-04
KR20090050939A (ko) 2009-05-20
US20090130960A1 (en) 2009-05-21
CN101434047A (zh) 2009-05-20
SG152978A1 (en) 2009-06-29

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