US20090130960A1 - Method For Producing A Semiconductor Wafer With A Polished Edge - Google Patents

Method For Producing A Semiconductor Wafer With A Polished Edge Download PDF

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Publication number
US20090130960A1
US20090130960A1 US12/262,202 US26220208A US2009130960A1 US 20090130960 A1 US20090130960 A1 US 20090130960A1 US 26220208 A US26220208 A US 26220208A US 2009130960 A1 US2009130960 A1 US 2009130960A1
Authority
US
United States
Prior art keywords
polishing
edge
semiconductor wafer
polished
cloth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/262,202
Other languages
English (en)
Inventor
Klaus Roettger
Werner Aigner
Makoto Tabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AIGNER, WERNER, TABATA, MAKOTO, ROETTGER, KLAUS
Publication of US20090130960A1 publication Critical patent/US20090130960A1/en
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02024Mirror polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02021Edge treatment, chamfering

Definitions

  • the patent application relates to a method for producing a semiconductor wafer with a polished edge, which method involves using a polishing cloth containing fixed abrasive for polishing the edge.
  • the polishing of the edge by means of such a polishing cloth is abbreviated to “FA” polishing hereinafter.
  • the machining of the edge of a semiconductor wafer is receiving increasing attention.
  • a smooth edge having a predetermined edge form is required.
  • the edge form is usually produced by grinding the rough edge of a semiconductor wafer sliced for a crystal.
  • cloth polishing By comparison with this edge polishing, referred to hereinafter as cloth polishing for short, FA polishing has the advantage of obviating the comparatively complicated handling of slurry and enabling higher throughputs. This advantage is opposed by the disadvantage that the polished edge is less smooth.
  • U.S. Pat. No. 6,514,423 B1 proposes etching the edge after the FA polishing in order to reduce its roughness.
  • a method for producing a semiconductor wafer with a polished edge comprising polishing at least one side of the semiconductor wafer; and polishing the edge of the polished semiconductor wafer, wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.
  • the invention exploits the unexpected advantage that the form of the edge of the polished semiconductor wafer can be corrected by means of an FA polishing, but not by means of a cloth polishing.
  • the method is applied to a semiconductor wafer whose edge has already undergone a shaping machining step, preferably a grinding step, but whose edge has not yet been polished.
  • the method begins with the polishing of at least one side of the semiconductor wafer. This involves a single-side polishing or a double-side polishing. A double-side polishing carried out simultaneously is preferred. A suitable machine for double-side polishing is described for example in DE 100 07 390 A1.
  • the semiconductor wafer lies in a cutout, provided therefor, in a carrier acting as a guide cage and between an upper and a lower polishing plate.
  • At least one polishing plate and the carrier are rotated, and the semiconductor wafer moves, with a polishing agent being supplied, on a path predetermined by a rolling curve, relative to the polishing plates covered with polishing cloth.
  • the polishing pressure with which the polishing plates press on to the semiconductor wafer and the duration of the polishing are parameters which crucially codetermine the material removal brought about by means of the polishing.
  • the polishing of at least one side of the semiconductor wafer is preferably performed as removal polishing, that is to say with the aim of removing material with a thickness of at least 5 ⁇ m from the semiconductor wafer side to be polished.
  • a polishing cloth containing fixed abrasive, for example particles of silicon carbide, silicon dioxide or diamond, is used during the FA polishing.
  • the FA polishing is effected in the presence of a liquid polishing agent, for example in the presence of water.
  • a liquid polishing agent for example in the presence of water.
  • a polishing cloth having particularly fine abrasive preferably with a mesh size of not less than 4000, that is to say with an average particle diameter of not more than 5 ⁇ m, more preferably not more than 4 ⁇ m.
  • a multistage FA polishing in the course of which polishing is effected using finer and finer abrasive and which is concluded with the fine abrasive is also particularly suitable.
  • Such a polishing step sequence and suitable polishing devices are described for example in US 2006/0252355 A1.
  • the FA polishing is performed in the presence of a slurry containing free abrasive, for example colloidal silicon dioxide or cerium oxide.
  • a slurry containing free abrasive for example colloidal silicon dioxide or cerium oxide.
  • a third embodiment involves carrying out firstly an FA polishing in the presence of a liquid polishing agent and then a cloth polishing in the presence of a slurry containing free abrasive, for example colloidal silicon dioxide or cerium oxide.
  • a slurry containing free abrasive for example colloidal silicon dioxide or cerium oxide.
  • the average particle diameter of the fixed abrasive in the polishing cloth can be larger than when the subsequent cloth polishing is dispensed with.
  • the use of a polishing cloth having fixed abrasive with a mesh of 1000 to 2000, that is to say with an average particle diameter of 7 to 25 ⁇ m, is preferred when a subsequent cloth polishing is carried out.
  • the duration of the cloth polishing can be made very short, for example 15 to 30 s.
  • the method according to the invention preferably also comprises a polishing of the front side of the semiconductor wafer that is carried out as a single-side polishing.
  • the front side of the semiconductor wafer is deemed to be that side of the semiconductor wafer on which provision is made for constructing electronic components.
  • the single-side polishing referred to hereinafter as CMP (“chemical-mechanical polishing”), is preferably performed as luster polishing with the aim of providing a smoothest possible side surface.
  • the material removal of the CMP with a thickness of at most 1 ⁇ m, is significantly smaller than in the case of a removal polishing.
  • the CMP of the front side is preferably carried out after the double-side polishing and before or after the FA polishing.
  • the method according to the invention optionally also comprises the deposition of an epitaxial layer on the front side of the semiconductor wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
US12/262,202 2007-11-15 2008-10-31 Method For Producing A Semiconductor Wafer With A Polished Edge Abandoned US20090130960A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007056122A DE102007056122A1 (de) 2007-11-15 2007-11-15 Verfahren zur Herstellung einer Halbleiterscheibe mit polierter Kante
DE102007056122.0 2007-11-15

Publications (1)

Publication Number Publication Date
US20090130960A1 true US20090130960A1 (en) 2009-05-21

Family

ID=40576892

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/262,202 Abandoned US20090130960A1 (en) 2007-11-15 2008-10-31 Method For Producing A Semiconductor Wafer With A Polished Edge

Country Status (7)

Country Link
US (1) US20090130960A1 (de)
JP (1) JP2009124153A (de)
KR (1) KR20090050939A (de)
CN (1) CN101434047A (de)
DE (1) DE102007056122A1 (de)
SG (1) SG152978A1 (de)
TW (1) TW200921773A (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100178851A1 (en) * 2009-01-13 2010-07-15 Masayuki Nakanishi Polishing apparatus and polishing method
US20100330786A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing An Epitaxially Coated Semiconductor Wafer
US20100327414A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing A Semiconductor Wafer
US20100330885A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Polishing The Edge Of A Semiconductor Wafer
US20110097975A1 (en) * 2009-10-28 2011-04-28 Siltronic Ag Method for producing a semiconductor wafer
US9193026B2 (en) 2013-03-19 2015-11-24 Siltronic Ag Method for polishing a semiconductor material wafer

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009030292B4 (de) * 2009-06-24 2011-12-01 Siltronic Ag Verfahren zum beidseitigen Polieren einer Halbleiterscheibe
DE102010014874A1 (de) * 2010-04-14 2011-10-20 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
JP2012009550A (ja) * 2010-06-23 2012-01-12 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2012019126A (ja) * 2010-07-09 2012-01-26 Disco Abrasive Syst Ltd ウエーハの加工方法
DE102013210057A1 (de) 2013-05-29 2014-12-04 Siltronic Ag Verfahren zur Politur der Kante einer Halbleiterscheibe
CN104526493A (zh) * 2014-11-18 2015-04-22 天津中环领先材料技术有限公司 一种单晶硅晶圆片边缘抛光工艺
CN108214110A (zh) * 2016-12-14 2018-06-29 有研半导体材料有限公司 一种硅抛光片边缘加工工艺

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6162730A (en) * 1995-02-28 2000-12-19 Komatsu Electronic Metals Co., Ltd. Method for fabricating semiconductor wafers
US6211088B1 (en) * 1998-08-31 2001-04-03 Sumitomo Metal Industries, Ltd. Manufacturing method for semiconductor gas-phase epitaxial wafer
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
US6465328B1 (en) * 1998-10-01 2002-10-15 Sumitomo Metal Industries, Ltd. Semiconductor wafer manufacturing method
US6514423B1 (en) * 2000-02-22 2003-02-04 Memc Electronic Materials, Inc. Method for wafer processing
US20060252355A1 (en) * 2004-11-16 2006-11-09 Nihon Micro Coating Co., Ltd. Polishing tape and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW308561B (de) * 1995-08-24 1997-06-21 Mutsubishi Gum Kk
DE10007390B4 (de) 1999-03-13 2008-11-13 Peter Wolters Gmbh Zweischeiben-Poliermaschine, insbesondere zur Bearbeitung von Halbleiterwafern

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6162730A (en) * 1995-02-28 2000-12-19 Komatsu Electronic Metals Co., Ltd. Method for fabricating semiconductor wafers
US6211088B1 (en) * 1998-08-31 2001-04-03 Sumitomo Metal Industries, Ltd. Manufacturing method for semiconductor gas-phase epitaxial wafer
US6465328B1 (en) * 1998-10-01 2002-10-15 Sumitomo Metal Industries, Ltd. Semiconductor wafer manufacturing method
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
US6514423B1 (en) * 2000-02-22 2003-02-04 Memc Electronic Materials, Inc. Method for wafer processing
US20060252355A1 (en) * 2004-11-16 2006-11-09 Nihon Micro Coating Co., Ltd. Polishing tape and method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100178851A1 (en) * 2009-01-13 2010-07-15 Masayuki Nakanishi Polishing apparatus and polishing method
US20100330786A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing An Epitaxially Coated Semiconductor Wafer
US20100327414A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing A Semiconductor Wafer
US20100330885A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Polishing The Edge Of A Semiconductor Wafer
US8389409B2 (en) 2009-06-24 2013-03-05 Siltronic Ag Method for producing a semiconductor wafer
US8388411B2 (en) 2009-06-24 2013-03-05 Siltronic Ag Method for polishing the edge of a semiconductor wafer
US8551870B2 (en) 2009-06-24 2013-10-08 Siltronic Ag Method for producing an epitaxially coated semiconductor wafer
US20110097975A1 (en) * 2009-10-28 2011-04-28 Siltronic Ag Method for producing a semiconductor wafer
US8685270B2 (en) 2009-10-28 2014-04-01 Siltronic Ag Method for producing a semiconductor wafer
US9193026B2 (en) 2013-03-19 2015-11-24 Siltronic Ag Method for polishing a semiconductor material wafer

Also Published As

Publication number Publication date
TW200921773A (en) 2009-05-16
DE102007056122A1 (de) 2009-05-28
JP2009124153A (ja) 2009-06-04
KR20090050939A (ko) 2009-05-20
CN101434047A (zh) 2009-05-20
SG152978A1 (en) 2009-06-29

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Legal Events

Date Code Title Description
AS Assignment

Owner name: SILTRONIC AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROETTGER, KLAUS;AIGNER, WERNER;TABATA, MAKOTO;REEL/FRAME:021766/0840;SIGNING DATES FROM 20081009 TO 20081013

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION