TW200913079A - Method of processing a high-k dielectric for cet scaling - Google Patents
Method of processing a high-k dielectric for cet scaling Download PDFInfo
- Publication number
- TW200913079A TW200913079A TW097128623A TW97128623A TW200913079A TW 200913079 A TW200913079 A TW 200913079A TW 097128623 A TW097128623 A TW 097128623A TW 97128623 A TW97128623 A TW 97128623A TW 200913079 A TW200913079 A TW 200913079A
- Authority
- TW
- Taiwan
- Prior art keywords
- thickness
- layer
- dielectric
- further characterized
- annealing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 17
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims description 38
- 238000000151 deposition Methods 0.000 claims description 21
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 16
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- 239000007789 gas Substances 0.000 claims description 15
- DZBUGLKDJFMEHC-UHFFFAOYSA-N acridine Chemical compound C1=CC=CC2=CC3=CC=CC=C3N=C21 DZBUGLKDJFMEHC-UHFFFAOYSA-N 0.000 claims description 10
- 239000002253 acid Substances 0.000 claims description 9
- 229910052727 yttrium Inorganic materials 0.000 claims description 8
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- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 2
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- 239000011733 molybdenum Substances 0.000 claims description 2
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 4
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 claims 2
- 229910052691 Erbium Inorganic materials 0.000 claims 1
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- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 claims 1
- 150000004678 hydrides Chemical class 0.000 claims 1
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- 239000010955 niobium Substances 0.000 claims 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims 1
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- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 229910052735 hafnium Inorganic materials 0.000 abstract 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 abstract 1
- 230000008901 benefit Effects 0.000 description 12
- 230000008021 deposition Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
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- RYHBNJHYFVUHQT-UHFFFAOYSA-N 1,4-Dioxane Chemical compound C1COCCO1 RYHBNJHYFVUHQT-UHFFFAOYSA-N 0.000 description 1
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- LRBQNJMCXXYXIU-PPKXGCFTSA-N Penta-digallate-beta-D-glucose Natural products OC1=C(O)C(O)=CC(C(=O)OC=2C(=C(O)C=C(C=2)C(=O)OC[C@@H]2[C@H]([C@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)[C@@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)[C@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)O2)OC(=O)C=2C=C(OC(=O)C=3C=C(O)C(O)=C(O)C=3)C(O)=C(O)C=2)O)=C1 LRBQNJMCXXYXIU-PPKXGCFTSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 240000006394 Sorghum bicolor Species 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
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- LRBQNJMCXXYXIU-NRMVVENXSA-N tannic acid Chemical compound OC1=C(O)C(O)=CC(C(=O)OC=2C(=C(O)C=C(C=2)C(=O)OC[C@@H]2[C@H]([C@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)[C@@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)[C@@H](OC(=O)C=3C=C(OC(=O)C=4C=C(O)C(O)=C(O)C=4)C(O)=C(O)C=3)O2)OC(=O)C=2C=C(OC(=O)C=3C=C(O)C(O)=C(O)C=3)C(O)=C(O)C=2)O)=C1 LRBQNJMCXXYXIU-NRMVVENXSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Composite Materials (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
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200913079 九、發明說明: 【發明所屬之技術領域】 在先申請案之參照 此申請案已於2007年7月30在美國提出申請,專利申言主 5 案 5虎為 11/830,331。 發明領域 本發明大致關於半導體裝置,以及更明確地,關於處 理高_K介電f供用於電容等效厚度(CET)之尺寸縮放 方法。 、 10 【^*前 發明背景 為了改良高-k半導體裝置的性能,要求高士介電質材 料的電容等效厚度(CET)之尺寸縮放。高介電質材料之 例子可包括Hf02、Zr02、HfZr04、HfSiO、HfSiON等等。 15已發現到,為了連續之CET之尺寸縮放,要求物理上較薄 的高-k介電質(約15入或更薄)。然而,在一例子中,扣 厚度(Tphy)之最佳化的研究已顯示出,當Tphy小於15入, C£T較高。這是因為小於i 5A之Tphy HfZr04膜是非均—的且 對於導致較厚之界面層的氧擴散更具通透性。 >0 因此,需要一改良的方法以克服上述此技術領域中的 問題。 ^ I勞^明内容】 發明概要 根據本發明’提供一種在半導體層上製造半導體元件 200913079 之方法,包含: 形成間極介電質,其中形成該閘極介電質包含在該半 導體層上沈積包含錯酸給之高介電質; 在包含氫及氮的《環境巾,在攝氏㈣度至攝氏85〇 5度之間的溫度下,將高士介電質退火;以及 在該高-k介電質上形成閘極。 圖式簡單說明 本發明將利用實施例來例示說明,且不受限於附帶的 圖式’於圖式中,類似的元件符號意指類似的元件。在圖 10式中的元件是供簡便性及清楚性的例示說明,以及不必然 地需依比例繪製。 第1圖至第3圖為根據本發明揭露之—實施例的處理高 -K介電質飼於電料效厚度(CET)之尺寸縮放的方法 之不同階段期間,半導體元件的橫截面圖; 第4圖為具有根據本發明揭露之實施例的處理方法形成之 高-k介電質層的半導體元件之橫截面圖; 第5圖為解釋說明CET相對於供用於多數目標厚度 之高-k介電質層的圖形表現圖,其中第一組未經過根據 本發明揭露之實補處理,以及第二組經過根據本發明 20揭露之實施例處理;以及 參 第6圖為例示說明等效氧化物厚度(EOT)相對於供用 於多數目標厚度之高-k介電質層的圖形表現圖,其中第-組未經過根據本發明揭露之實施例處理’以及第二組經過 根據本發明揭露之實施例處理。 200913079 【貧施方式】 詳細說明 5 10 15 一種製造半導體元件之方法,包括製備具有上部閘極 之間極介電質。半導體元件是在半導體廣上製造。包含錯 酸铪4姊„係沈積麵半導體層上。高拆電質是在 b 3氫及氮的氣體^兄中’在界於攝氏㈣度至攝氏咖度 =的溫度下退火。閘極是在高姊電質上形成。高_k介電 I的功用是使用於閘極介電質。-影響為改良電晶體性 此’另—方面為維持或甚至改良_漏電的程度。 «康本發明揭露之實施例的—方法,包括物理上較薄 (15A或更薄)的高-k介電質之形成,該高-k介電質具有所 欲薄膜介電特性供用於CET之尺寸縮放。該方法包括钱刻 融材料及同時有助於薄化界面層叫的處理,以致於可 獲得所欲的啦之尺寸職效益。在—實施财將所欲 之CET之尺寸縮放最大化。 根據本發明揭露之-實施例,一方法包含⑴沉積或形 成減較厚(比15A厚)的高_k介電質層,以致於起始的高 -k膜是連續的及更均勻的;(2)藉由在例如氨⑽、石比 咬(C5H5N)、聯胺(N2h4)之含有氮及氮的氣體環境中 之較高溫度沈積後退火,執行經控制之高_k介電質層的去 除;以及(3)改變退火溫度(65G_85(rc)及時間(5〇_2〇〇s) 以獲得一蝕刻速率及因此調變高-k介電質供用於cET之尺 寸縮放的最後厚度。 在本文中所描述之半導體基體可為任何半導體材料 20 200913079 或材料的組合,例如砷化鎵、矽鍺、絕緣層上覆矽(SOI)、 石夕、單晶硬及其類似物,及上述之組合。 第1圖至第3圖為根據本發明揭露之一實施例的處理高 -K介電質供用於電容等效厚度(cet)之尺寸縮放的方法 5之不同階段期間,半導體元件的橫截面圖。在一實施例中, 提供—半導體基板12,該基板包含具有覆蓋在該基板12之 表面上的二氧化矽之界面層(IL) 14的矽基板。在第2圖中, 高-k介電質層16係形成在界面層14上。在一實施例中,高_k 介電質層16包含HfZr〇4。高-k介電質層16及界面層14一起 10由元件符號17表示。 在第3圖中,半導體元件1〇係藉由暴露於氣體環境18 及一定的時程的退火20來處理。在一實施例中,氣體環境 18包含含有氮和氫之氣體環境。舉例而言,在一實施例中, 含有氮及氫之氣體環境包含氨(NH3)、砒啶(C5H5N)、 15聯胺(N2H4)或其他適合的氮及氫氣體環境中之一或多者。 退火20包含舉例而言,大約65〇。(:至85〇。(::(65〇_85〇。〇之 退火溫度,以及大約5〇秒至200秒(50-200S)之時程。氣體 環境及退火的組合提供所欲之高冷介電質厚度減少速率, 因此具有調變高_k介電質供用於CET之尺寸縮放之最終厚 2〇 度的能力。 基於多數理由,在含有氮及氫之氣體環境中的高溫沈 積後退火是有利的。一理由是,在含有氮及氫之氣體環境 中的高溫沈積後退火合併控制量之氮及降低高-k介電質中 的氧空缺及陷阱密度的可能性。基於另一理由,在含有氮 200913079 及氮的氣體環境中的高溫沈積後退火使高-k介電質層密 實。再者’在含有氮及氫之氣體環境中的高溫沈積後退火 抑制界面氧化物生長。更重要的是,在含有氮及氳之氣體 環境中的高溫沈積後退火,係以經控制的方式,化學地去 5除(亦即’蝕刻)所欲量之高_k層。因此,化學蝕刻方法 造成較薄、較密實及均一的高-k層,其具有較薄之界面層 供用於CET之尺寸縮放。 第4圖為具有根據本發明揭露之實施例的處理方法形 成之高-k介電質層17的半導體元件1〇之橫截面圖。尤其, 10 根據本發明之一實施例,第4圖為在半導體元件10之製造的 進一步處理期間,第3圖之半導體元件1〇的部分橫截面圖, 半導體元件的特徵為高—k介電質層。進一步處理包括使用 任何用於形成的適當技術’及根據所欲半導體元件的應用 的要求,形成閘極22、侧壁間隔件24、源極/汲極區域(26,28) 15 及碎化物區域(未顯示)。 第5圖為解釋說明CET(在垂直軸上)相對於供用
度。數據點40代表經過根據本發明揭露 。數據點38代表 升獲得的HfZr04厚 之實施例處理所獲 200913079 得的HfZr04厚度。由元件符號42代表之實質厚度Tph,々 16A,且為最大CET效益厚度的代表。 元件符號44表示之箭頭係圖示地代表CET之尺寸縮 放。雖然數據點38及40的實質厚度在最大CET效益厚度42 5 處類似,需注意的是,數據點38之CET為約超過15A或約 15人,另一方面,數據點40之CET為約小於14A或約13.5人。 回想數據點3 8為未經過根據本發明揭露之實施例處理所獲 得的高-k介電質的代表。此外,數據點40為經過根據本發 明揭露之實施例處理所獲得的高-k介電質的代表。因此, 10 在數據點38與數據點40之間,CET之尺寸縮放的量約 1.5A。另外,第5圖所示之數據點34,由元件符號42所表示 之實質厚度Tphy代表藉由有關其他數據點34中獲得之CET 效益的新方法所獲得之最大CET效益厚度。 元件符號46表示之箭頭係圖示地代表界面層(IL)之增 15 加厚度。換言之,在實質厚度小於最大CET效益厚度42之 下,觀察到界面層厚度隨高-k介電質層與界面層厚度之組 合的整體實質厚度之減少而增加。此一界面層厚度增加是 非所欲的,以及因此總實質厚度減少至低於最大CET效益 厚度42及窗36的外部是不偏好的。再者,為了減少厚度小 20 於最大CET效益厚度42及窗36之外的情況,界面層厚度占 總厚度的比例愈來愈大(與高-k介電質所促成之總厚度的 百分比相較)。窗36之實質厚度的範圍(最小值Tphy,最大 值Tphy)係根據既定半導體元件應用的特殊要求來選擇。窗 36之範圍係依锆酸铪膜中的Hf含量而定。若使用不同的高 10 200913079 -k介電質層,將獲得不同之f36的限制。此數據的目的在 於解釋δ兒明傳統厚度尺寸縮放至較低的限制。 此外,元件符號48表示之箭頭係圖示地代表實質層 i曰加厚度。換言之,在實質厚度大於最大CET效益厚度C 5之下,觀察到雖然實質厚度增加,界面層厚度隨高_k介電 質層與界面層厚度之組合的整體實f厚度的增加而維持 約相同。此-界面層厚度維持在實質固定的厚度是所欲 的,以及因此總實質厚度增加至最大CET效益厚度42以 上’及由於高-k介電質厚度增加,窗36之外部是占優勢的。 10 第6圖為例示說明等效氧化物厚度(EOT)(在垂直軸 上)相對於供用於多數目標厚度之高4介電質層(在水平 軸上)的圖形表現圖,其中第一組52未經過根據本發明揭 露之實施例處理,以及第二組54經過根據本發明揭露之實 施例處理。由圖形表示圖5〇可觀察到,利用數據點之適當 15曲線近似法,當第一組52之高-k介電質層的實質厚度為 〇A,IL層之EOT約9A。第二組54之高-k介電質層的實質厚 度為0A時’ IL層之EOT約7_5A。約1.5A之差異代表經過根 據本發明揭露之實施例處理的高-k介電質層之約略il層厚 度降低。再者,經過根據本發明揭露之實施例處理的高_k 20 介電質之例示說明的數據點(由線54上之空心矩形所表 示),實質上比未經過根據本發明揭露之實施例處理的高 -k介電質的對應數據點(由線52上之實心矩形所表示)薄。 現在應瞭解到’本發明已提供一種在一半導體層上製 造一半導體元件之方法,包含:形成閘極介電質,其中形 200913079 成閘極介電質包含在該半導體層上沉積包含錯酸給之高_k 介電質·,在包含氮及氫的氣體環境中,在界於攝氏65〇度至 攝氏850度之間的溫度下,使該高_k介電質退火;以及在該 W介電質上形成閘極。退火步驟之進—步特徵在於氣體 5環境包含由氨、砒啶及聯胺所組成之組群中之一者。在另 一實施例中,沉積步驟之進一步特徵在於锆酸铪包含 略〇4。在另-實施例中’退火步驟的特徵在於溫度不超 過攝氏800度。在又另-實施例中,退火步驟的特徵在於溫 度不超過攝氏750度。在又另一實施例中,退火步驟的特徵 10 在於溫度為約攝氏700度。 在另一實施例中,形成閘極之步驟包含沉積由氮化 鈦、碳化钽、氮化鉬及氮氧化鉬所組成之組群中之一者。 退火步驟之進一步特徵在於在退火步驟之後,高_k介電質 是連續的。 15 在另一實施例中,形成閘極介電質之步驟進一步包含 在執行沉積步驟之前,在該半導體層上,形成具有第一厚 度的界面氧化物。退火步驟使界面氧化物減少至小於第一 厚度之第二厚度,其中該第二厚度小於10埃。此外,退火 步驟之進一步特徵在於減少該高七介電質之厚度。 在另一實施例中,一種在一半導體層上形成一半導體 元件之方法,包含:直接在該半導體層上形成一界面氧化 物’直接在該界面氧化物上沈積一錯酸給之層;在包含氮 及氫的氣體環境中,在界於攝氏65〇度至攝氏750度之間的 溫度下,使該鍅酸铪退火;以及在該锆酸铪上形成閘極。 12 200913079 退火步驟之進—步特徵在於氣體八 胺所組成之組群中之—者。沉積步綠=由 鍅酸給包含HfZK)4。退火步驟〜 v特徵在於忒 面層之厚度及該歸給之厚度。步特徵在於減少該界 進一步特徵在於界面氧化/面氧化物之步驟的 氧化物層之厚度的步驟將該界面$ #者,減少界面 10埃。 物之厚度減少至小於
10 15
20 在^關巾,-種在—㈣切成_半導體元件之 方法,包3:直接在-半導體層切成二氧化料,巧 该-乳化㈣具有H直接在該二氧切層上沉積一 錯酸給層,其巾減酸給層具有—厚度;在包 氣體環境中,在界於攝氏65〇度至攝氏⑽度之間的溫度 下,使該贿铪層退火,其減少該二氧切層之厚度及該 錯酸給層之厚度及在該歸铪層上形朗極^一^ 施例中’ 酸給層步驟之進-步特徵在祕酸給包含 HfZr〇4 ;以及退火該錯酸給層之步驟的進—步特徵在於施 用由氨、砒啶及聯胺所組成之組群中之_者。在另一實施 例中,退火步驟之進一步特徵在於溫度為約攝氏7〇〇度。 在發明說明及申請專利範圍中,若有用到專門術語 “前部”、“背部”、“頂部”、“底部,,、“上部” 及“下部”及類似用語的話,係為了說明的目的而使 用,但不必然用於描述永久的相對位置。應瞭解到,在 適當的情況下’所使用的專門術語是可互換的,以致於 本文中所描述之本發明的實施例能例如以本文中所例示 13 200913079 說明的或另外描述的其他位向來操作。 雖然本發明在本文中是參考特定的實施例來描述, 在未偏離下述申請專利範圍中所描述之本發明的範疇之 下,可進行各種不同的改良及變化。舉例而言,方法可 5 應用於使用在高度尺寸縮放之CMOS、3D集成、MRAM、 包埋之NVM、包埋之SRAM及其他半導體元件應用的高-k 介電質。因此,說明書及圖式係以例示說明的觀點而非 限制的觀點視之,以及所有此等之改良企圖包括於本發 明的範疇内。描述於本文中關於特定實施例的任何效 10 益、優點或問題的解決方法非意欲解釋成任何或所有申 請專利範圍的關鍵、必要或主要的特徵或元件。 在本文中使用之專門術語“辆合”一詞非意欲 限制於直接耦合或機械耦合。 再者,使用於本文中之用語“一(a或an) ”是定義為 15 —或一以上。在申請專利範圍中使用之例如“至少一”及 “一或多”等前置詞,即使當同一申請專利範圍中包括前 置詞“ 一或多”或“至少一 ”及例如“ 一(a或an ) ”之不 定冠詞時,不應解釋成暗示由不定冠詞“一(a或an) ”所 導引的另一請求元件係將含有此等被導引之請求元件的任 20 何特定申請專利範圍,限制成僅含有一此等元件的發明。 定冠詞之使用亦適用相同的原則。 除非另外說明,例如“第一”及“第二”等用語係用 於任意地區分此等用語所描述的元件。因此,此等用語不 必然意指此等元件的時間上或其他優先性。 14 200913079 【陶式簡單說明】 第1圖至第3圖為根據本發明揭露之一實施例的處理高 -K介電質供用於電容等效厚度(CET)之尺寸縮放的方法 之不同階段期間,半導體元件的橫截面圖; 5 第4圖為具有根據本發明揭露之實施例的處理方法形成之 高-k介電質層的半導體元件之橫截面圖; 第5圖為解釋說明CET相對於供用於多數目標厚度 之兩-k介電質層的圖形表現圖’其中第一組未經過根據 本發明揭露之實施例處理,以及第二組經過根據本發明 10揭露之實施例處理;以及 第6圖為例示說明等效氧化物厚度(EOT)相對於供用 於多數目標厚度之高-k介電質層的圖形表現圖,其中第一 組未經過根據本發明揭露之實施例處理,以及第二組經過 根據本發明揭露之實施例處理。 15 【主要元件符號説明】 10半導體元件 24間隔件 12半導體基板 26源極區域 14界面層 28沒極區域 16高-k介電質層 17高-k介電質層16及界面層 14 18氣體環境 20退火 22閑極 30解釋說明CET(在垂直軸上) 相對於供用於多數目標厚度 之高-k介電質層(在水平軸 上)的圖形表現圖 32 第一組 15 200913079 34 第二組 36窗 38數據點 40數據點 42最大CET效益厚度 44 CET之尺寸縮放 46界面層(IL)之增加厚度 48實質層增加厚度 52 第一組 54第二組 16
Claims (1)
- 200913079 十、申請專利範圍: 1. 一種在半導體層上製造半導體元件之方法,包含: 形成閘極介電質,其中形成該閘極介電質包含在 該半導體層上沈積包含锆酸铪之高-k介電質; 5 在包含氫及氮的氣體環境中,在攝氏650度至攝氏 850度之間的溫度下,將高-k介電質退火;以及 在該面-k介電質上形成閘極。 2. 如申請專利範圍第1項之方法,其中該退火步驟之進一 步特徵在於該氣體環境包含由氨、砒啶及聯胺所組成 10 之組群中之一者。 3. 如申請專利範圍第1項之方法,其中該沈積步驟之進一 步特徵在於該鍅酸铪包含HfZr04。 4. 如申請專利範圍第1項之方法,其中該退火步驟之進一 步特徵在於溫度不超過攝氏800度。 15 5. 如申請專利範圍第4項之方法,其中該退火步驟之進一 步特徵在於溫度不超過攝氏750度。 6. 如申請專利範圍第5項之方法,其中該退火步驟之進一 步特徵在於溫度約攝氏700度。 7. 如申請專利範圍第1項之方法,其中該形成閘極之步驟 20 包含沉積由氮化鈦、碳化钽、氮化鉬及氮氧化鉬所組 成之組群中之一者。 8. 如申請專利範圍第1項之方法,其中該退火步驟之進一 步特徵在於在該退火步驟之後,該高-k介電質是連續 的。 17 200913079 9. 如申請專利範圍第1項之方法,其中該形成閘極介電質 之步驟進一步包含在執行該沉積步驟之前,在該半導 體層上,形成具有第一厚度的界面氧化物。 10. 如申請專利範圍第9項之方法,其中該退火步驟使該界 5 面氧化物減少至小於第一厚度之第二厚度,其中該第 二厚度小於10埃。 11. 如申請專利範圍第10項之方法,其中該退火步驟之進 一步特徵在於減少該高-k介電質之厚度。 12. —種在一半導體層上形成一半導體元件之方法,包含: 10 直接在該半導體層上形成一界面氧化物; 直接在該界面氧化物上沈積一錯酸給之層; 在包含氮及氫的氣體環境中,在界於攝氏650度至 攝氏750度之間的溫度下,使該锆酸铪退火;以及 在該鍅酸铪上形成閘極。 15 13.如申請專利範圍第12項之方法,其中該退火步驟之進 一步特徵在於氣體環境包含由氨、砒啶及聯胺所組成 之組群中之一者。 14.如申請專利範圍第13項之方法,其中該沉積步驟之進 一步特徵在於該結酸铪包含HfZr04。 20 15.如申請專利範圍第14項之方法,其中該退火步驟之進 一步特徵在於減少該界面層之厚度及該鍅酸铪之厚 度。 16.如申請專利範圍第15項之方法,其中該形成界面氧化 物之步驟的進一步特徵在於該界面氧化物包含氧化 18 200913079 砍。 17.如申請專利範圍第16項之方法,其”減少界面氧化 物之厚度的步驟係將該界面氧化物厚度減少至小於10 埃。 5 18. _種在-石夕層上形成—半導體元件之方法,包含: 直接在一半導體層上形成二氧化矽層,其中該二 氧化矽層具有一厚度; 直接在e亥一氧化發層上沉積一錯酸給層,其中該 锆酸銓層具有一厚度; 10 在包含氮及氫的氣體環境中,在界於攝氏650度至 攝氏750度之間的溫度下,使該錯酸铪層退火,其減少 該二氧化矽層之厚度及該鍅酸铪層之厚度;以及 在該錯酸铪層上形成閘極。 19_如申請專利範圍第18項之方法,其中: 15 該沉積錯酸給層步驟之進一步特徵在於錯酸給包 含HfZr04 ;以及 退火該锆酸铪層之步驟的進一步特徵在於施用由 氨、础啶及聯胺所組成之組群中之一者。 20·如申請專利範圍第18項之方法,其中該退火步驟之進 2〇 一步特徵在於溫度為約攝氏700度。 19
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KR100450681B1 (ko) * | 2002-08-16 | 2004-10-02 | 삼성전자주식회사 | 반도체 메모리 소자의 커패시터 및 그 제조 방법 |
JP2004311782A (ja) * | 2003-04-08 | 2004-11-04 | Tokyo Electron Ltd | 成膜方法及び成膜装置 |
FR2855908B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince |
KR100555543B1 (ko) * | 2003-06-24 | 2006-03-03 | 삼성전자주식회사 | 원자층 증착법에 의한 고유전막 형성 방법 및 그고유전막을 갖는 커패시터의 제조 방법 |
US7115530B2 (en) * | 2003-12-03 | 2006-10-03 | Texas Instruments Incorporated | Top surface roughness reduction of high-k dielectric materials using plasma based processes |
US7071038B2 (en) * | 2004-09-22 | 2006-07-04 | Freescale Semiconductor, Inc | Method of forming a semiconductor device having a dielectric layer with high dielectric constant |
US7217643B2 (en) * | 2005-02-24 | 2007-05-15 | Freescale Semiconductors, Inc. | Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures |
US7531399B2 (en) * | 2006-09-15 | 2009-05-12 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices and methods with bilayer dielectrics |
-
2007
- 2007-07-30 US US11/830,331 patent/US20090035928A1/en not_active Abandoned
-
2008
- 2008-06-16 JP JP2010520014A patent/JP2010535428A/ja not_active Withdrawn
- 2008-06-16 CN CN200880100700A patent/CN101765903A/zh active Pending
- 2008-06-16 EP EP08771155A patent/EP2176879A1/en not_active Withdrawn
- 2008-06-16 WO PCT/US2008/067079 patent/WO2009017888A1/en active Application Filing
- 2008-07-29 TW TW097128623A patent/TW200913079A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
EP2176879A1 (en) | 2010-04-21 |
JP2010535428A (ja) | 2010-11-18 |
CN101765903A (zh) | 2010-06-30 |
US20090035928A1 (en) | 2009-02-05 |
WO2009017888A1 (en) | 2009-02-05 |
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