經濟部中央標準局員工消費合作社印製 495900 A7 __B7 五、發明説明（1 ) ^ 本發明是有關於一種半導體製程，且特別是有關於一 種改善複晶發/複晶砍氧化層（poly 〇xide)之介面粗繞度的 方法’可應用在電容器的製作上，以改善電容器的操作性 在半導體積體電路中，特別是某些混合模式的積體電 路(mix-mode)，即集數位與類比於一體的電路中，常利用 複晶石夕與金屬層及其夾層之介電層構成電容器。第1圖即 繪示一電容器結構之剖面示意圖。此電容器是建構在一半 導體基底10上方，利用一複晶矽層14構成下電極板，以 一金屬層22為上電極板，而其間乃夾有一介電層ls。介 電層15通常包括一複晶矽氧化層16、氮化矽層ι8、以及 四乙氧基矽烷層20(TEOS)。此外，圖中標號"表示源極/ 没極區’ 12表示閘氧化層。 在上述中，複晶矽氧化層16通常是由複晶矽層施以氧 化處理而得，然而在複晶矽裡存有許多不同方向的晶粒 (grain)及晶界(grain boundary)，這些晶粒和晶界於氧化過 程中有不同的氧化速率，造成氧化後在複晶石夕氣化層i 6 和複晶矽層14的介面上呈現凹凸不平的形狀，如圖中9所 示’因而破壞該複晶矽氧化層的電性，造成低崩潰電麼及 南漏電流等缺點。 就目前而言，雖然以低溫(<60(TC)形成的複晶石夕層具 有較小的晶粒尺寸（grain size)，但由於沈積速率較慢，會 影響產能(throughput)，再加上溫度太低容易會有位向的問 題產生（orientation growth issue)，因此目前仍是以高严 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐) (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 495900 A7Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 495900 A7 __B7 V. Description of the Invention (1) ^ The present invention relates to a semiconductor process, and in particular to an improved polycrystalline hair / polycrystalline oxide layer (poly 〇xide The method of the interface coarse winding degree 'can be applied to the manufacture of capacitors to improve the operability of the capacitors. In semiconductor integrated circuits, especially some mixed-mode integrated circuits (mix-mode) In analog circuits, capacitors are often composed of polycrystalline stone and the dielectric layer of the metal layer and its interlayer. Figure 1 is a schematic cross-sectional view of a capacitor structure. This capacitor is constructed over a semi-conductor substrate 10, and a polycrystalline silicon layer 14 is used to form a lower electrode plate, and a metal layer 22 is used as an upper electrode plate with a dielectric layer 1s interposed therebetween. The dielectric layer 15 generally includes a polycrystalline silicon oxide layer 16, a silicon nitride layer ι8, and a tetraethoxysilane layer 20 (TEOS). In addition, the reference numeral " in the figure indicates a source / inverted region ' 12 indicates a gate oxide layer. In the above, the polycrystalline silicon oxide layer 16 is usually obtained by subjecting the polycrystalline silicon layer to oxidation treatment. However, there are many grains and grain boundaries in the polycrystalline silicon in different directions. These The grains and grain boundaries have different oxidation rates during the oxidation process, resulting in an uneven shape on the interface of the polycrystalline stone gasification layer i 6 and the polycrystalline silicon layer 14 after oxidation, as shown in Figure 9 ' Therefore, the electrical properties of the polycrystalline silicon oxide layer are destroyed, causing shortcomings such as low breakdown current and south leakage current. At present, although the polycrystalline spar layer formed at low temperature (< 60 (TC)) has a smaller grain size, the slower deposition rate will affect the throughput. If the temperature is too low, it is easy to cause orientation growth issues. Therefore, it is still applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) with high strict paper standards. (Please read the back Please fill in this page again)-Binding · Order 495900 A7
五、發明説明（2 ) (請先閲讀背面之注意事項再填寫本頁) (>600 C)的條件來製作此複晶矽層，請參照第2圖，繪示 以習知方法製作複晶矽與複晶矽氧化層之流程，其優點是 沈積速率快，但缺點是表面較粗糙、均勻度差，影響到複 晶石夕與介電層之間的介面品質。 有鑑於此’本發明的目的就是提供一種改善複晶矽與 複晶矽氧化層之間介面品質的方法，藉由改善竣晶矽層的 表面粗链度（surface roughnesi)，使後序形成的複晶石夕氧化 層與該複晶矽肩間形成良好的介面，以改善電容器的性 能。依據本發明之方法，可以在不影響產能的情況下，得 到介面品質良好的複晶矽氧化層，因而提昇了電容器的崩 潰電壓。 經濟部中央標準局員工消費合作社印裝 根據上述目的，本發明提供一種改善複晶矽/複晶矽氧 化層介面品質的方法，係在基底上先以高於600 t：的反轉 溫度，例如約620〜640乞，迅速沈積一高溫複晶矽層；之 後，再以以低於600 °C的反應溫度，例如約550〜570 °C , 沈積一層較薄的低溫複晶矽層，此低溫複晶矽層之表面粗 链度、晶粒尺寸較小，與上述之南溫複晶發層共同構成一 電容器的下電極板。將摻質佈植入複晶石夕層後，以熱氧化 法所形成的複晶矽氧化層，由於介面品質良好，具有優良 的電性。為完成電容器的製作，之後的步驟還包括：在複 晶矽氧化層上依序形成氮化矽層、四乙氧基矽烷層、以及 一導電層。 根據本發明之特點，上述沈積高溫複晶矽層與低溫複 晶矽層的步驟，可在同一反應室連續地進行，或者，也可 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公策） 495900 經濟部中央標準局員工消費合作社印裝 五 A7V. Description of the invention (2) (Please read the precautions on the back before filling in this page) (> 600 C) to make this polycrystalline silicon layer. Please refer to Figure 2 to show how to make the polycrystalline silicon layer by conventional methods. The process of crystalline silicon and polycrystalline silicon oxide layers has the advantage of fast deposition rate, but the disadvantages are rough surface and poor uniformity, which affects the interface quality between polycrystalline stone and dielectric layer. In view of this, the object of the present invention is to provide a method for improving the quality of the interface between the polycrystalline silicon and the polycrystalline silicon oxide layer. By improving the surface roughnesi of the finished silicon layer, the subsequent formation of A good interface is formed between the polycrystalline stone oxide layer and the polycrystalline silicon shoulder to improve the performance of the capacitor. According to the method of the present invention, a polycrystalline silicon oxide layer with a good interface quality can be obtained without affecting the production capacity, thereby increasing the collapse voltage of the capacitor. According to the above purpose, the present invention provides a method for improving the quality of a polycrystalline silicon / polycrystalline silicon oxide interface interface, which is firstly performed on a substrate at an inversion temperature higher than 600 t: At about 620 ~ 640, a high-temperature polycrystalline silicon layer is quickly deposited; after that, a thinner low-temperature polycrystalline silicon layer is deposited at a reaction temperature lower than 600 ° C, such as about 550 ~ 570 ° C. The surface roughness of the polycrystalline silicon layer is relatively small, and the grain size is small. Together with the above-mentioned south temperature complex crystal layer, the lower electrode plate of a capacitor is formed. The polycrystalline silicon oxide layer formed by thermal oxidation after the doped cloth is implanted into the polycrystalline stone layer has a good interface quality and excellent electrical properties. To complete the fabrication of the capacitor, the subsequent steps further include: sequentially forming a silicon nitride layer, a tetraethoxysilane layer, and a conductive layer on the polycrystalline silicon oxide layer. According to the features of the present invention, the above steps of depositing the high-temperature polycrystalline silicon layer and the low-temperature polycrystalline silicon layer may be continuously performed in the same reaction chamber, or the paper size may be adapted to the Chinese National Standard (CNS) A4 specification (210X297). Policy) 495900 Employees' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, printed five A7
發明説明（ 以分開來’在相同或不同的反應室中依次分別進行；其中 後者在沈積完高溫複晶石夕層後 ，可用氫氟酸(HF)先將複晶 矽層表面上的原生氧化層（native oxide)加以去除後，再進 行低溫複晶矽層的沈積。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示一電容器結構之剖面示意圖。 第2圖為習知製作複晶矽與複晶矽氧化層之製程流程 第3圖為依據本發明實施例丨，製作複晶矽與複晶矽 氧化層之製程流程圖。 第4圖為依據本發明實施例2，製作複晶石夕與複晶石夕 氧化層之製程流程圖。 符號說明： 1〇〜半導體基底；u〜複晶矽層；22〜金屬，層；15〜 介電層；16〜複晶矽氧化層；18〜氮化矽層；20〜四乙氧 基矽烷層；11〜源極/汲極區；12〜閘氧化層。 實施例1 _本發明之方法，適用於一半導體基底上，在基底上依 據傳統方式形成有場氧化物與閘氧化層等。於是，藉由場 氧化物隔離定義出一元件區，即得於元件區内的閘氧化層 上方’依下列步驟形成複晶矽與複晶矽氧化層。 圖 (請先閲讀背面之注意事項再填寫本頁) 495900 經濟部中央標準局員工消費合作社印装 A7 B7 五、發明説明（4 ) 睛參照第2圖’本實施例中是以連續方式，在同一反 應室内依序形成高溫複晶石夕層與低溫複晶石夕層。首先，在 630 °C下形成高溫複晶石夕層，沈積進行30分鐘後，將溫度 降至560 °C，以60分鐘的時間.完成低溫複晶矽層的沈積（降 溫過程30分鐘’ 560 °C沈積30分鐘，且降溫過程仍繼續 沈積）。所得之複晶矽層，經原子力顯微鏡(AFM ; Atomic Force Microscopy)量測其表面粗糙度（surface r0Ughness)為 78.27 A 〇 實施例2 請參照第3圖，本實施例中是將形成高溫複晶矽層與 低溫複晶矽層的步驟分開進行。首先，以630 °C的反應溫 度，沈積一層厚約3150 A的高溫複晶矽層後，將晶圓自 反應室取出。由於在複晶矽層上通常會有一層原生氧化層 存在，因此在進行低溫複晶矽層的沈積前，先以氫氟酸將 此氧化層去除，以避免影響電性品質。接著，在560 °C下 進行低溫複晶矽層的沈積約10分鐘，完成下電極的製作。 所得之複晶矽層經AFM量測其表面粗糙度為78·09 A。 比較例1、2 依照習知製作複晶矽的方式，在630 °C的溫度下分別 形成厚度3150 A (比較例1)、及4400 A (比較例2)的複晶 矽層，經AFM量測其表面粗糙度分別為95·07人、96·89 A 。茲將上述實施例與比較例之製程條件、表面粗糙度比 較如下表所示： 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） (請先閱讀背面之注意事項再填寫本頁)Description of the invention (Separately 'in the same or different reaction chambers in order; after the latter has deposited the high temperature polycrystalline stone layer, the hydrofluoric acid (HF) can be used to first oxidize the original polycrystalline silicon layer surface. After the native oxide layer is removed, the low-temperature polycrystalline silicon layer is deposited. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is provided below in cooperation with The attached drawings are described in detail as follows: Brief description of the drawings: Figure 1 shows a schematic cross-sectional view of a capacitor structure. Figure 2 is a conventional process flow for manufacturing polycrystalline silicon and polycrystalline silicon oxide layers. Figure 3 In accordance with the embodiment of the present invention, a process flow chart of manufacturing a polycrystalline silicon and a polycrystalline silicon oxide layer is shown. FIG. 4 is a process flow chart of manufacturing a polycrystalline silicon and a polycrystalline silicon oxide layer according to Embodiment 2 of the present invention. Symbol description: 10 ~ semiconductor substrate; u ~ polycrystalline silicon layer; 22 ~ metal, layer; 15 ~ dielectric layer; 16 ~ polycrystalline silicon oxide layer; 18 ~ silicon nitride layer; 20 ~ tetraethoxy Silane layer; 11 ~ source / drain region; 12 ~ gate oxygen Embodiment 1 _ The method of the present invention is applicable to a semiconductor substrate, and a field oxide and a gate oxide layer are formed on the substrate in a conventional manner. Therefore, an element region is defined by field oxide isolation. That is, above the gate oxide layer in the device area, the polycrystalline silicon and polycrystalline silicon oxide layers are formed according to the following steps. Figure (Please read the precautions on the back before filling out this page) Equipment A7 B7 V. Description of the invention (4) Refer to Figure 2 in this example. In this embodiment, a high-temperature polycrystalite layer and a low-temperature polycrystalite layer are sequentially formed in the same reaction chamber in a continuous manner. First, at 630, A high temperature polycrystalline stone layer was formed at ° C. After the deposition was carried out for 30 minutes, the temperature was reduced to 560 ° C in 60 minutes. The deposition of the low temperature polycrystalline silicon layer was completed (30 minutes of cooling process' 560 ° C deposition 30 Minutes, and the deposition process continued to be carried out.) The obtained polycrystalline silicon layer had a surface roughness (surface r0Ughness) of 78.27 A measured by atomic force microscope (AFM; Atomic Force Microscopy). Example 2 Please refer to Section 3 In this embodiment, the steps of forming a high-temperature polycrystalline silicon layer and a low-temperature polycrystalline silicon layer are performed separately. First, at a reaction temperature of 630 ° C, a high-temperature polycrystalline silicon layer having a thickness of about 3150 A is deposited, and then the crystals are deposited. It is taken out from the reaction chamber. Since a primary oxide layer usually exists on the polycrystalline silicon layer, before the low temperature polycrystalline silicon layer is deposited, the oxide layer is removed with hydrofluoric acid to avoid affecting the electrical properties. Then, the low-temperature polycrystalline silicon layer was deposited at 560 ° C for about 10 minutes to complete the fabrication of the lower electrode. The obtained polycrystalline silicon layer had a surface roughness of 78 · 09 A as measured by AFM. Comparative Examples 1 and 2 According to the conventional method for making polycrystalline silicon, a polycrystalline silicon layer having a thickness of 3150 A (Comparative Example 1) and 4400 A (Comparative Example 2) was formed at a temperature of 630 ° C. The surface roughness was measured at 95.07 persons and 96.89 A, respectively. The comparison of the process conditions and surface roughness of the above examples and comparative examples is shown in the following table: This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the precautions on the back before filling (This page)
495900 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（5 )495900 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5)
表1 製程條件 表面粗縫度 實施例1 630 °C ,30 min+560 °C ,60min 78.27 A 實施例2 630 〇C，3150 A +560 〇C，l〇min 78.09 A 比較例1 630 t：，厚度 3150 A 95.07 A 比較例2 630 °C，厚度 4450 A 96.89 A 由上表可以看出，以本發明之方法所形成之複晶矽 層，其表面粗糙度有明顯的改善，將有利於後續複晶矽氧 化層的製作。 ， 實施例3、4 &比較例3、4 在實施例3、4中，是依實施例1所述之方法，先在 一半導體基底上分兩階段沈積複晶矽層，並佈植離子於複 晶矽層中以提昇其導電性，然後以熱氧化法在複晶矽層上 形成一複晶矽氧化層；之後，按照習知的方式，依序形成 氮化矽層、TEOS層、以及金屬層等，以完成電容器之製 作，並測量其崩潰電壓。上述中複晶石夕層的製程條件及電 容器之崩潰電壓請參照表2。 在比較例3、4中，是依習知製作電容器的方式，在 閘氧化層上直接形成高溫複晶矽，來作為電容器的下電 極；其中比較例3之複晶矽厚度為4400 A，比較例4之 複晶矽厚度為3500 A。複晶矽層的製程條件及所得電容 器之崩潰電壓同樣請參照表2。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 495900 A7 B7 五、發明説明（6 )Table 1 Process conditions Surface roughness Example 1 630 ° C, 30 min + 560 ° C, 60 min 78.27 A Example 2 630 ° C, 3150 A +560 ° C, 10 min 78.09 A Comparative Example 1 630 t: , Thickness 3150 A 95.07 A Comparative Example 2 630 ° C, thickness 4450 A 96.89 A As can be seen from the table above, the surface roughness of the polycrystalline silicon layer formed by the method of the present invention has a significant improvement, which will be beneficial to Subsequent fabrication of a polycrystalline silicon oxide layer. Examples 3 and 4 & Comparative Examples 3 and 4 In Examples 3 and 4, according to the method described in Example 1, a polycrystalline silicon layer was first deposited in two stages on a semiconductor substrate, and ions were implanted. A polycrystalline silicon layer is formed in the polycrystalline silicon layer to improve its conductivity, and then a polycrystalline silicon oxide layer is formed on the polycrystalline silicon layer by a thermal oxidation method; thereafter, a silicon nitride layer, a TEOS layer, And metal layers, etc. to complete the fabrication of the capacitor and measure its breakdown voltage. Please refer to Table 2 for the process conditions of the above-mentioned polycrystalline stone layer and the breakdown voltage of the capacitor. In Comparative Examples 3 and 4, the conventional method of making a capacitor is to form a high-temperature polycrystalline silicon directly on the gate oxide layer as the lower electrode of the capacitor. The thickness of the polycrystalline silicon of Comparative Example 3 is 4400 A. The polycrystalline silicon thickness of Example 4 was 3500 A. Please refer to Table 2 for the process conditions of the polycrystalline silicon layer and the breakdown voltage of the obtained capacitor. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) 495900 A7 B7 V. Description of the invention (6)
表2 製程條件 崩潰電壓 實施例3 630 °C ,26 min+560 °C ,10min 73 V 實施例4 630 °C ,38 min+560 °C ,10min 79 V 比較例3 630 °C，厚度 4400 A 59.87 V 比較例4 630 °C，厚度 3500 A 72.09 V 由上表可知，依本發明之方法所製作之電容器，其崩 潰電壓明顯高於傳統的電容器，此乃由於複晶矽層之粗糙 度的改善，使後續形成的複晶矽氧化層與複晶矽層之間擁 有良好的介面品質，因而提高了電容器的崩潰電壓。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210'〆297公釐）Table 2 Process conditions breakdown voltage Example 3 630 ° C, 26 min + 560 ° C, 10 min 73 V Example 4 630 ° C, 38 min + 560 ° C, 10 min 79 V Comparative Example 3 630 ° C, thickness 4400 A 59.87 V Comparative Example 4 630 ° C, thickness 3500 A 72.09 V As can be seen from the table above, the capacitor produced according to the method of the present invention has a significantly higher breakdown voltage than traditional capacitors. This is due to the roughness of the polycrystalline silicon layer. The improvement makes the subsequent formation of the polycrystalline silicon oxide layer and the polycrystalline silicon layer have a good interface quality, thereby increasing the breakdown voltage of the capacitor. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210'〆297 mm)