CN101765903A - 处理高k电介质以实现CET缩放的方法 - Google Patents

处理高k电介质以实现CET缩放的方法 Download PDF

Info

Publication number
CN101765903A
CN101765903A CN200880100700A CN200880100700A CN101765903A CN 101765903 A CN101765903 A CN 101765903A CN 200880100700 A CN200880100700 A CN 200880100700A CN 200880100700 A CN200880100700 A CN 200880100700A CN 101765903 A CN101765903 A CN 101765903A
Authority
CN
China
Prior art keywords
layer
thickness
dielectric
feature
zirconic acid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200880100700A
Other languages
English (en)
Inventor
R·I·赫德
斯里坎斯·B·萨马弗达姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101765903A publication Critical patent/CN101765903A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种制造半导体器件(10)的方法，包括制造具有覆盖栅电极(22)的栅电介质(17)。半导体器件(10)被制造在半导体层(12)上。在半导体层上沉积包括锆酸铪的高k电介质(16)。在包括氢和氮的环境中在650摄氏度与850摄氏度之间的温度下对高k电介质进行退火。在高k电介质上形成栅电极(22)。高k电介质工在栅电极(17)中使用。一种影响是在保持、甚至改善栅极漏电水平的同时改善晶体管性能。

Description

处理高k电介质以实现CET缩放的方法
技术领域
本公开总体上涉及半导体器件，更具体而言，涉及处理高k电介质以实现电容等效厚度(CET)缩放的方法。
背景技术
为了改善高k半导体器件性能，需要高k电介质材料的电容等效厚度(CET)缩放((CET)scaling)。高k电介质材料的示例可以包括HfO2、ZrO2、HfZrO4、HfSiO、HfSiON等。已经发现对于持续CET缩放而言需要物理上较薄的高k电介质(
Figure GPA00001009799400011
左右或更薄)。然而，在一个示例中，HfZrO4厚度(Tphy)研究的最优化已经显示当Tphy小于
Figure GPA00001009799400012
时CET较高。这是因为小于
Figure GPA00001009799400013
Tphy的HfZrO4膜是不均匀的且对于氧扩散更具有渗透性，这导致较厚的界面层。
因此，需要一种用于克服如上文所讨论的本领域中的问题的改善方法。
附图说明
通过举例来说明本发明，并且本发明不受附图的限制，在附图中类似的附图标记指示类似的元件。附图中的元件仅仅是为了简单和明了而示出且其不一定按比例绘制。
图1～3是根据本公开的一个实施例的在处理高k电介质以用于CET缩放的方法的各阶段期间的半导体器件的横截面图；
图4是具有用根据本公开的实施例的处理方法形成的具有高k电介质层的半导体器件的横截面图；
图5是示出针对若干目标厚度的CET对比高k电介质层的厚度的图形表示视图，其中，第一组未经过根据本公开的实施例的处理且第二组经过根据本公开的实施例的处理；以及
图6是示出针对若干目标厚度的等效氧化物厚度(EOT)对比高k电介质层的目标物理厚度的图形表示视图，其中，第一组未经过根据本公开的实施例的处理且第二组经过根据本公开的实施例的处理。
具体实施方式
制造半导体器件的方法包括制造具有覆盖栅电极的栅电介质。在半导体层上制造半导体器件。在半导体层上沉积包括锆酸铪的高k电介质。在包括氢和氮的环境中在650摄氏度与850摄氏度之间的温度下对高k电介质进行退火。在高k电介质上形成所述栅电极。高k电介质功能供在栅电介质中使用。一种影响是在保持、甚至改善栅极漏电水平的同时改善晶体管性能。
根据本公开的实施例的方法包括形成具有用于CET缩放的期望薄膜电介质性质的物理上较薄(
Figure GPA00001009799400021
或更薄)的高k电介质。该方法包括蚀刻高k材料且同时帮助薄化界面层(IL)以便能够获得期望的CET缩放益处的处理。在一个实施例中，使期望的CET缩放最大化。
根据本公开的一个实施例，一种方法包括(1)沉积或形成相对厚(厚于
Figure GPA00001009799400022
)的高k电介质层，以便起始高k膜是连续的且更均匀；(2)通过在诸如氨水(NH3)、嘧啶(C5H5N)、联胺(N2H4)等含有氮和氢的环境中通过较高温度沉积后退火来执行起始高k电介质层的受控去除；以及(3)改变退火温度(650～850C)和时间(50～200s)以获得蚀刻速率并因此调整高k电介质材料的最终厚度以实现CET缩放。
本文所述的半导体衬底可以是任何半导体材料或材料组合，诸如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等、以及以上各项的组合。
图1～3是根据本公开的一个实施例的在处理高k电介质以实现CET缩放的方法的各阶段期间的半导体器件10的横截面图。在一个实施例中，提供半导体衬底12，该衬底包括具有覆盖衬底12的表面的氧化硅的界面间层(IL)14的硅衬底。在图2中，形成覆盖界面层14的高k电介质层16。在一个实施例中，高k电介质层16包括HfZrO4。用附图标记17来共同地指示高k电介质层16和界面层14。
在图3中，通过暴露于环境18和退火20给定的持续时间来处理半导体器件10。在一个实施例中，环境18包括含有氮和氢的环境。例如，在一个实施例中，含有氮和氢的环境包括氨水(NH3)、嘧啶(C5H5N)、联胺(N2H4)、或其它适当的氮和氢环境中的至少一个。例如，退火20包括约为650℃至850℃(650～850℃)左右的退火温度且具有约为50秒至200秒(50～200s)左右的持续时间。环境与退火的组合提供期望的高k电介质厚度减小速率，因此使得能够实现调节用于CET缩放的高k电介质的最终厚度的能力。
由于许多原因，含氮和氢的环境中的高温沉积后退火是有益的。原因之一，含氮和氢的环境中的高温沉积后退火结合了受控量的氮并可能降低高k电介质中的氧空穴和陷阱密度。原因之二，含氮和氢的环境中的高温沉积后退火使高k电介质层密度增加。此外，含氮和氢的环境中的高温沉积后退火抑制界面氧化物生长。更重要的是，含氮和氢的环境中的高温沉积后退火以受控方式在化学上去除(即蚀刻)高k层的期望水平。因此，此化学蚀刻处理得到针对CET缩放的具有较薄界面层的较薄、稠密、且均匀的高k层。
图4是具有用根据本公开的实施例的处理方法形成的高k电介质层17的半导体器件10的横截面图。特别地，图4是图3的半导体器件10的制造中的进一步处理期间的部分的局部横截面图，该半导体器件的特征在于根据本公开的一个实施例的高k电介质层。进一步处理包括使用用于形成栅电极22、侧壁间隔物24、源极/漏极区(26、28)、以及硅化物区(未示出)的任何适当技术并根据期望半导体器件应用的要求来形成它们。
图5是示出针对若干目标厚度的CET(在竖轴上)对比高k电介质层的厚度(在横轴上)的图形表示视图30，其中，第一组32未经过根据本公开的实施例的处理而第二组34经过根据本公开的实施例的处理。使用等于1.2伏的栅电压来确定用于图形视图30的CET厚度。还可以针对其它栅电压获得CET厚度数据。现在参考由附图标记36指示的窗口，包含在窗口36内的是数据点38和40。数据点38表示在没有根据本公开的实施例的处理的情况下获得的HfZrO4的厚度。数据点40表示用根据本公开的实施例的处理获得的HfZrO4的厚度。由附图标记42指示的物理厚度Tphy约为
Figure GPA00001009799400041
且表示最大CET益处(benefit)厚度。
由附图标记44所指示的箭头来以图形方式表示CET缩放。虽然数据点38和40的物理厚度在最大CET益处厚度42下是类似的，但请注意用于数据点38的CET在大于
Figure GPA00001009799400042
或约
Figure GPA00001009799400043
左右，而用户数据点40的CET在小于
Figure GPA00001009799400044
或约
Figure GPA00001009799400045
左右。回想一下，数据点38表示在没有根据本公开的实施例的处理的情况下获得的高k电介质。另外，数据点40表示用根据本公开的实施例的处理获得的高k电介质。因此，在数据点38与数据点40之间获得约
Figure GPA00001009799400046
左右的CET缩放量。另外，图5所示数据点34的由附图标记42指示的物理厚度Tphy表示相对于在其它数据点34之间获得的CET益处而言通过新工艺获得的最大CET益处厚度。
用附图标记46作指示的箭头来以图形方式表示界面层(IL)增大厚度。换言之，在小于最大CET益处厚度42的物理厚度下，可以看出界面层厚度随着组合的高k电介质层和界面层厚度的总体物理厚度的减小而增大。界面层厚度的此类增大是不期望的，因此在最大CET益处厚度42以下和窗口36外面减小的总物理厚度是不优选的。此外，为了减小小于最大CET益处厚度42且在窗36外面的厚度，界面层厚度在总厚度中占越来越大的百分比(与可归于高k电介质层的总厚度的百分比相比)。根据给定半导体器件应用的特定要求来选择窗口36的物理厚度的范围(最小Tphy、最大Tphy)。窗口36的范围取决于锆酸铪膜中的Hf含量。如果使用不同的高k电介质层，则将获得对窗口36的不同限制。此数据的目的是示出缩放到较低CET的传统厚度的限制。
另外，用附图标记48所指示的箭头来以图形方式表示物理层增大厚度。换言之，在大于最大CET益处厚度42的物理厚度下，可以看出虽然物理厚度增大了，但界面层厚度仍然大约与组合的高k电介质层和界面层厚度的增大总物理厚度相同。这样将界面层厚度保持在基本上恒定的厚度是期望的，因此在最大CET益处厚度42之上和窗口36外面的总物理厚度增大主要是由于高k电介质层厚度的增大。
图6是示出针对若干目标厚度的等效氧化物厚度(EOT)(在竖轴上)对比高k电介质层的目标物理厚度(在横轴上)的图形表示视图50，其中，第一组52未经过根据本公开的实施例的处理而第二组54经过根据本公开的实施例的处理。从图形表示视图50可以看出，用数据点的适当曲线拟合，对于第一组52的高k电介质层的
Figure GPA00001009799400051
的物理厚度而言，IL层的EOT在
Figure GPA00001009799400052
左右。对于第二组54的高k电介质层的
Figure GPA00001009799400053
的物理厚度而言，IL层的EOT在
Figure GPA00001009799400054
左右。约
Figure GPA00001009799400055
的差表示用本公开的实施例处理的高电介质层的近似IL层厚度减小。而且，用本公开的实施例处理的高k电介质层的所示数据点(由线54上的开放矩形指示)在物理上薄于未经本公开的实施例处理的高k电介质层的相应数据点(由线52上的实心矩形指示)。
现在，应认识到已提供了一种在半导体层上制造半导体器件的方法，包括：形成栅电介质，其中，形成所述栅电介质包括在半导体层上沉积包括锆酸铪的高k电介质；在含有氢和氮的环境中在650摄氏度与850摄氏度之间的温度下对高k电介质进行退火；以及在所述高k电介质上形成栅电极。退火步骤的特征还在于包括由氨水、嘧啶、以及联胺所构成的组中的一种的环境。在另一实施例中，沉积步骤的特征还在于锆酸铪包括HfZrO4。在另一实施例中，退火步骤的特征在于温度不超过800摄氏度。在另一实施例中，退火步骤的特征还在于温度不超过750摄氏度。在又一实施例中，退火步骤的特征还在于温度约为700摄氏度。
在另一实施例中，形成栅极的步骤包括沉积由氮化钛、碳化钽、氮化钼、以及氧氮化钼所构成的组中的一种。退火步骤的特征还在于高k电介质在退火步骤之后是连续的。
在另一实施例中，形成栅电介质的步骤还包括在执行沉积步骤之前在半导体层上形成第一厚度的界面氧化物。退火步骤将该界面氧化物减小至小于第一厚度的第二厚度，其中，所述第二厚度小于10埃。另外，退火步骤的特征还在于减小高k电介质的厚度。
在另一实施例中，一种在半导体层上形成半导体器件的方法，包括：直接在半导体层上形成界面氧化物；直接在该界面氧化物层上沉积一层锆酸铪；在含有氢和氮的环境中在650摄氏度与750摄氏度之间的温度下对锆酸铪进行退火；以及在所述锆酸铪上形成栅电极。退火步骤的特征还在于包括由氨水、嘧啶、以及联胺所构成的组中之一的环境。沉积步骤的特征还在于锆酸铪包括HfZrO4。退火步骤的特征还在于减小界面层的厚度和锆酸铪的厚度。形成界面氧化物的步骤的特征还在于所述界面氧化物包括氧化硅。此外，减小界面氧化物的厚度的步骤将界面氧化物的厚度减小至小于10埃。
在一个实施例中，一种在硅层上形成半导体器件的方法，包括：直接在半导体层上形成二氧化硅层，其中所述二氧化硅层具有厚度；直接在所述二氧化硅层上沉积锆酸铪，其中，所述锆酸铪层具有厚度，在含有氢和氮的环境中在约650摄氏度与约750度之间的温度下对锆酸铪层进行退火，这减小二氧化硅层的厚度和锆酸铪层的厚度；以及在所述锆酸铪层上形成栅电极。在一个实施例中，沉积锆酸铪的步骤的特征还在于锆酸铪层包括HfZrO4；对锆酸铪层进行退火步骤的特征还在于应用由氨水、嘧啶、以及联胺所构成的组中的一种。在另一实施例中，退火步骤的特征还在于温度约为700摄氏度。
说明书和权利要求中的诸如“前”、“后”、“顶”、“底”、“上”、“下”等相关术语(如果有的话)用于说明的目的且不一定用于描述永久性相对位置。应理解的是，这样使用的术语在适当的情况下可互换，使得本文所述的本发明的实施例例如能够在不同于本文所示或所述的其它取向进行操作。
虽然本文参照特定实施例来描述本发明，但在不脱离如以下权利要求所阐述的本发明的范围的情况下可以进行各种修改和变更。例如，所述方法可以应用于在高度缩放的CMOS、3D集成、MRAM、嵌入式NVM、嵌入式SRAM、及其它半导体器件应用中使用的高k电介质。因此，应将说明书和附图视为说明性意义，而不是限制性意义，且所有此类修改意图包括在本发明的范围内。本文相对于特定实施例所描述的任何益处、优点、或问题的解决方案并不意图被理解为任何或全部要求保护的范围的关键、必要、或本质特征或要素。
本文所使用的术语“耦合”并不意图局限于直接耦合或机械耦合。
此外，本文所使用的术语“一个”或“一种”被定义为一个或多于一个。而且，不应将权利要求中的诸如“至少一个”和“一个或多个”等介绍性短语的使用理解为暗示用不定冠词“一个”或“一种”来介绍另一权利要求要素使包含这样介绍的权利要求要素的任何特定权利要求局限于仅包含一个此类要素的发明，即使当该权利要求包括介绍性短语“一个或多个”或“至少一个”和诸如“一个”或“一种”的不定冠词时。这也适用于定冠词的使用。
除非另有说明，诸如“第一”和“第二”等术语用来任意地区别此类术语所描述的要素。因此，这些术语不一定意图指示此类要素的时间或其它优先次序。

Claims (20)

1.一种在半导体层上制造半导体器件的方法，包括以下步骤：
形成栅电介质，其中，形成所述栅电介质包括在半导体层上沉积包括锆酸铪的高k电介质；
在含有氢和氮的环境中在650摄氏度与850摄氏度之间的温度下对所述高k电介质进行退火；以及
在所述高k电介质上形成栅电极。
2.权利要求1的方法，其中，退火步骤的特征还在于所述环境包括由氨水、嘧啶、以及联胺所构成的组中的一种。
3.权利要求1的方法，其中，沉积步骤的特征还在于所述锆酸铪包括HfZrO4。
4.权利要求1的方法，其中，退火步骤的特征还在于温度不超过800摄氏度。
5.权利要求4的方法，其中，退火步骤的特征还在于温度不超过750摄氏度。
6.权利要求5的方法，其中，退火步骤的特征还在于温度约为700摄氏度。
7.权利要求1的方法，其中，形成栅极的步骤包括沉积由氮化钛、碳化钽、氮化钼、以及氧氮化钼所构成的组中的一种。
8.权利要求1的方法，其中，退火步骤的特征还在于所述高k电介质在退火步骤之后是连续的。
9.权利要求1的方法，其中，形成栅电介质的步骤还包括在执行沉积步骤之前在所述半导体层上形成第一厚度的界面氧化物。
10.权利要求9的方法，其中，退火步骤将所述界面氧化物减小至小于所述第一厚度的第二厚度，其中，所述第二厚度小于10埃。
11.权利要求10的方法，其中，退火步骤的特征还在于减小所述高k电介质的厚度。
12.一种在半导体层上形成半导体器件的方法，包括以下步骤：
直接在半导体层上形成界面氧化物；
直接在该界面氧化物层上沉积锆酸铪的层；
在含有氢和氮的环境中在650摄氏度与750摄氏度之间的温度下对所述锆酸铪进行退火；以及
在所述锆酸铪上形成栅电极。
13.权利要求12的方法，其中，退火步骤的特征还在于所述环境包括由氨水、嘧啶、以及联胺所构成的组中的一种。
14.权利要求13的方法，其中，沉积步骤的特征还在于所述锆酸铪包括HfZrO4。
15.权利要求14的方法，其中，退火步骤的特征还在于减小所述界面氧化物层的厚度和所述锆酸铪的厚度。
16.权利要求15的方法，其中，形成界面氧化物的步骤的特征还在于所述界面氧化物包括氧化硅。
17.权利要求16的方法，其中，减小界面氧化物的厚度的步骤将所述界面氧化物的厚度减小至小于10埃。
18.一种在硅层上形成半导体器件的方法，包括以下步骤：
直接在半导体层上形成二氧化硅层，其中所述二氧化硅层具有厚度；
直接在所述二氧化硅层上沉积锆酸铪层，其中，所述锆酸铪层具有厚度，
在含有氢和氮的环境中在约650摄氏度与约750度之间的温度下对所述锆酸铪层进行退火，由此减小所述二氧化硅层的厚度和所述锆酸铪层的厚度；以及
在所述锆酸铪层上形成栅电极。
19.权利要求18的方法，其中：
沉积锆酸铪层的步骤的特征还在于所述锆酸铪层包括HfZrO4；以及
对锆酸铪层进行退火的步骤的特征还在于采用由氨水、嘧啶、以及联胺所构成的组中的一种。
20.权利要求18的方法，其中，退火步骤的特征还在于温度约为700摄氏度。
CN200880100700A 2007-07-30 2008-06-16 处理高k电介质以实现CET缩放的方法 Pending CN101765903A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/830,331 2007-07-30
US11/830,331 US20090035928A1 (en) 2007-07-30 2007-07-30 Method of processing a high-k dielectric for cet scaling
PCT/US2008/067079 WO2009017888A1 (en) 2007-07-30 2008-06-16 Method of processing a high-k dielectric for cet scaling

Publications (1)

Publication Number Publication Date
CN101765903A true CN101765903A (zh) 2010-06-30

Family

ID=40304706

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880100700A Pending CN101765903A (zh) 2007-07-30 2008-06-16 处理高k电介质以实现CET缩放的方法

Country Status (6)

Country Link
US (1) US20090035928A1 (zh)
EP (1) EP2176879A1 (zh)
JP (1) JP2010535428A (zh)
CN (1) CN101765903A (zh)
TW (1) TW200913079A (zh)
WO (1) WO2009017888A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011005718B4 (de) * 2011-03-17 2012-10-31 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zum Verringern der Äquivalenzdicke von Dielektriika mit großem ε in Feldeffekttranistoren durch Ausführen eines Ausheizprozesses bei geringer Temperatur
US8421132B2 (en) * 2011-05-09 2013-04-16 International Business Machines Corporation Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
KR101799146B1 (ko) 2012-04-05 2017-11-17 도쿄엘렉트론가부시키가이샤 반도체 디바이스의 제조 방법 및 기판 처리 시스템
KR102428659B1 (ko) 2015-08-24 2022-08-04 삼성전자주식회사 반도체 소자의 제조 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444555B2 (en) * 1999-12-07 2002-09-03 Advanced Micro Devices, Inc. Method for establishing ultra-thin gate insulator using anneal in ammonia
US6432779B1 (en) * 2000-05-18 2002-08-13 Motorola, Inc. Selective removal of a metal oxide dielectric
US6300202B1 (en) * 2000-05-18 2001-10-09 Motorola Inc. Selective removal of a metal oxide dielectric
US6448192B1 (en) * 2001-04-16 2002-09-10 Motorola, Inc. Method for forming a high dielectric constant material
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
US6902681B2 (en) * 2002-06-26 2005-06-07 Applied Materials Inc Method for plasma etching of high-K dielectric materials
KR100450681B1 (ko) * 2002-08-16 2004-10-02 삼성전자주식회사 반도체 메모리 소자의 커패시터 및 그 제조 방법
JP2004311782A (ja) * 2003-04-08 2004-11-04 Tokyo Electron Ltd 成膜方法及び成膜装置
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
KR100555543B1 (ko) * 2003-06-24 2006-03-03 삼성전자주식회사 원자층 증착법에 의한 고유전막 형성 방법 및 그고유전막을 갖는 커패시터의 제조 방법
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
US7071038B2 (en) * 2004-09-22 2006-07-04 Freescale Semiconductor, Inc Method of forming a semiconductor device having a dielectric layer with high dielectric constant
US7217643B2 (en) * 2005-02-24 2007-05-15 Freescale Semiconductors, Inc. Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures
US7531399B2 (en) * 2006-09-15 2009-05-12 Taiwan Semiconductor Manufacturing Company Semiconductor devices and methods with bilayer dielectrics

Also Published As

Publication number Publication date
US20090035928A1 (en) 2009-02-05
JP2010535428A (ja) 2010-11-18
TW200913079A (en) 2009-03-16
WO2009017888A1 (en) 2009-02-05
EP2176879A1 (en) 2010-04-21

Similar Documents

Publication Publication Date Title
Khanna et al. Short-channel effects in MOSFETs
CN101421850B (zh) 多介质finfet结构和方法
US9997629B2 (en) FinFET with high mobility and strain channel
US6921913B2 (en) Strained-channel transistor structure with lattice-mismatched zone
US7709331B2 (en) Dual gate oxide device integration
EP1593161B1 (en) Strained channel finfet
US11637193B2 (en) Gate-all-around field effect transistor and method for manufacturing same
US6518634B1 (en) Strontium nitride or strontium oxynitride gate dielectric
US6812119B1 (en) Narrow fins by oxidation in double-gate finfet
US20080272366A1 (en) Field effect transistor having germanium nanorod and method of manufacturing the same
CN100485962C (zh) 半导体器件及其制造方法
US20130043515A1 (en) Strained Channel Field Effect Transistor and the Method for Fabricating the Same
US20080311713A1 (en) Mobility enhancement by strained channel cmosfet with single workfunction metal-gate and fabrication method thereof
WO2013095779A1 (en) Soi finfet with recessed merged fins and liner for enhanced stress coupling
US6287897B1 (en) Gate dielectric with self forming diffusion barrier
Migita et al. Electrical performances of junctionless-FETs at the scaling limit (L CH= 3 nm)
US20090261381A1 (en) CMOS transistor using germanium condensation and method of fabricating the same
CN1349249A (zh) 制造半导体侧壁翼片的方法
CN101388340A (zh) 金属高k晶体管及其制备方法
US20020142523A1 (en) Method of fabricating semiconductor device having notched gate
US6991990B1 (en) Method for forming a field effect transistor having a high-k gate dielectric
TW200937535A (en) A hetero-structured, inverted-T field effect transistor
CN102044566A (zh) 半导体元件与其制作方法
US8790972B2 (en) Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment
CN101765903A (zh) 处理高k电介质以实现CET缩放的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20100630