TW200840011A - Film-on-wire bond semiconductor device and method of forming the same - Google Patents

Film-on-wire bond semiconductor device and method of forming the same Download PDF

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Publication number
TW200840011A
TW200840011A TW096145470A TW96145470A TW200840011A TW 200840011 A TW200840011 A TW 200840011A TW 096145470 A TW096145470 A TW 096145470A TW 96145470 A TW96145470 A TW 96145470A TW 200840011 A TW200840011 A TW 200840011A
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Taiwan
Prior art keywords
semiconductor die
intermediate layer
semiconductor
die
layer
Prior art date
Application number
TW096145470A
Other languages
English (en)
Inventor
Hem Takiar
Shrikar Bhagath
Chin-Tien Chiu
Ong King Hoo
Original Assignee
Sandisk Corp
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Publication date
Priority claimed from US11/566,097 external-priority patent/US20080131998A1/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200840011A publication Critical patent/TW200840011A/zh

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Description

200840011 九、發明說明： 【發明所屬之技術領域】 本發明的實施例與一低剖面半導體裝置及其製造方法有 關。 【先前技術】 kl 對可檇式电子產品要求的急速增長刺激了對高容量儲存 裝置的需求。非揮發性半導體記憶體裝置，如快閃記憶 卡已被廣泛使用以滿足對數位資訊儲存和交換日益增長 • @要求。它們的輕便性、多樣及穩健的設計還有其高可靠 性和大容量，使得此類記憶體裝置成為許多電子裝置中的 理想使用產品’這些電子裝置包括諸如數位相機、數位音 樂播放器、電玩控制台、個人數位助理（pDA)和手機。 人們已知多種封裝配置，而快閃記憶體卡一般製造作為 安裝於一基板。基板一般包括一個堅硬的、介電質基座， 馨此基座的一面或兩面都蝕刻有導電層。在晶粒和導電層之 間形成電連接，導電層為晶粒與主裝置連接提供一條電引 線結構。一旦晶粒與基板之間的電連接建立起來，一般就 將該裝配件裝入一成型的化合物中作為保護封裝。 . 圖1所示是一傳統的半導體封裝18(無成型化合物）。业 型的封裝包括複數個半導體晶粒的組合。晶粒可透過晶粒 附者黏著層24附著於一基板上。一般而言，基板u是由一 堅硬聚醯亞胺的核心28組成的。使用已知的微影和餘刻製 程，在核心上以所要求的電引線圖案形成薄膜銅層儿。傳 127011.doc 200840011 導圖案的暴露表面可用電鐘的製程鍍金-層或多層，以形 成用於半導體晶粒與基板的電連接、基板與主裝置之間的 !連接的㈣。可料接遮罩36將㈣基板，而使襯墊裸 路，以使在基板上形成的電引線圖案與其絕緣進
護作用。而本逡雜曰， J 而丰¥體晶粒上的連結墊可由線連結34與基板上 的鍍層襯墊電連接。 ,我們已經知運’以偏置或堆疊結構使半導體晶粒互相在 彼此=層層疊放。在—偏置裝置中，—個晶粒是被放置 ； 米之上的，致使較低晶粒的連結塾裸露。偏置妒 置的優勢是每個半導體晶粒上更易獲得連結墊。然而，偏 置結構需要在基板上使用更大的佔用面積，而基板的面積 卻很有限。 在一堆疊的結構中，如圖丨所示的先前技術，兩個或更 夕的半導體晶粒相互直接堆疊在彼此頂部，與偏置結構相 匕車又&樣在基板上佔據的面積較少。然而，在堆疊結構 中’相鄰半導體晶粒之間需留有空隙，以安置線連結路 34。除了連結線路34本身的高度，在連結線上方還要有額 外工間’因為-個晶粒與下_個晶粒之間的連結線Μ的接 觸，會導致短路。正如圖！和圖2的放大圖所示，已知將相 鄰兩個半導體晶粒間的線連結回路埋於個別晶粒間的黏著 層26。此等結構顯示於如下專利中：^等人之美國專利 第6,388,313號，標題為，，多晶粒模組,，，及以叩等人之美國 專利案第7,037,756號’標題為"堆疊微電子裝置及其製造 方法這I麥考文獻闌釋了本發明之先前技術圖^和圖2 127011 ,d〇c 200840011 一黏著層26之 回路與上部晶 的半導體晶粒封裝，其中線連結回路掩埋於 内，層26具有—定厚度，其足以防止線連結 粒2 0較低的面發生短路。 -直存在-種要使記憶體模組增加儲存容量的驅動力。 一個增加儲存容量的方法是增加 沾叙旦虹 内所用的記憶體晶粒 的數里。對於可檇式記憶體封裳， W用的晶粒數量要受到 封裝厚度的限制。由此，減小封裝容 M, ^ ^ ^ 里的；度，亚增加記 fe體岔度成了熱切關注的重點
圖和圖2中所示的封 衣1 8要求黏著層26將半導體晶 々阳风比窝要的更厚以確 保在生產製造時線連結回路是掩 丄、· 岭疋掩埋的，不碰觸下一個相鄰 + :體晶粒的下面。這額外的黏著層厚度對具有多於兩個 堆疊的晶粒和具有嵌人線連結回路的多個黏著層的封裝更 是一大問題。 【發明内容】 轉明的-實施例與_至少包括安裝於_基板的第一個 和第二半導體晶粒的低剖面半導體封裝有關。第—和第二 半導體晶粒由一低剖面中間黏著層隔開，帛一半導體晶粒 及基板間的線連結回路便是嵌入該中間黏著層上。中間層 :以是作為塗在第一半導體晶粒上的黏著液體的電絕緣： 虱化合物。可將中間層塗在第一半導體晶粒的至少大體上 正個表面上，或者是僅以離散量塗在第一半導體晶粒的連 結塾上。 塗上中間層之後，第二半導體晶粒被堆疊在中間層頂部 上。依據本發明，第二半導體晶粒和中間層之間介面處可 127011.doc 200840011 需形成一介電層。在實施例中，可透過各種已知的方法使 介電層在第二半導體晶粒的背面形成，例如將環氧化合物 壓成片狀，或在取得第二半導體晶粒之半導體晶圓的製造 期間生長或沈積介電膜。在研磨晶圓背面使其到達所需要 厚度的情況中，介電層是在背面研磨製程之後、裝配到第 一半導體晶粒之前形成的。 因為第二半導體晶粒的背面是電絕緣體，在先前技術
中，中間層無需將從第二半導體晶粒的線連結回路隔開: 而且連結線前端會與介電層接觸。因此與傳統的堆疊半導 體晶粒配置相Λ，第一及第二堆疊半導體晶粒間的間隔需 做得更薄°第二半導體晶粒還需在_強壓下黏著，以減小 中間層的厚度’還需局部分平坦化第一半導體晶粒表面上 的線連結回路高度。 一旦所有的半導體晶粒附著、線路連結到基板上，便可 藉由如加熱及/或紫外線來固化半·導體封裝。在另一實施 例，中間層可在第二半導體晶粒附著之前固化。 貝 【實施方式】 現參考圖3 Α至13來描述實施例，該等圖式與一低剖面半 導體封裝有關。應明白，本發明可以多種不同形式實施， 並非限於本文所陳述的實施例。q，提供這些實施例， 所表述的就可㈣完整’從而將本發明全方位地傳達給孰 悉此項技術者。事實上，本發明包含附屬請求項中所定義 的本發明的精神與範圍内之此等實施例的可供選擇的方 法、修正、和同等物。另外 门4物另卜在下列本發明的詳盡描述 127011.doc 200840011 日中’陳述了許多特定的細節’以期讀者可透徹地瞭解本發 月。然而’-般技術者將清楚，本發明也可在無這些特定 細節的情況下實施。 /考圖3A的流程圖和圖‘13的侧視圖與俯視圖，對本發 明進行描述。本發明實施列與一半導體封裝8〇有關，封^ 80的一部A包括纟步驟2〇〇中安裝於一基板⑽的第一半導 體晶粒100，如圖4和5中所示。晶粒100在已知的黏著或晶 ，連結製程中可透過晶粒附著黏著層1G4安裝於基板102。 曰曰粒附著黏著層1G4可以是如結構已知的環氧化合物，曰 本Nm〇 Denko公司、加州Abelstik公司和加州公司 均有售。如下文所解釋的，黏著層1〇4可用作黏著液體， 其在回焊製程中固化之前一直保持該狀態。 儘官之於本發明並非關鍵，基板1〇2可有多種不同的晶 片承載媒介，包括一 PCB、一引線框、一捲帶式自動連結 (TAB)捲帶。當基板1〇2是一 pCB時，基板可由一包括於其 上形成的一頂部和/或底部導電層的核心組成。核心可以 疋各種介電材料，例如，聚硫亞胺壓片、包括fr4和fr5 的環氧樹脂、雙馬來亞醯胺三氮六環（bismaleimide triazine，BT)或此類物質。 導電層可由所知的用於基板上的銅、銅合金、鍍銅、鍍 銅合金、合金42(42FE/58NI)、銅鍍鋼或其他金屬或物質組 成。導電層可蝕刻至一用於半導體晶粒和外部裝置之間信 號交流的傳導圖案上。在導電層中，還用到虛設圖案，是 為了減小由於基板内不均勻的熱膨脹而造成的在基板上的 127011.doc -10- 200840011 機械應力。基板ι〇2還另包括組成接觸墊(圖5)和/或接 觸指狀元件（如一例子中，封裝80是一 LGA封裝）的裸露金 屬片段。可將接觸墊和指狀元件上鍍金一層或多層，例如 透過一此項技術中已知的電鍍製程。 步驟200中’將半導體晶粒100安裝至基板102後，連結 線106可在晶粒1〇〇上的連結墊1〇8(圖5)和步驟中基板 102上的連結墊110之間附著。連結線ι〇6可透過一已知的 線連結製程安裝。在實施例中，線連結製程可以是低剖面 線連結製程，例如反轉連結製程。在圖4和5中，晶粒1〇〇 的兩相對的側面上有線連結。在本發明的另一實施例中， 線連結106可設在晶粒100的一邊、三邊或四邊。 在步驟204中，可在晶粒1〇〇的暴露表面塗上中間層 120。中間層12〇是已知組成物的電絕緣黏性環氧化合物， 日本NiU〇 Denk0公司、加州Abelstik公司和加州公 司均有售。中間層120用作黏著液體，在下文所解釋的回 焊製程之前一直保持黏著液體的狀態。在實施例中，中間 層120是被視為液體使用的，但是卻有相當強的黏性以在 機械上支撐置KKO上的第二半導體晶粒。在實施例中， 黏性可達如約1-2X1G6厘泊，但應明自，在其他的實施例 中，黏度可高於或低於該值。中間層的材料可與用作黏著 層104的材料一樣或不同。在另一實施例中，在中間層12〇 内會用到隔離球狀物。隔離球狀物可以是聚合物球體，作 為晶粒100和其上安裝的一第二晶粒之間的隔離物。此類 隔離球狀物在此項技術中是廣4人知❸，例如在美國專利 12701 l.doc • 11 - 200840011 案第6,650,019號中即有闡述，其標題為：，，包括堆疊半導 體晶粒的半導體封裝之製造方法”，其專利的全部内容以 引用的方式併入此文。 如圖4和5，在一實施例中 可將中間層120塗在晶粒1 〇〇
的至/大體上整個表面上（部分邊緣可能有黏性物質，也 可能沒有）。層120的黏著材料塗布致使線連結回路1〇6部 分掩埋在層12〇中。也就是說，與連結塾⑽相鄰的線連結 106的部分以及連結回路的前端部分都掩埋於中間層 中。因中間層12〇僅塗在晶粒1⑽的表面上，從晶粒1〇〇佔 用面積延伸出來的線106的部分並未嵌入在中間層120中。 不僅將封裝80内堆疊的半導體晶粒黏著在一起中間層 12 0還使兩個堆疊的半導體晶粒之間空出一些空間以容納 線連結回路1G6的位置1而，從下—個相鄰的半導體晶 粒’中間層上並不需要額外的空間去分隔線連結回路 106。尤其在先前的技術中’連結線所嵌入的黏著層需足 夠厚以確保連結線不會受下—個㈣晶粒下表面短路的影 響。然而，在下文更詳盡的描述中，附著於中間層12〇上 的第二晶粒的表面是電絕緣體。依此，不同於先前技術， 從下-個相鄰的晶粒開始]間層12〇不需分隔線連結回 路106 ’而較之傳統堆疊半導體晶粒構造，堆疊晶粒間的 間隔j薄。例如’中間層12〇的厚度可以是25_5〇㈣，而 在先前技術中是75 μηι。應明白，在本發明的其他實施例 中’中間層120的厚度也可小於25_或大於5〇_。 如上所指示的，在步驟·中’可將一第二半導體晶粒 127011.doc •12- 200840011 122堆疊在中間層12〇上，如圖6和7所示。根據本發明，在 半導體晶粒122和中間層120之間的介面處可形成介電層 130。在實施例中，介電層13〇也可在半導體晶粒122背面形 成。介電層130可透過各種已知的方法在半導體晶粒122上 形成。在一實施例中，層13 〇可以是一壓貼於半導體晶粒 122背面的黏性環氧化合物，並如下文所說，在中間層 之前或和其一起被固化。介電層13〇還可在半導體晶粒122 製造過程中形成於晶圓級。例如，當晶圓未經背面研磨 時，可在半導體的製造過程中生長介電層13〇。介電層 還可透過各種製程，包括化學電鍍、化學氣相沈 * 只 / νΓΛ 發、喷濺、鐳射沈積、分子光束磊晶術、噴射、噴繪、絲 網印刷術在半導體晶粒122的背面上沈積介電膜而獲得。在 晶圓未經背面研磨的情況下，會在晶圓的製造過程中沉積 介電膜。在晶圓受到背面研磨的情況下，會在背面研磨製 程之後、晶粒122被附著於中間層12〇之前沉積介電膜。這 可以是在晶粒122從晶圓上分割之前或之後。也考慮形成介 電層130的其他沈積方法或技術。在實施例中，介電層 的厚度在10 μηι和20 μιη之間，但應明白，介電層13〇的厚度 可小於或大於本發明之替代實施例中之介電層厚度。 大於2 0也可小於1 〇。 一旦晶粒122附著於中間層12〇，在步驟21〇中可用已知的 線連結製程中之連結線124將晶粒122線連結於基板1〇2。 本發明的實施例中，可能只有一對半導體晶粒1〇〇和 122。但是在進一步的實施例中，有多於兩個半導體晶粒 127011.doc -13- 200840011 互相堆疊。在這樣的實施例中，如圖3A的虛線所指示，步 驟204 ’以較上層的晶粒的上纟面塗上黏㈣，步驟 即附著另θθ粒，步驟21 〇，即給每個堆疊在晶粒 122上的另外的半導體晶粒重複線連結另一晶粒。 正如上文所指出的，在中間層12〇上施加可有效地支撐 半導體晶粒122的黏性，而不用過度平坦化線連結回路
106仁是，虽半導體晶粒122附著於中間層〗2〇，需在中 間層施加壓力以減小中間層12〇的厚度。這樣做，連結線 106的前端就會接觸介電層13〇，如圖7所示。但是，由於 介電層130將連結線1〇6的每股相互隔開、同時也與半導體 晶粒122分隔，因此不會發生短路。 如圖8，進一步的實施例，需用一壓縮負載將半導體晶 粒122安瓜至封裝14〇，以減小中間層12〇的厚度，如上文 所述，另外局部平坦化半導體1〇〇表面上方連結線1〇6的高 度。層120的厚度和連結線1〇6的高度應減小到一不影響連 接至半導體晶粒1〇〇上連結線的結構完整之值。如上文所 述在貝施例中，該厚度是在25 μπι至50 μηι之間，而在其 他實施例中，也可小於25 μπι或大於5〇 μιη。 一旦所有的半導體晶粒都安裝妥當，且線連結至基板 1〇2上，在步驟212的回焊製程中，半導體封裝8〇會被固 化，以使包括中間層12〇和晶粒附著層1〇4的各黏著層變 更可用各種已知的方法固化，包括諸如加熱和/或紫外 線；固化取決於黏性材料。 在以上參考圖3Α的流程圖所描述的實施例中，封裝肋是 1270Il.doc 14 200840011 在所有的半導體晶粒均堆疊好、連結線完成後才固化。在 參考圖3B的流程圖所描述的本發明的另一實施例中，在安 裝半導體晶粒122之前，中間層12〇和晶粒連結層1〇4可在 步驟206固化（本實施例中，層1〇4和12〇可在步驟2〇6中同 時固化或先後固化）。在該實施例中，介電層π〇可以是或 包括一可固化黏著劑，這樣半導體晶粒丨22就可以附著於 一固化的中間層120，其後並在後續固化製程中牢牢附 著。還考慮晶粒連結層104和/或中間層120在步驟206中可 部分固化至b-階段。而半導體晶粒丨22完全安裝好後，就 可使層104和/或106全部固化。 在上述實施例中，中間層i2〇可以是黏性材料。但是， 應明白，當130是黏性材料時，中間層12〇就無需是黏性材 料。在此實施例中，層12〇被用作連結線1〇6周圍的液體塗 上’僅充當分隔晶粒1 〇〇和12〇、使連結線丨〇6的每股相互 絕緣的間隔層。此實施例中，晶粒1〇〇和122透過電絕緣黏 著層130相互附著。 圖9-12所示的是本發明的另一實施例。在該實施例中， 並不疋在半導體晶粒1 〇〇的大體上整個表面塗上中間層 120，而是僅作為離散量的黏性材料144塗在半導體晶粒 100上之接觸墊108上並與其鄰接。特別地，黏性材料144 可塗在包括連結墊108之半導體晶粒ι〇〇的第一區域，而不 塗在不包括連結墊的第二區域。該實施例適用於當接觸墊 108的一面、兩面、三面或四面在半導體晶粒1⑽上時。 在另一實施例中，如圖丨丨和12所示，當第二半導體晶粒 127011.doc -15- 200840011 122附著於封裝時，需用壓縮力稍加平坦化黏著層Μ#。如 上文所指，除了平坦化黏著層144，壓縮力還可減小半導 體晶粒100表面上線連結回路1〇6前端的高度。其後，在固 化製程中，黏性區域可進一步平坦化，以使黏著層144延 展到晶粒1〇〇的表面。應明白，液體黏著層144並非一旦與 晶粒122附著後及/或在後續固化製程後，即覆蓋晶粒1〇〇 的整個表面。另外，在有些實施例中，半導體晶粒122上 的介電層130亦由可固化的黏著劑組成，黏性材料144和介 電層130會在晶粒100和122之間的介面鋪展開來以填充其 間的空隙。 圖9-12所示實施例中，一旦晶粒122附著於晶粒1〇〇，第 一半導體曰曰粒12 2便連同線連結12 4透過一已知的線連結方 法線連結至基板102。接著封裝如上所述被固化。 在上述這些實施例中，從晶粒1〇〇和122出來的連結線可 以是未塗布的金，但也可是銅、鋁或其他金屬。在本發明 的進一步實施例中，晶粒100和/或122的連結線用絕緣聚 合物事先（如在被嵌於中間層120之前）絕緣的，以使電線表 面為電絕緣。已知此類事先絕緣連結線是為了防止相鄰連 結線間發生短路。適合本發明使用的事先絕緣連結線之兩 例揭露於：美國專利申請案第5,396,104號，標題為：”樹 脂塗層連結線及其製造方法，以及半導體裝置，，及美國公 開專利申請案第2004/0124545號中，標題為：π高密度積 體電路及其封裝方法”，其全部内容以引用的方式併入本 文。使用事先絕緣連結線的實施例可在具備或不具備中間 1270ll.doc -16 - 200840011 層120的情況下操作。在沒有中間層12〇的情況下操作的此 類實施例中’介電層13〇是用於附著晶粒的黏著劑。 如圖13，根據以上任何所述實施例，堆疊的晶粒結構形 成之後，在步驟214中，該架構被包入一成型化合物15〇， 而在步驟216中’被單一化’以形成一完成的半導體晶粒 封裝160。成型化合物15〇是已知的一種環氧化合物，如 Sumit〇m_ Nitt〇 Denk〇公司均有售，這兩家公司總部都在 日本。然後，在步驟218中，完成的封裝⑽可視需要封入 一蓋子。 在很多實施例中，上述半導體晶粒可包括—個或多個快 閃記憶體晶片、控制器如專用積體電路，這樣，封裝WO 就可用作快閃記憶體裝置。應明白，在本發明的進：步實 施例中，封裝160可包括配置的半導體晶粒以發揮其他^ 用。 幻文對於本鲞明的詳盡描述旨在解析和說明，而非將本 發明拘泥於此。從上述教示，也可作出修改和變化。選擇 這些說明的實施例，是為了儘可能以最佳方式解釋本發明 的規則和實際應用，則吏熟悉此項技術者在各種實施例中 且在各種修改下利用本發明。預期本發明範疇如附屬請求 項所定義。 【圖式簡單說明】 ，是-傳統的包括安裝在—基板上的堆疊半導體晶粒 的半導體封裝的剖面側面圖。 圖2是圖工中半導體封裝一部分的放大剖面側面圖。 1270Il.doc -17- 200840011 圖3 A是依據本發明_每 流程圖。 ““列的半導體封裝的製造方法的 圖3B是依據本發明的一每 法的流程圖。 則的丰導體封裳的製造方 側面 圖 圖4是本發明產品製造中半導體封裝-部分的剖面 圖5是圖4所示的本發明丰遙 月牛導體封裝的-部分的俯視圖。 圖6疋本發明產品製 圖 衣、〒牛V體封裝一部分的剖面側面 圖 圖7是本發明產品製造中半導體封裝一部分 的剖面側面 圖8是本發明產品製造中另一實 分的剖面側面圖。 圖9是本發明產品製造中又一 、——，…1 驵対裝一部 分的剖面侧面圖。 圖1〇是圖9的又一實施例中半導體封裝的一 施例中半導體封裝一 施例中半導體封裝一 部 圖 部分的俯視 的剖面側 圖11是圖9的產品製造中半導體封裝的一部分 面圖。 圖 圖12是圖9的產品製造中半導體封裝一部分的 剖面側面 面側面 圖 圖13是依據本發明實施例的一半導體封裝的剖 〇 【主要元件符號說明】 127011.doc -18- 200840011
18 半導體封裝 20 上層晶粒 22 基板 24 晶粒附著黏著層 26 黏著層 28 核心 30 薄膜銅層 34 連結電線 36 焊合模版 100 晶粒 102 基板 104 黏著層 106 線連結回路 108 連結墊 110 連結墊 120 中間層 122 第二半導體晶粒 124 連結電線 130 介電層 144 黏著層 150 成型化合物 160 封裝 127011.doc -19-

Claims (1)

  1. 200840011 十、申請專利範圍： κ 一種半導體裝置，包括： 一包括第一、第-科罢主^ 乐一對置表面的第一半導體晶粒，該第 一表面包括複數個連結墊； 複數個連結線，該複數個連結線的每條連結線具有— 終端附著至該第—半導體晶粒的一結合墊； —施加於該第-1導體晶粒之該第-表面的一中間 層，該複數個連結線中每條連結線的-部分嵌於該中間 層； 一弟二半導體晶粒；和 ^ ^成於Α第一半導體晶粒之一表面的電絕緣層，該 第二半導體晶粒附著於該中間層，其中該電絕緣層與該 中間層相接觸，該電絕緣層使該第二半導體晶粒與該中 間層中的該等連結線相絕緣。 2. 如凊求項1之半導體裝置，其中該中間層覆蓋該第一半 導體晶粒的該第一表面的大體上全部。 3. 如請求項1之半導體裝置，其中該中間層覆蓋該第一表 面上包括該等連結線的一第一區域而不覆蓋該第一表面 上不包括該等連結線的一第二區域。 4.如請求項1之半導體裝置，其中該中間層是-黏著層， 用於使忒第一及邊第二半導體晶粒附著在一起。 5·如請求項!之半導體裝置，其中該中間層是一環氧化合 物層’用於使該第一及該第二半導體晶粒附著在一起。 6.如請求項丄之半導體裝置，其中該等連結線以一連結回 127011.doc 200840011 路的形式附著於該第一半導體晶粒，該中間層在該第一 半導體晶粒的該第一表面之上的高度約與該第一半導體 晶粒之該第一表面上最上部分之連結回路的高度相等。 7.如凊求項丨之半導體裝置，其中該複數個連結線經提供 鄰接於該第一半導體晶粒之該第一表面的_單邊。 8·如請求们之半導體裝置，其中該複數個連結線經提供 鄰接於《亥第一半導體晶粒之該第一表面的兩個相對的
    9. 10. 如凊求項1之半導體裝置，其中該複數個連結線經提供 於該弟半‘體晶粒之該第一表面的四個邊周圍。 如請求項1之半導體裝置’其中該中間層包括複數個隔 離球狀物。 11· 一種形成 、 ，一叫，•儿〜卞守瓶 裝置的方法，該方法包括以下步驟：
    (a)線連結複數條線至該第一半導體晶粒之一表面， 以形成複數條線連結回路； ⑻將複數條線連結回路中的每條線連結回路的一部 分嵌入施加於該第一半導體晶粒之該表面的一中間層； (c)在該第二半導體晶粒之一表 表面上形成一電絕緣 體；及 一半導體晶粒， 二半導體晶粒之. (d)將S弟一半導體晶粒附著於該第 其中該電絕緣體插入該中間層和該第 間0 12.如請求項11之方法，其 中把該複數條線連結回路中每股 127011.doc -2 - 200840011 線連結回路之一部分嵌入施加於該第一半導體晶粒之該 表面的該中間層的該步驟⑻包括用-液體覆蓋該第一半 導體a曰粒之該第一表面的至少大體上全部之步驟。 求項11之方法，其中把該複數條線連結回路中每股 線連結回路之一部分嵌入施加於該第一半導體晶粒之該 表面的該中間層的該步驟（b)包括覆蓋該表面包括該等線
    連、、Ό 口路的_第_區域而不覆蓋該表面不包括該等線連 結回路的一第二區域之步驟。 14·如明求項i!之方法，其中把該複數條線連結回路中每股 線連結回路之_部分嵌人該中間層的該步驟⑻包括施加 :液體於各線連結回路部分周圍之該第—半導體晶粒的 該表面之步驟。 月长項11之方法，還包括將該中間層變硬之步驟（e)。 16·如凊求項15之方法，其中使該中間層變硬之該步驟⑷是 在將该第二半導體晶粒附著於該第一半導體晶粒的該步 驟（d)之後發生。 17· $請求項16之$法，纟中將該第二半導體晶粒附著於該 第一半導體晶粒的該步驟（d)包括在該第一及該第二半導 體B曰粒對該中間層所施加的壓縮力下減小該中間層厚 度0 18·如請求項16之方法，其中將該第二半導體晶粒附著於該 第一半導體晶粒的該步驟（d)包括在該第一及該第二半導 體晶粒對該中間層所施加的壓縮力下減小該中間層内之 該等線連結回路的高度。 12701I.doc 200840011 19. 如請求項15之方法，其中使該中間層變硬之該步驟（e)是 在將該第二半導體晶粒附著於該第一半導體晶粒的該步 驟（d)之前發生。 20. 如請求項11之方法，其中在該第二半導體晶粒之一表面 形成一電絕緣體的該步驟（c)包括在該第二半導體晶粒之 該表面上層壓一介電膜之步驟。
    127011.doc
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