TW200818550A - Semiconductor light emitting element and method for manufacturing the same - Google Patents
Semiconductor light emitting element and method for manufacturing the same Download PDFInfo
- Publication number
- TW200818550A TW200818550A TW096124370A TW96124370A TW200818550A TW 200818550 A TW200818550 A TW 200818550A TW 096124370 A TW096124370 A TW 096124370A TW 96124370 A TW96124370 A TW 96124370A TW 200818550 A TW200818550 A TW 200818550A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- side electrode
- type semiconductor
- semiconductor light
- semiconductor layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
- H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/24998—Reinforcing structures, e.g. ramp-like support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Description
200818550 九、發明說明 【發明所屬之技術領域】 本發明係有關半導體發光元件及其製造方法。 【先前技術】 以往,作爲半導體發光元件,知道有半導體雷射或發 光二極體等(例如,參照下記之專利文獻1 ),一般,半導 體發光元件係具有省電且高亮度之特徵,例如,作爲、液晶 顯示裝置的光源所示用。 [專利文獻1] 日本特開2003-243773號公報 圖1 〇係表示以往之半導體發光元件的一例,而在所圖 示之半導體發光元件X中,於基板101上,層積有n-GaN 層102、活性層103、以及p-GaN層104,而n-GaN層102 及p-GaN層104係經由絕緣層107所被覆,絕緣層107係例 如由Si02而成,並形成有2個開口 107a,而此等開口 107a 係使n_GaN層102及p-GaN層104做爲部分地露出,而對 於n-GaN層102及p-GaN層104,係藉由開口 107a而各自 連接有配線108,配線108係由接觸於n-GaN層102或p-GaN層104之Ni層108a,和形成於Ni層108a上之Au層 l〇8b而成。 對於上述半導體發光元件X係有著如以下所述的問 題,即,針對在半導體發光元件X的製造工程’開口 107a 之形成,係經由對於被覆n-GaN層102及p-GaN層1〇4之 200818550 絕緣層而言,施以蝕刻所進行,此時,n-GaN層102及p-GaN層1 04則受到經由蝕刻之損傷,因此,在此等各層與 配線1 08之界面的電性電阻變大,半導體發光元件X之驅 動電壓則不當地變高。 作爲爲了對於上述問題作對策之方策之一,考兩有例 如,將Au而成之中繼電極(略圖示)形成於各開口 107a, 之後,形成配線1 〇 8者,此情況,期待經由該中繼電極, n-GaN層102或p-GaN層104與配線108之導通狀態成爲良 好者。 但,在另一方面,產生其他的問題,即,在高環境溫 度下進行配線1 〇 8之形成的情況,有著從上述中繼電極對 於絕緣層107有擴散Au之虞,其結果,絕緣層107之至少 一部分則成爲具有導電性,有著洩漏電流變大的問題。 【發明內容】 本發明係依上述的情事所構思的構成,因此,本發明 係其課題爲提供:可防止驅動電壓的增加,且抑制洩漏電 流之情況的半導體發光元件者。 經由本發明之第1的側面所提供之半導體發光元件係 具備:η型半導體層及p型半導體層,和挾持於上述η型 半導體層及上述ρ型半導體層之活性層,和與上述η型半 導體層接觸之η側電極,和與上述ρ型半導體層接觸之ρ 側電極,和被覆上述η型半導體層及上述ρ型半導體層, 且使上述η側電極及上述ρ側電極之一部分露出之絕緣層 200818550 ,而上述η側電極係由A1而成,且由與上述^型半導體 層接觸之第1層,和形成於其第1層上,且由Ni、W、Zr 及Pt之任一而成之第2層所構成,而上述p側電極係由 Au而成,且由與上述p型半導體層接觸之第1層,和形成 於其第1層上’且由Ni、W、Zr及pt之任一而成之第2層 所構成。 如根據如此構成’可享受到如以下之技術性效果者, 即,在形成上述η側電極及上述p側電極之後,對於上述 絕緣層而言’施以蝕刻之情況,只曝露各電極之中的上述 第2層於鈾刻,另一方面,其第2層係因由Ni、W、Zr及 Pt而成,故無經由蝕刻而其表面過大損害者,因此,可 縮小各電極及在與其導通之構件的界面電阻者,並可以低 電壓驅動半導體發光元件者,另外,針對在各電極,可經 由第2層而被覆第1層之上面全體者,此情況,針對在各電 極,可將與上述絕緣層接觸的幾乎部分,可作爲第2層(例 如,如適當薄化第1層之厚度即可),而形成上述第2層之 Ni、W、Zr或Pt係與Au不同,對於上述絕緣層而言不易 擴散,隨之,可防止上述絕緣層不當導體化之情況,可控 制上述半導體發光元件之洩漏電流者。 理想爲本發明之半導體發光元件係更加具備接觸於上 述η側電極(或p側電極)之配線,此配線乃包含第1層與 形成於此第1層上的第2層,配線之該第1層乃接觸於上述 η側電極(或ρ側電極)之上述第2層的同時,由與上述η側 電極(或ρ側電極)之上述第2層相同的材質所成,另外, -6- 200818550 上述配線之上述第2層乃由Au所成’如根據如此構成, 上述η側電極或p側電極與上述配縣係接合再由相互相同 材質而成的部分,由此,與接合同爲異種金屬之情況作比 較,更可縮小針對在上述各電極與上述配線之界面的電阻 者。 如根據本發明之第2的側面,提供具備η型半導體層 、和Ρ型半導體層、和挾於此等η型半導體層及ρ型半導 體層的活性層的半導體發光元件之製造方法,其製造方法 乃包含形成接觸上述η型半導體層之η側電極、形成接觸 上述Ρ型半導體層之Ρ側電極、形成被覆上述η型半導體 層、上述Ρ型半導體層、上述η側電極及上述ρ側電極的 絕緣層,對於上述絕緣層而言,經由施以蝕刻,露出上述 η側電極及上述Ρ側電極之一部分的各工程;上述η側電 極之形成乃經由在於上述η型半導體層上形成Α1所成第1 層、更且於此第1層上,形成Ni、W、Zr及Pt之任一者 所成第2層而進行,上述P側電極之形成乃經由在於上述 ρ型半導體層上形成Au所成第1層、更且於此第1層上, 形成Ni、W、Zr及Pt之任一者所成第2層而進行者。 如根據如此構成,針對在上述蝕刻,係上述n側電極 及上述ρ側電極之中,只有上述第2層曝露於飩刻,而上 述第2層係由Ni、W、Zr或Pt而成,故無經由蝕刻而其 表面有過大損害者’隨之,可縮小上述η側電極及上述ρ 側電極,和在與其導通之構件的界面電阻者,並可以低電 壓驅動半導體發光元件者。 200818550 本發明之其他特徵及利點係經由參照附加圖面而進行 以下詳細說明,而更爲清楚。 【實施方式】 [爲了實施發明之最佳型態] 以下,關於本發明之理想的實施型態,參照圖面而具 體進行說明。 圖1係表示依據本發明之半導體發光元件的一例,而 所圖示之半導體發光元件A係形成於基板1上,並具備: n-GaN層2、活性層3、p-GaN層4、η側電極5、p側電極6 、絕緣層7、以及配線8,而半導體發光元件Α係作爲透 過絕緣層7而射出光線的構成。 基板1係例如爲藍寶石製,並支撐n-GaN層2、活性 層3、以及ρ-GaN層等,基板1之厚度係例如作爲3 5 0 //m程 度。 n-GaN層2係爲摻雜Si於GaN的層,而n-GaN層2的 厚度係例如爲3.5//ΙΓ)程度,而對基板1與n-GaN層2之間, 係層積有緩衝層21及未摻雜GaN層22,此等之緩衝層21 及未摻雜GaN層22係爲爲了緩和基板1與η-GaN層2的晶 格偏移之構成,而緩衝層21及未摻雜GaN層22之厚度係 各自作爲0.05 μιη、2.0 μπι程度。 活性層3係具有多重量子井(MQW)構造’而在活性層3 之中,電子與正孔則進行再結合而發光光線之同時,進行 其光線的放大,此時的電子係從η側電極5所供給’而正 -8 - 200818550 孔係從P側電極所供給,活性層3係交互層積複數之 InGaN層與複數之GaN層,而各InGaN層係較n-GaN層 ’帶隙爲小,並作爲針對在活性層3之井層而發揮機能, 另外,上述各GaN層係爲在活性層3之阻障層,而構成活 性層3之InGaN層的數量及GaN層的數量係例如爲3〜7的 範圍,另外,活性層3的厚度係例如爲0.1 μιη程度。 p-GaN層4係爲摻雜Mg於GaN的層,而p-GaN層4的 厚度係例如爲〇. 1 W程度。 η側電極5係形成於n-GaN層2上,η側電極5係爲朝 向活性層3,爲了供給電子的構成,並作爲由A1層(第i層 )51及Ni層(第2層)52而成之層積構造,A1層51係接觸於 η-GaN層2,其厚度係作爲4000A程度,Ni層52係形成於 A1層51上,其厚度係作爲5000A程度,然而,亦可取代 Ni層52,將2層作爲由w、Zr或Pt而成之構成。 P側電極6係形成於p-GaN層4上,而p側電極6係爲 朝向活性層3,爲了供給正孔的構成,並由Au層(第i層 )61及Ni層(第2層)62而成,Au層61係接觸於p-GaN層4 上’其厚度係作爲400 0A程度,而Ni層62係形成於Au層 61上,其厚度係作爲5 00A程度,而理想爲Ni層62係作爲 被覆Au層61之上面全體的構成,然而,亦可取代Ni層 62 ’將2層作爲由w、Zr或Pt而成之構成,針對在本發 明係η側電極5的第2層與p側電極6的第2層係理想爲作爲 同一材質者。 絕緣層7係例如有si〇2而成,並被覆n_GaN層2及ρ_ 200818550
GaN層4 ’對於絕緣層7係形成有2個開口 7a,而對於各開 口 7a內係設置有上述η側電極5或p側電極6,並各電極 之上面則部分地,從絕緣層7露出。 配線8係因爲爲使半導體發光元件a與鄰接與此之其 他的半導體發光元件導通,使圖外之端子與半導體發光元 件A之構成,而配線8係Ni層(第1層)81及Au層(第2層 )8 2而成,而Ni層81係與n側電極5之Ni層52,或p側電 極6之Ni層62接觸,並作爲與Ni層52,62相同材料,An 層82係形成於Ni層8 1上,Ni層8 1及Au層82之厚度係各 自作爲5 00A程度及8 000A程度,而配線8之第1層的材質 係理想爲作爲與接觸於該配線之p側電極5或η側電極6之 第2層的材質相同之情況。 接著,關於半導體發光元件Α之製造方法的一例, 參照圖2〜圖5的同時,於已下進行說明。 首先,如圖2所示,於基板1上,層積緩衝層2 1、未摻 雜GaN層22、η-GaN層2、活性層3、以及p-GaN層4,而 此等層之形成係例如經由有機金屬氣相成長法(MOCVD)。 接著,如圖3所示,形成η側電極5及p側電極6,具 體而言,例如使用蒸鍍法及剝離法之手法,形成Α1層5 1 、Au層61、及Ni層52,53,此時,將Α1層51、Au層61 之厚度作爲4000A程度,將Ni層52,53之厚度作爲500A 程度。
接著,如圖4所示,呈被覆η-GaN層2、p-GaN層4、η 側電極5、以及ρ側電極地,形成絕緣層7 A,而絕緣層7 A -10- 200818550 之形成係例如,經由使用Si 〇2之蒸鍍法而進行。 接著,對於絕緣層7A而言,例如經由藉由根據微縮 術之手法而形成之光罩(略圖示),施以蝕刻之情況,形成 圖5所示之2個開口 7a,其蝕刻係爲例如離子蝕刻,並作爲 蝕刻氣體,在以流量40 Sccm(相當針對在特定之標準狀態 的1分鐘之體積流量(cc = cm3))供給CF4,將壓力作爲3.0 Pa 程度之狀態,經由將高頻率電力作爲1 00 W程度之條件而 進行,而2個開口 7a係爲使η側電極5之Ni層52及p側電 極6之Ni層62露出之構成,由此,得到絕緣層7。 之後,經由例如使用蒸鍍法及剝離法之手法,形成使 厚度爲50 0A程度Ni層81與厚度爲800 0A程度之Au層82 層積之配線8情況,得到半導體發光元件A。 接著,關於半導體發光元件A之作用,進行說明。 圖6係表示關於半導體發光元件A與比較例1,2,測 定順方向電壓Vf與順方向電流If之結果,針對在同圖, 圖表GA係爲半導體發光元件A之測定結果,圖表Gx, GY係爲各比較例1,2的測定結果,比較例1係爲與圖1 0所 示之半導體發光元件X相同的構成,比較例2係爲基本上 與比較例1 (半導體發光元件X)相同的構成,但,設置中 繼電極於各開口 1 〇7a內之情況則爲不同,而個中繼電極 係爲2層構造,由Ni製之下層及Au製之上層而成,下層 係接觸於半導體發光元件X的層102或層104,上層係爲 接觸於配線1 〇 8之構成。 首先,比較圖表Ga(半導體發光元件A)與圖表Gx(比 -11 - 200818550 較例1),例如,針對在工業上的使用,對於可作爲適當的 發光情況,爲了得到成爲目標之1.0* w5a程度之順方向 電流If,係有必要針對在比較例1,將順方向電壓Vf作爲 12V程度者,對此,如根據本發明,如將順方向電壓Vf 作爲7V程度,則足夠,即,如根據本發明,可較比較例 ,使驅動電壓下降,此理由係可認爲如以下所述,針對在 比較例1,如圖1 〇所示,對於η - G aN層1 0 2及p - G aN層而 言,直接接核配線1 〇8,而對於形成圍住其接合部分之開 口 107a,一般,對於絕緣層107而言,施以蝕刻,此時, n-GaN層102及p-GaN層104之表面,經由鈾刻而成爲損傷 ,而當於其被損傷的面,形成配線108時,針對在n-GaN 層102及ρ-GaN層104與配線108之界面的電組則增大,而 成爲需要大的驅動電壓,另一方面,如根據本發明,如圖 5所示,n-GaN層2及p-GaN層4則無曝露於蝕刻,另外, 曝露於鈾刻之Ni層52,62係比較而言,蝕刻速度爲慢, 不液晶由蝕刻而損傷,隨之,半導體發光元件A之驅動 電壓係變低。 接著,比較圖表GA(半導體發光元件A)與圖表Gx(比 較例2 ),針對在比較例2係即使爲順方向電壓V f爲1 . 0 V以 下之比較低電壓之狀態,順方向電流If則流動1.0 * 1 〇·7 A程 度,而其電流係爲所謂的洩漏電流,並經由發明著的硏究 ,了解到對於在活性層1 03 (參照圖1 〇)之發光係幾乎無貢 獻,產生如此之洩漏電流的理由係可認爲如以下所述,如 上述,針對在比較例2,係於各開口 1 〇 7 a內設置中繼電極 -12- 200818550 ,並其上層則作爲Au製,但Au係針對在6 0 0 °C程度之溫 度,對於絕緣層107擴散,其結果,絕緣層107之一部分則 作爲導電化,使洩漏電流產生,對此,針對在半導體發光 元件A係如圖1所示,η側電極5及p側電極6之中,與絕 緣層7接觸的幾乎部分係爲Ni層52,62,而Ni係對於由 Si02等而成之絕緣層7而言,不易擴散,隨之,可迴避絕 緣層7作爲不當導體化之情況,而可控制洩漏電流者。 圖7係表示針對在半導體發光元件A,進行複數次對 於順方向電壓Vf之順方向電流If的測定(Vf-If特性的測 定)之結果,具體而言,以固定對於η側電極5及p側電極 6之計測檢測的位置狀態,使順方向電壓Vf變化的同時, 測定順方向電流If(第1次測定),接著,使計測檢測的位 置作爲不同,測定相同的測定(第2次測定),之後,更加 地,使計測檢測的位置作爲不同,測定相同的測定(第3次 測定),如同圖所示,對於3個Vf-If特性測定結果係幾乎 無不均,另一方面,圖8係針對在比較例2,進行同樣的測 定之結果,而針對在比較例2係當變更計測檢測的位置時 ,Vf-If特性則產生大的變化,而其不同係針對在半導體 發光元件A係因Ni層52,62並無經由時刻而損傷,故可 認爲P側電極5及η側電極6之全面則經由全體爲平滑者。 η側電極5及ρ側電極6與配線8之接合係經由Ni層5 2 ,62與Ni層81之接合所實現,如此相同材質之同爲構件 的接合係比較於同爲異種金屬之接合而適合於使接合部的 電阻下降之情況,進而,對於使半導體發光元件A之驅 13- 200818550 動電壓下降之情況爲有利。 η側電極5之A1層51係容易形成與n-GaN層2有電組 的接觸,另外,P側電極6之Au層6 1係容易形成與p-GaN 層4有電組的接觸’此等係對於使半導體發光元件a之驅 動電壓下降之情況爲有利。 圖9係表示使用半導體發光元件A之發光裝置的一例 ,針對在本裝置係配置複數之半導體發光元件A爲矩陣 狀,然而,針對在同圖係省略圖1所示之基板1及絕緣層7 ,而配置成矩陣狀之複數的半導體發光元件A之中同爲 鄰接之構成係經由配線1 08所連接,而針對在本裝置係某 個半導體發光元件A之n側電極5則與鄰接之半導體發光 元件Α之ρ側電極6連接,由此,此等半導體發光元件a 係作爲相互串聯連接,如根據如此之發光裝置,可作爲面 發光的同時’可謀求驅動電壓的下降,和洩漏電流之控制 者。 【圖式簡單說明】 [圖1]係爲表示依據本發明之半導體發光元件的一例 之要部剖面圖。 [圖2]係爲表示上述半導體發光元件之製造工程的一 工程之剖面圖’並表示於基板上,使半導體層積之狀態。 [圖3]係爲表示上述製造方法之其他的一工程之剖面 圖,並表示形成有η側電極及p側電極之狀態。 [圖4]係爲表示上述製造方法之其他的一工程之剖面 -14- 200818550 圖,並表示形成有絕緣層之狀態。 [圖5]係爲表示上述製造方法之其他的一工程之剖面 圖,並表示於絕緣層施以鈾刻的樣子。 [圖6]係爲表不圖1所不之半導體發光元件與比較例1 ,2之順方向電壓-電流特性之圖表。 [圖7]係爲表示圖1所示之半導體發光元件之順方向電 壓-電流特性之圖表。 [圖8 ]係爲表示比較例2之順方向電壓-電流特性之圖 表。 [圖9]係爲表示使用圖1所示之半導體發光元件之發光 裝置的一例之要部平面圖。 [圖1 0 ]係爲表示以往之半導體發光元件的一例之要部 剖面圖。 接著,參照圖1〜圖1 6,說明本發明之實施型態。 【主要元件符號說明】 2 ·· n-GaN 層 3 :活性層 4,1 04 : p-GaN 層 5 : η側電極 6 : Ρ側電極 7,7 A,1 〇 7 :絕緣層 7 狂,1 0 7 a :開口 8,1〇8 :配線 -15- 200818550 21 : 22 : 5 1, 82 : 52, A, 緩衝層 未摻雜 81 : A1 Au層 62 : Ni X :半導
GaN層 層 層 體發光元件 -16-
Claims (1)
- 200818550 十、申請專利範圍 1· 一種半導體發光元件,屬於具備η型半導體層及P 型半導體層、 和挾於上述η型半導體層及上述Ρ型半導體層之活性層、 和接觸上述η型半導體層之η側電極、 和接觸上述ρ型半導體層之Ρ側電極、 被覆上述η型半導體層及上述Ρ型半導體層,且露出 上述η側電極及上述ρ側電極之各一部分的絕緣層、 的半導體發光元件,其特徵乃 上述η側電極乃:由Α1所成且與上述η型半導體層 接觸之第1層、和形成於此第1層上,且由Ni、W、Zr及 Pt之任一者所成第2層所構成, 上述P側電極乃:由Au所成且與上述ρ型半導體層 接觸之第1層、和形成於此第1層上,且由Ni、W、Zr及 Pt之任一者所成第2層所構成。 2 ·如申請專利範圍第1項之半導體發光元件,其中, 在更具備接觸於上述η側電極之配線的構成中,此配線乃 包含第1層與形成於此第1層上的第2層,上述配線之上述 第1層乃接觸於上述η側電極之上述第2層的同時,由與上 述η側電極之上述第2層相同的材質所成,上述配線之上 述第2層乃由Au所成者。 3 ·如申請專利範圍第1項之半導體發光元件,其中, 在更具備接觸於上述ρ側電極之配線的構成中,此配線乃 包含第1層與形成於此第1層上的第2層,上述配線之上述 -17· 200818550 第1層乃接觸於上述p側電極之上述第2層的同時,由與上 述P側電極之上述第2層相同的材質所成,上述配線之上 述第2層乃由Au所成者。 4. 一種半導體發光元件之製造方法,屬於具備η型半 導體層、和ρ型半導體層、和挾於此等η型半導體層及ρ 型半導體層的活性層的半導體發光元件之製造方法,其特 徵乃 包含形成接觸上述η型半導體層之η側電極、 形成接觸上述ρ型半導體層之ρ側電極、 形成被覆上述η型半導體層、上述ρ型半導體層、上 述η側電極及上述ρ側電極的絕緣層、 對於上述絕緣層,經由施以蝕刻,露出上述η側電極 及上述Ρ側電極之一部分的各工程; 上述η側電極之形成乃經由在於上述η型半導體層上 形成Α1所成第1層、更且於此第1層上,形成Ni、W、 Zr及Pt之任一者所成第2層而進行,上述ρ側電極之形 成乃經由在於上述P型半導體層上形成Au所成第1層、 更且於此第1層上,形成Ni、W、Zr及Pt之任一者所成 第2層而進行者。 -18-
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006184331A JP5008911B2 (ja) | 2006-07-04 | 2006-07-04 | 半導体発光素子およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200818550A true TW200818550A (en) | 2008-04-16 |
TWI350013B TWI350013B (zh) | 2011-10-01 |
Family
ID=38894513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096124370A TW200818550A (en) | 2006-07-04 | 2007-07-04 | Semiconductor light emitting element and method for manufacturing the same |
Country Status (6)
Country | Link |
---|---|
US (1) | US8101963B2 (zh) |
JP (1) | JP5008911B2 (zh) |
KR (1) | KR100984433B1 (zh) |
CN (1) | CN101479861B (zh) |
TW (1) | TW200818550A (zh) |
WO (1) | WO2008004545A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101894895A (zh) * | 2009-05-21 | 2010-11-24 | Lg伊诺特有限公司 | 发光器件以及具有该发光器件的发光器件封装 |
TWI462282B (zh) * | 2008-09-11 | 2014-11-21 | Toshiba Kk | 半導體光源及其製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010040894A (ja) * | 2008-08-07 | 2010-02-18 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
KR20100076083A (ko) | 2008-12-17 | 2010-07-06 | 서울반도체 주식회사 | 복수개의 발광셀들을 갖는 발광 다이오드 및 그것을 제조하는 방법 |
KR101456270B1 (ko) | 2010-03-23 | 2014-11-12 | 서울반도체 주식회사 | 복수개의 발광셀들을 갖는 발광 다이오드 및 그것을 제조하는 방법 |
US9318530B2 (en) * | 2012-08-07 | 2016-04-19 | Seoul Viosys Co., Ltd. | Wafer level light-emitting diode array and method for manufacturing same |
KR101601073B1 (ko) * | 2014-09-22 | 2016-03-15 | 서울반도체 주식회사 | 복수개의 발광셀들을 갖는 발광 다이오드 및 그것을 제조하는 방법 |
KR101761856B1 (ko) * | 2016-03-02 | 2017-07-26 | 서울반도체 주식회사 | 복수개의 발광셀들을 갖는 발광 다이오드 및 그것을 제조하는 방법 |
DE102019114315A1 (de) * | 2019-05-28 | 2020-12-03 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Anordnung und verfahren zur herstellung einer anordnung |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3722426B2 (ja) | 1994-09-19 | 2005-11-30 | 株式会社東芝 | 化合物半導体装置 |
JPH0955536A (ja) * | 1995-08-11 | 1997-02-25 | Sharp Corp | Iii族窒化物系化合物半導体発光素子およびその製造方法 |
JP3269344B2 (ja) * | 1995-08-21 | 2002-03-25 | 松下電器産業株式会社 | 結晶成長方法および半導体発光素子 |
JPH0969668A (ja) * | 1995-08-31 | 1997-03-11 | Toshiba Corp | 半導体発光装置とこれを製造するための高圧原料容器及び半導体発光装置の製造方法 |
JP3292044B2 (ja) * | 1996-05-31 | 2002-06-17 | 豊田合成株式会社 | p伝導形3族窒化物半導体の電極パッド及びそれを有した素子及び素子の製造方法 |
JP3625377B2 (ja) * | 1998-05-25 | 2005-03-02 | ローム株式会社 | 半導体発光素子 |
JP4003296B2 (ja) * | 1998-06-22 | 2007-11-07 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
JP2000332290A (ja) | 1999-05-20 | 2000-11-30 | Matsushita Electric Ind Co Ltd | 窒化物半導体素子およびその製造方法 |
JP3511372B2 (ja) * | 1999-08-31 | 2004-03-29 | シャープ株式会社 | 半導体発光素子およびそれを使用した表示装置 |
JP2001217456A (ja) * | 2000-02-03 | 2001-08-10 | Sharp Corp | 窒化ガリウム系化合物半導体発光素子 |
JP3864782B2 (ja) * | 2000-02-16 | 2007-01-10 | 日亜化学工業株式会社 | 窒化物半導体レーザ素子 |
KR100391373B1 (ko) | 2000-10-13 | 2003-07-16 | 광주과학기술원 | 반사막이 삽입된 p형 전극구조를 가지는 질화물계 발광다이오드 및 그 제조방법 |
JP4063520B2 (ja) * | 2000-11-30 | 2008-03-19 | 日本碍子株式会社 | 半導体発光素子 |
JP3872327B2 (ja) * | 2000-12-04 | 2007-01-24 | 日本碍子株式会社 | 半導体発光素子 |
JP4097601B2 (ja) * | 2001-10-26 | 2008-06-11 | アンモノ・スプウカ・ジ・オグラニチョノン・オドポヴィエドニアウノシツィオン | 窒化物半導体レーザ素子、及びその製造方法 |
JP2003243773A (ja) | 2003-03-04 | 2003-08-29 | Sony Corp | 半導体発光素子の製造方法および半導体発光素子 |
JP2005117020A (ja) * | 2003-09-16 | 2005-04-28 | Stanley Electric Co Ltd | 窒化ガリウム系化合物半導体素子とその製造方法 |
JP3833227B2 (ja) | 2003-11-04 | 2006-10-11 | 昭和電工株式会社 | III族窒化物p型半導体の製造方法およびIII族窒化物半導体発光素子 |
KR100822771B1 (ko) | 2003-12-10 | 2008-04-17 | 쇼와 덴코 가부시키가이샤 | 질화갈륨계 화합물 반도체 발광소자 및 그 음극 |
TWI229485B (en) * | 2004-04-06 | 2005-03-11 | Univ Nat Central | Semiconductor laser device structure and method of manufacturing the same |
JP4632690B2 (ja) * | 2004-05-11 | 2011-02-16 | スタンレー電気株式会社 | 半導体発光装置とその製造方法 |
TWI257721B (en) | 2004-05-26 | 2006-07-01 | Showa Denko Kk | Gallium nitride-based compound semiconductor light emitting device |
WO2005117150A1 (en) | 2004-05-26 | 2005-12-08 | Showa Denko K.K. | Gallium nitride-based compound semiconductor light emitting device |
KR100568502B1 (ko) * | 2004-08-11 | 2006-04-07 | 한국전자통신연구원 | 반도체 발광소자 |
KR100682870B1 (ko) | 2004-10-29 | 2007-02-15 | 삼성전기주식회사 | 다층전극 및 이를 구비하는 화합물 반도체 발광소자 |
US7221044B2 (en) * | 2005-01-21 | 2007-05-22 | Ac Led Lighting, L.L.C. | Heterogeneous integrated high voltage DC/AC light emitter |
JP4778745B2 (ja) * | 2005-07-27 | 2011-09-21 | パナソニック株式会社 | 半導体発光装置及びその製造方法 |
-
2006
- 2006-07-04 JP JP2006184331A patent/JP5008911B2/ja not_active Expired - Fee Related
-
2007
- 2007-07-03 CN CN2007800245191A patent/CN101479861B/zh not_active Expired - Fee Related
- 2007-07-03 US US12/307,193 patent/US8101963B2/en not_active Expired - Fee Related
- 2007-07-03 KR KR1020087031739A patent/KR100984433B1/ko active IP Right Grant
- 2007-07-03 WO PCT/JP2007/063291 patent/WO2008004545A1/ja active Application Filing
- 2007-07-04 TW TW096124370A patent/TW200818550A/zh not_active IP Right Cessation
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI462282B (zh) * | 2008-09-11 | 2014-11-21 | Toshiba Kk | 半導體光源及其製造方法 |
CN101894895A (zh) * | 2009-05-21 | 2010-11-24 | Lg伊诺特有限公司 | 发光器件以及具有该发光器件的发光器件封装 |
US8283692B2 (en) | 2009-05-21 | 2012-10-09 | Lg Innotek Co., Ltd. | Light emitting device and light emitting device package having the same |
CN101894895B (zh) * | 2009-05-21 | 2013-09-11 | Lg伊诺特有限公司 | 发光器件以及具有该发光器件的发光器件封装 |
US8648383B2 (en) | 2009-05-21 | 2014-02-11 | Lg Innotek Co., Ltd. | Light emitting device and light emitting device package having the same |
US9349919B2 (en) | 2009-05-21 | 2016-05-24 | Lg Innotek Co., Ltd. | Light emitting device and light emitting device package having the same |
Also Published As
Publication number | Publication date |
---|---|
TWI350013B (zh) | 2011-10-01 |
US20090256170A1 (en) | 2009-10-15 |
JP2008016537A (ja) | 2008-01-24 |
WO2008004545A1 (fr) | 2008-01-10 |
KR100984433B1 (ko) | 2010-09-30 |
KR20090015998A (ko) | 2009-02-12 |
CN101479861B (zh) | 2010-12-08 |
JP5008911B2 (ja) | 2012-08-22 |
CN101479861A (zh) | 2009-07-08 |
US8101963B2 (en) | 2012-01-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200818550A (en) | Semiconductor light emitting element and method for manufacturing the same | |
US9281439B2 (en) | Nitride semiconductor element and method for producing same | |
US8097532B2 (en) | Method for manufacturing a semiconductor light emitting device | |
JP3244010B2 (ja) | 周縁に電極を有する発光ダイオード | |
WO2006088046A1 (ja) | 半導体発光素子 | |
TWI397196B (zh) | 氮化物半導體發光元件之製造方法 | |
WO2015141517A1 (ja) | 半導体発光素子及びその製造方法 | |
KR20130120876A (ko) | 발광 다이오드 및 이의 제조방법 | |
TW200935626A (en) | Light emitting diode and method for manufactring the same | |
JP2008171997A (ja) | GaN系半導体発光素子 | |
JP2005354040A (ja) | 半導体発光素子およびその製法 | |
US20030047743A1 (en) | Semiconductor light emitting device | |
US20150280073A1 (en) | Semiconductor light-emitting element and production method therefor | |
TWI585993B (zh) | Nitride light emitting device and manufacturing method thereof | |
KR100593543B1 (ko) | 질화물 반도체 발광 소자 및 그 제조 방법 | |
JP5880633B2 (ja) | 半導体発光素子 | |
JP2006024913A (ja) | 窒化ガリウム系化合物半導体発光素子用透光性正極および発光素子 | |
JP6190591B2 (ja) | 半導体発光素子 | |
JPH10209498A (ja) | 半導体発光素子 | |
JP2016195187A (ja) | 半導体発光素子 | |
TW201515259A (zh) | 氮化物半導體發光元件及其製造方法 | |
JP2014116412A (ja) | 半導体発光素子 | |
JP2014107475A (ja) | 半導体発光素子 | |
JP6198396B2 (ja) | 半導体発光素子 | |
JP2015050381A (ja) | 半導体発光素子及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |