TW200818497A - Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same - Google Patents

Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same Download PDF

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Publication number
TW200818497A
TW200818497A TW096118175A TW96118175A TW200818497A TW 200818497 A TW200818497 A TW 200818497A TW 096118175 A TW096118175 A TW 096118175A TW 96118175 A TW96118175 A TW 96118175A TW 200818497 A TW200818497 A TW 200818497A
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Taiwan
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transistor
strain
channel
lining
semiconductor
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TW096118175A
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English (en)
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TWI365537B (en
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Tetsuji Ueno
Hwa-Sung Rhee
Ho Lee
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Samsung Electronics Co Ltd
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Publication of TWI365537B publication Critical patent/TWI365537B/zh

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

200818497 24459pif.doc 九、發明說明： 【發明所屬之技術領域】 本發明之實施例是關於一種半導體元件以及其製造方 法，且更特定言之，是關於一種具有改良閃爍雜訊二=之 半導體元件。 〈 【先前技術】 在當今之半導體製造過程中，元件大小正變得愈來侖 小。由於元件大小的減小，所以提升電子與電洞之遷移^ 之方法正持續發展。其中之一種方法包括誘發半導體元: 之通迢區域中產生應變。然而，經應變的類比金屬氧化半 導體(metal oxide semiconductor，MOS)電晶體傾向於展現 出惡化的閃爍雜訊特性。即使應變技術可能具有增強類比 MOS電晶體之互導與截止頻率特性之能力，其可能並=為 提升電子與電洞之遷移率的最有效方法。詳言之，在包括 提供完全整合之功能的數位以及類比M〇s電晶體之大型 積體電路（large-scale integrated circuit，LSI)的情況下， 將應變技術同時應用於數位MOS電晶體以及類比M〇s電 晶體可能並不適當。因此，存在對可藉由改良操作與雜訊 特性來達成綜效之半導體元件的需要。 【發明内容】 本發明之例示性實施例是針對一種半導體元件，其具 有基底、配置於基底上之類比NM0S電晶體（anal〇g NM〇s transistor)以及配置於基底上之擠壓應變通道類比pM〇s
電晶體（compressively_strained-channel analog PMOS 6 200818497 24459pif.doc transistor)。第一蝕刻終止 nmos電晶體且第二見令層（etchstopli腊,ESL)覆蓋 在500 Hz之頻率下，_=盖PM〇S電晶體，其中分別 訊功率與參考未應變通^ ^及·S電晶體之閃櫟雜 ，准訊功率相比的相對 0s… 【貫施方式】
現將參看附圖以充分P 明之較佳實關在®巾展示了本發 α ^ …、而本發明可具體化於許多不同形式， t應被看作限於本文中所提出之實施例。相反，提供此 傅達本發明之範疇至孰習士 字指代全文恤似組Γ 在圖式中，相似數 勺;^丄至圖5祝明半導體元件之示意圖，此半導體元件 比PMQS電㈣21帽2)以及應變或未 ^'交通_比NM0S電晶體侧、棚與測（圖3至 、:5)的各種組合。藉由射縫或拉伸應力施加至典型通 ^使得可改魏體（電子或電洞）之遷料_獲得應變 >這PMOS電晶體2100在5〇〇 Hz之頻率下的閃爍（1/f) 功卞（svg(v /Hz))與參考未應變通道類比pM〇s電 :體2GGG在相同頻率下之_雜訊功率相比的相對量測 、、去果小於1。類似地，NMOS電晶體3100、41⑻以及51⑻ 在500 Hz之頻率下的閃爍雜訊功率與參考未應變通道類 比NMOS電晶體1000在相同頻率下之閃爍雜訊功率相比 之相對量測結果亦小於i。因此，PM〇s電晶體21⑻以及 7 200818497 24459pif.doc NMOS電晶體3100、4100與5100之閃爍雜訊特性不小於 參考未應變通道類比PMOS電晶體2000以及參考未應變 通道類比NMOS電晶體1〇〇〇之閃爍雜訊特性。 芩考未應變通道類比NMOS電晶體1〇〇〇與參考未應 變通道類比PMOS電晶體2000具有與pm〇S電晶體2100 以及NMOS電晶體3100、4100與5100相同的設計規則且 由與PMOS電晶體2100以及NMOS電晶體3100、4100 f 與5100相同的材料形成。參考未應變通道類比NMOS電 1 晶體1000與參考未應變通道類比PMOS電晶體2000為具 有不誘發應變之通道的MOS電晶體。意即，圖丨中所示 之參考未應變通道類比MOS電晶體1 〇〇〇與參考未應變通 道類比PMOS電晶體2000誘發小於士 | 2 | Gdyne/pmJ之 應力或並不在通道中誘發任何應力。姓刻終止襯層 1152a與1152b可為中性蝕刻終止襯層（neutral ESL， NESL) ’其誘發小於土 I 2 I Gdyne/cm2之應力且可具有小 於lxl0“/cm」之氫濃度，且具體言之，具有小於lxl〇21/cm3 〇 之氫濃度。 應變通道類比NMOS電晶體3100 (圖3)、4100 (圖 4)與5100 (圖5)以及參考未應變通道類比電晶 體1000 (圖1)可包括半導體基底1〇〇、薄薄地形成於半 導體基底100中之淺溝渠隔離（shallow trench is〇lati〇n， ST1) 102、形成於由淺溝渠隔離1〇2界定之主動區域中之 η型源極/汲極區域128a以及形成於n型源極/汲極區域 128a之間的通道104a〇NM〇s電晶體更包括形成於通道 200818497 24459pif.doc l〇4a上之閘極12〇、插入於半導體基底1〇〇與閘極丨加之 間的閘極絕緣層110以及形成於閘極12〇之側壁上之間隙 壁123。金屬矽化物層13〇可分別形成於閘極12〇上及/或 η型源極/汲極區域12ga中。 ▲同樣，應變通道類比PM0S電晶體21〇〇以及參考未 應！通運類比PMOS電晶體2000可包括半導體基底1〇〇、 溥薄地形成於半導體基底HK)巾之淺溝渠隔離1Q2:形成 於由淺溝渠隔離1〇2界定之主動區域中之p型源極級極區 域128b以及形成於p型源極/汲極區域12肋之間的通道 lOlPMOS電晶體更包括形成於通道難上之間極 120插入於半.體基底！〇〇與間極12〇之間的閑極絕緣層 110以及形成於閘極12〇之侧壁上之間隙壁123。金屬石夕化 物層130可分別形成於閘極12〇上及/或p型源極/沒極區 域128b中。 NMOS電晶體310G、41G0與51GQ分別包括覆蓋各別 閘極120以及各別間_ 123且沿著半導體基底1〇〇之頂 表面延伸之第一蝕刻終止襯層152a、252a以及352a^M〇s 電晶體2100可包括覆蓋各別閘極12〇、間隙壁123且沿著 半導體基底1GG之頂表面延伸之第二*祕止襯層咖 或皿（圖2中所示）。隨著半導體元件之整合密度增加， 電晶，之間的距離顯著減小且相關聯的設計規則顯著減 少’藉此減小了相關聯的接觸區域。第—#刻終止概層 152a、252a與352a以及第二钱刻終止襯層152b與3汹 經形成’以便當形成接觸孔時防止爛邊緣在侧操作期 200818497 24459pif.doc 間被減小。PMOS電晶體2100以及NMOS電晶體31〇〇、 4100與5100是基於以下發現而設計的：1/f雜訊受到類比 NMOS電晶體中之ESL之氫濃度或類比PMOS電晶體中 之通道中誘發的擠壓應變之位準的相當大的影響，如圖6 至圖11中所示。 Ι/f雜訊功率svg主要受到界面狀態密度以及載體散射 之影響，如由等式（1)所識別： ^ ~^WLC …（1 ) 其中Svg指示雜訊功率，Nt指示界面狀態密度，//指 示遷移率，N指示载體密度，且α指示散射係數。圖6至 圖11中所示之實驗結果指示應力減小了雜訊功率；且界面 狀態密度之增加導致雜訊功率之增加。詳言之，圖6說明 使用電漿增強化學氣相沈積（plasma enhanced chemical vapor deposition，PECVD)方法形成之SiON層之應力量測 (/ 結果與氳濃度的曲線圖。具有lxl021/cmj之低氫濃度之中 性蝕刻終止襯層（NESL)以及具有lxl022/cm3之高氫濃度 之NESL皆展現出約2 Gdyne/cm2之應力。此與展現出約 -12 Gdyne/cm2之應力的具有lxl022/cm3之高氫濃度之擠壓 银刻終止襯層（compressive ESL，CESL)形成比較。 圖7說明包括具有低氫濃度之NESL之類比PMOS電 晶體（NESL(LH))的負偏壓溫度不穩定性（negative bias temperature instability, NBTI)量測結果、包括具有誘發通 10 200818497 24459pif.doc 道中之松壓應的南虱;)辰度之CESL之類比PMOS電晶體 (CESL(_)的NBTI量測結果、包括具有低氯濃度之 NESL以及填充基底中之凹槽且包括源極/汲極區域的磊晶 SiGe (epitaxial SiGe，eSiGe)層之類比 PM〇s 電晶體 eSiGe+NESL (LH)的ΝΒΊΊ量測結果之曲線圖。具有高 IU辰度之CESL誘發通道中之擦壓應變。產生圖7中說^ 之實驗結果的類比Ρ Μ〇S電晶體由同一材料形成且依據同 ζΛ 一設計規則。如自曲線圖可見，類比PMOS電晶體esiGe+ NESL (LH)展現出與類比PMOS電晶體NESL (LH)大 脰上相同的NBTI知性。另外，類比pm〇§電晶體cesL· (HH)展現出與類比:PMOS電晶體NESL (LH)不同的 NBTI特性。 圖8說明在500 Hz之頻率下的各種電晶體類型之雜訊 功率量測結果之間的曲線圖。詳言之，圖8展示包括具有 低氳濃度之NESL之類比PMOS電晶體NESL (LH)的雜 『 Λ功率虽測結果以及包括具有尚氫濃度之nesl之類比 PMOS電晶體NESL(HH)的雜訊功率量測結果。圖8亦 展不包括eSiGe層以及具有低氫濃度之NESL的類比 PMOS 電晶體 eSiGe+NESL (LH)以及包括 eSiGe 層以及 具有南氫濃度之NESL之類比pm〇S電晶體eSiGe+NESL (HH)的雜訊功率量測結果。此外，圖8展示包括具有低 氫滚度之CESL·的類比PMOS電晶體CESL (lh)以及包 括具有南氫濃度之CESL之類比pm〇S電晶體CESL(HH) 的雜訊功率量測結果。圖8亦提供包括eSiGe層以及具有 200818497 24459pif.doc 低氫濃度之CESL·的類比PMOS電晶體eSiGe+CESL(LH) 以及包括eSiGe層以及具有高氫濃度之CESL之類比 PMOS電晶體eSiGe+CESL (HH)的雜訊功率量測結果。 (基於圖7中說明之實驗結果）判定圖8中所提及之 類比PMOS電晶體eSiGe+NESL (LH)具有與類比PM〇s 電晶體NESL (LH)大體上相同的NBTI特性，但具有比 類比PMOS電晶體NESL (LH)低得多的雜訊功^位準。 由於eSiGe不包括氫，所以做出結論：由eSiGe誘發之擠 壓應變積極地影響PMOS電晶體之雜訊特性。意即，藉由 減小載體質量使得可減小散射係數，擠壓應變減小了 PMOS電晶體之雜訊功率。另外，假定類比pM〇s雷晶體 NESL (HH)與CESL (HH)之雜訊功率位準幾乎糾為 類比mos電晶體NESL (LH)與CESL (LH)之雜訊功 卞位準的兩倍⑥，可做出結論：由氫引㈣界面狀態密度 之增加導致雜訊功率之增加。假定類比p 二)具有比類比簡電晶體鹏L⑽‘良: t，可做出結論：擠壓應變可補償由氫引起的雜訊 pLos::匕且可稍改良雜訊特性。以此方式，即使類比 體之雜訊特性奸ESL之氫濃度㈣面影響，
帝曰誘發拚壓應變之適當的位準而防止類比PMOS 包日日to之雜訊特性受到進一步惡化。
| 9明圖8中說明之類比顺〇s電晶體‘順L (HHx , ‘eSlGe+NESL (LH)，、‘eSiGE+NESL 、CESL (LH)，、‘CESL (冊），、 12 200818497 24459pif.doc eSiGe+CESL (HH) ’ 與‘eSiGe+CESL (LH)，之雜 訊功率制絲對包括具有減濃度之NESL的參考類比 PMOS電晶體之軸功率量_果之相對量騎果之間的 關係之曲線圖。如在圖9中可見，與包括具有低氫濃度之 NESL的參考未應變通道類比pM〇s f晶體的雜訊功率相 比，具有擠壓應變通道之應變通道pM〇s電晶體之雜訊功 率^相對量測結果小於1，而與包括於應變通道PM0S電 晶體中之ESL的類型以及應變通道pM〇s電晶體之ES]L 的氫濃度無關。 圖10說明在500 Hz之頻率下的各種電晶體類型之雜 訊功率量測結果的曲線圖。詳言之，展示包括具有低氫濃 度之NESL的類比NMOS電晶體NESL(LH)的雜訊功率 量測結果以及包括具有高氫濃度之NESL之類比NMOS電 曰曰體NESL (HH)的雜訊功率量測結果。亦展示包括具有 低氳濃度之CESL的類比NMOS電晶體CESL (LH)以及 包括具有南氫濃度之CESL之類比NMOS電晶體CESL (HH)的雜訊功率量測結果。圖1〇中亦展示包括具有低 氫》辰度之拉伸姓刻終止襯層（tensile ESL，TESL)的類比 NMOS電晶體TESL(LH)以及包括具有高氫濃度之TESl 之類比NMOS電晶體TESL (HH)的雜訊功率量測結果。
類比 NMOS 電晶體 NESL (LH)、CESL (LH)以及 TESL
(LH)具有比類比NM〇S電晶體NESL(HH)、CESL(HH) 以及TESL (HH)改良的雜訊特性。然而，類比NM〇s電 晶體CESL(LH)以及CESL(HH)具有分別與類比NMOS 13 200818497 24459pif.doc =晶體NESL(LH)以及NESL(HH)幾乎相同的雜 。因此，可做出結論·舰NM〇s電晶體之雜訊功^ 到的ESL之氫濃度之影響比受到的擠壓應力之事二又 另外，假定類比NMOS電晶體TESL (Ui) 曰赘大。
NMas電晶體NESL (LH)務改良的雜訊特性，= 論：類比NMOS電晶體之雜訊特性可藉由誘發拉伸鹿= 得到改良。然而，假定，類比NM〇s電晶體tesl 之雜訊特性比類比NMOS電晶體NESL (LH)之雜^士 ^生 差，可做出結論：類比NM0S電晶體之雜訊功; ESL之氫濃度之影響比受到的拉伸應變之影響要大。 圖Π說明圖1〇 _說明之類比NM〇s電晶體nesl
(丽）、CESL (LH)、CESL (HH)、TESL (LH)與 TESL (I^H)之雜訊功率量測結果對包括具有低氳濃度之 的參考類比NMOS電晶體之雜訊功率量測結果之相對量 測結果之間的曲線圖。必須將ESL之氫濃度維持於相當低 (小於lxl〇21/cm3)，以便將類比NMOS電晶體之雜訊功 率與包括具有低氫濃度之NESL的參考類比NMOS電晶體 之雜訊功率之比值維持至小於1。因此，包括圖2之pM〇s 電晶體2100中之一者與圖3、圖4以及圖5之NMOS電 晶體3100、4100以及5100中之一者所組合之半導體元件 是基於圖6至圖11中說明之實驗結果的。藉由改良操作與 雜訊特性，期望此半導體元件達成綜效。 返回參看圖2,應變通道類比PMOS電晶體2100並不 受到第二蝕刻終止襯層152b與352b之氫濃度位準的影 14 200818497 24459pif.doc %。然而，應變通道類比PMOS電晶體2100可誘發其各 別通道中之捨壓應變以藉由改良操作與雜訊特性而達成综 效。詳言之，圖2之PMOS電晶體2100a為應變通道PMOS 電晶體，其包括並不誘發通道1〇4b中的擠壓應變之 NESL(第二蝕刻終止襯層152b)、填充半導體基底1〇〇中的 凹槽之擠壓磊晶半導體層124b (例如，siGe層）以及誘發 通迢104b中的擠壓應變之p型源極以及極區域128b。圖2 之PMOS電晶體2100b為應變通道pM〇s電晶體，其包括 誘發通道104b中的擠壓應變之CESL(第二蝕刻終止襯層 〕52b)。圖2之PMOS電晶體2100c為應變通道pm〇S電 晶體’其包括CESL(第二蝕刻終止襯層352b)以及與 CESL(第二蝕刻終止襯層352b)—起誘發通道1〇4中的擠壓. 應變之擠壓磊晶半導體層124b。 返回參看圖3至圖5以及NMOS電晶體3100、4100 與5100 ’將第一蝕刻終止襯層152a、252&與乃％之氫濃 度維彳寸於低濃度’例如小於lxl〇22/cm3，且具體言之，小 於IxlCH/cnr5。無論第一蝕刻終止襯層152a、252a與352a 疋否誘發各別對應的通道中之應變，皆維持上述之氫濃 度。當將此等參數連同PMOS電晶體2100、NMOS電晶 體3100、4100與5100 —起施加至半導體元件之製造時， 藉由改良操作與雜訊特性可達成綜效。 圖3中所示之NMOS電晶體3100a、3100b以及31〇〇c 白包括具有低氫濃度之NESL(第一钱刻終止襯層152a)。 更具體言之，NMOS電晶體31〇〇a為包括NESL(第一蝕刻 200818497 24459pif.doc 終止襯層152a)之未應變通道^^⑽電晶體，NM〇S電晶 體3100b為應變通道NMOS電晶體，其包括填充半導體基 底100中之凹槽、η型源極/汲極區域128a且誘發通道1〇= 中之拉伸應變的拉伸磊晶半導體層124a(例如，Sic層）。 NMOS電晶體31〇〇c為應變通道NMOS電晶體，其包括誘 發通道104a中之拉伸應變的播壓應變間極(c〇零㈤吻 strained gate，CSG)120，。包括拉伸磊晶半導體層124&與 【 拚壓應變閘極丨20’之應變通道NMOS電晶體（未圖示） 可得自NMOS電晶體3100b與3100c之不同特徵的組合， 且處於本發明之範奮内。 圖4中所示iNM0S電晶體41〇〇a、41〇〇b以及4i〇〇c 白匕治具有低氲，辰度之TESL(第一钱刻終止襯層252a)。更 具脰3之’ NMOS電晶體4100a為應變通道nm〇S電晶 體，其包括誘發通道l〇4a中之拉伸應變的丁ESL(第一蝕刻 終止襯層252a)。NMOS電晶體4100b為應變通道NM〇S 電晶體，其包括TESL(第一蝕刻終止襯層252a)、填充半導 G 體基底100中之凹槽、n型源極/汲極區域128a且與 TESL(第一蝕刻終止襯層252a)一起誘發通道⑺乜中之拉 變的拉伸磊晶半導體層124a(例如，Sic層>ΝΜ〇§ 電晶體4100c為應變通道NM〇s電晶體，其包括tesl(第 —钱刻終止襯層252a)以及連同TESL(第—侧終止觀層 252句一起誘發通道1〇4a中之拉伸應變的擠壓應變閘^ 120 。包括TESL(第一蝕刻終止襯層252a)、拉伸磊晶半 導體層124a與擠壓應變閘極12〇,之應變通道NM〇『電 16 200818497 24459pif.doc 晶體（未圖示）可得自NMOS電晶體41〇〇b與41〇〇c之不 同特徵的組合，且被考慮為處於本發明之範脅内。 圖5中所示之NMOS電晶體51〇〇a、51〇〇b以及5100c 皆包括具有低氫濃度之CESL(第一钱刻終止襯層352a)。 更具體言之，NMOS電晶體5l〇0a為應變通道NM〇s電晶 體，其包括誘發通道104a中之擠壓應變的CESL(第一蝕刻 終止襯層352a)。NMOS電晶體5100b為應變通道NM〇S 電晶體，其包括CESL(第一蝕刻終止襯層352a)、填充半 導體基底1〇〇中之凹槽的拉伸磊晶半導體層124a (例如， sic層）以及連同CESL 352a 一起誘發通道1〇如中之擠壓 應變的η型源極/汲極區域128a。NM〇s電晶體5i〇〇c為 應變通道NMOS電晶體，其包括_侧終止觀層 3S2a)以及連㈤CESL(第一钱刻終止襯層352&)一起誘發捽 麵變之觀應變· 12〇,。包括CESL(第—侧 襯層灿)、拉伸蟲晶半導體層咖與擠堡應變間極12〇， 之應變通道NMOS電晶體（未圖示）可得自ΝΜ〇§電晶 體^㈣與5職之不_徵的組合，且被考 發明之範疇内。 十 路以之實施例的半導體元件為藉由將數位電 路安裝於單一晶片上以提供單-完整系統的 目的:錢之錢LSI元件，則半導體元件可包括類 路區域以及触電路區域。以此方式，類可5 括圖2中所示之PM〇s電晶體21〇〇 M ^ 晶體删、圖k_S電晶體二 200818497 24459pif.doc 電晶體5100。根據系統LSI所需的效能之位準，數位電路 區域可包括應變或未應變通道數位NM〇s電晶體及應 變或未應變通道數位PMOS電晶體。 ^ 本文中參看圖12A至圖12E描述一種製造圖2中說明 之PMOS電晶體2100c以及圖4中說明之NM〇s電晶體 4100b的方法。參看圖12A，淺溝渠隔離1〇2形成於半導 體基底100 (例如，矽基底）之數位以及類比電路區域中。 ( 使用用於待形成於每一區域中之電晶體之類型的適當離 子，對半導體基底100執行通道離子植入。絕緣層與導體 層接著形成於半導體基底100上且經谓案化為閘極絕緣層 110以及閘極120。其後，形成界定通道1〇乜與1〇4b之源 杈/汲極延伸區域122。絕緣的間隙壁123形成於每一閘極 120的側壁上。 芩看圖12B，填充有分別誘發通道1〇4a與1〇4b中之 應變的拉伸磊晶半導體層124a與擠壓磊晶半導體層124b 之凹槽G是藉由部分蝕刻半導體基底1〇〇而形成。在凹槽 ϋ g之形成期間，可部分蝕刻閘極12〇。 一 茶看圖12C，形成拉伸磊晶半導體層124a與擠壓磊晶 半導體層124b，使得各凹槽G中可填充有拉伸磊晶半導體 層124a與播壓磊晶半導體層124b中之一者。誘發通道 l〇4a中之拉伸應變之Sic：層可形成於NM〇s區域中。誘 發通逼104b中之擠壓應變之以^層可形成於爾〇8區域 中使用每擇性轰晶生長（selective epitaxial growth，SEG ) 方去例如’低壓化學氣相沈積（low pressure chemical 18 200818497 24459pif.doc vapor deposition，LPCVD)方法或超高真空化學氣相沈積 (ultra-high vacuum chemical vapor deposition, UHC CVD ) 方法’可形成拉伸蠢晶半導體層124a與播壓蟲晶半導體層 124b。在拉伸磊晶半導體層124a與擠壓蟲晶半導體層i24b 之形成期間，可使用用以形成深源極/汲極區域126之摻質 而執行現場(in-situ)摻雜操作。舉例而言，使用、 S1H4、81¾¾、SiHCls 或 SiCU 作為 Si 源，GeH4 作為 Ge 源且（^2¾或CHsSiH3作為C源，可形成拉伸蟲晶半導體 層124a與擠壓磊晶丰導體層i24b。為了增強拉伸磊晶半 導體層124a與擠壓磊晶半導體層124b之選擇特性，可將 HC1成CL氣體添加至氣體源。亦可將^退6、或八姐， 氣體添加至氣體源以摻雜拉伸磊晶半導體層12知與擠壓 蟲晶半導體層124b。藉由添加HC1氣體，可能僅在使用 SEG方法暴露Si之區域巾選擇性地形成蟲晶半導體屏 124a與l24b，同時防止拉伸蠢晶半導體層ma與擠單: 晶半導體層124b在淺溝渠隔離1〇2中生長。、土猫 在形成拉伸磊晶半導體層124a與擠壓磊晶半導體厣 124b後，形成深源極/沒極區域126。如此一來，^刑曰 極區域施以及p _極/汲極區域128b之^極 右在形成拉伸蟲晶半導體層124a與擠壓县晶半導體岸 ⑽之层晶生長操作_執行摻雜操作 ^ 極/獅細。其後，使用侧_呈，金屬石=
:成於閘極120上以及n型源極/汲極區物a / 型源極/汲極區域128b上。 一 P 19 200818497 24459pif.doc 展w看^121) $成拉伸應變概層252以及擠壓應變襯 見層252覆蓋NM0S電晶體且擠壓應變 ，PM〇S電晶體。拉伸應變_
可由不同材料形成或可由相同材料形成，但 如此項技射所熟知處於列處理條件下。 〇N ===變襯層252，則拉伸應變概層拉之氮濃度 :二卢Cm如圖13中所說明。杈伸應變襯層252 之虱辰度可鬲於擠壓應變襯層352之气 比NMOS電晶體之閃焊雜气々卜4 二、又。為了改良頒 照射達約1至1。分 層252的氫濃度。作為uv , 低拉伸應變襯 變槻層352之氫濃度。藉由利用身圖亦可降低擠壓應 固12A至圖12D中臂明之 方法，可㈣圖12E中說明的具有擁 閃 雜訊特性之麵S以及PMC)S =2、叫 至圖：=電方^
G NMOS以及PMOS電晶體成内連線，使得可自 半導體基纟丨⑻電信號，以及包括在 (packaging sub她）。可使用;相關聯的封裝基板 述之方法而製造半導體元件，其中;⑽描 與播壓遙晶半導體層124b之mi:日日半導體層124a 由在NMOS以及PMOS電晶體上叫另外;藉 發特性之第一與第二ESL· (如以上^ 有所要的應變誘 述），可製造類比電晶體之各種組合*目2至圖5所描 200818497 24459pif.doc 圖14說明解釋形成誘發NMOS電晶體之通道104a中 的拉伸應變之播壓應變閘極120’之方法的截面圖。n型源 極/没極區域128a與p型源極/没極區域128b形成於半導 體基底 100 中，且閘極轉換層（gate transformation layer) 124 形成於半導體基底100之整個表面上。對半導體基底1QQ 執行回火(annealing)，使得將擠壓應變施加至由多晶石夕形 成之閘極120。結果，具有經轉換的上部分之擠壓應變閘 極120’形成於NMOS區域中。閘極轉換層124之類型以 及擠壓應變閘極120’之形成揭露於κ· Ota等人之“Novel Locally Strained Channel Technique for High Performance 55nm CMOS”（International Electron Devices Meeting， 2·2·1 ’ IEEE ’ 2002 年 2 月）以及 Chien-Hao Chen 等人之 "Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance
Strained-Si Device Application”（ VLSI Technology，2004 ) 中，其揭露内容以引用的方式併入本文中。在形成播壓應 G 變閘極丨2〇後，移除閘極轉換層124，且執行以上參看圖 12B至圖12D描述之製程以完成半導體元件之製造。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1說明用以評估根據本發明之實施例的類比M〇s 21 200818497 24459pif.doc 電晶體之雜訊功率特性 體的截面圖。 之參考未應變通道類比MOS電 曰曰 Θ ^=根據本發明之實施例的半導體元件之擠壓應 電晶體之截面圖。 θ圖5"兄明根據本發明之實施例的半導體元件之 類比NMOS電晶體的戴面圖。 ° 兒月使用笔漿^習強化學氣相沈積（chemical vapor
Ο deposition，CVD)方法形成之si〇N層之應力量測結果與 氫濃度量觀果之__之曲關。 圖’一圖11王現用於判定影響閃爍雜訊之因素之實驗 數據。 圖12A至圖12E說明解釋製造半導體元件之方法的截 •圖13况明誘發擠壓應變si〇N層之氫濃度的紅外 (infrared，IR)!測結果與誘發拉伸應濃度 的汉量測結果之間的關係之曲線圖。 層 且古圖二：明用於解釋根據本發明之實施例的製造包括 【主要元件符號說明】 100 :半導體基底 102 ·淺溝渠隔離 作用造成拉伸應變之通道的nM〇s 凡件之丰¥體几件之方法的截面圖。 l〇4a ··通道 104b :通道 22 200818497 24459pif.doc 11Θ :閘極絕緣層 120 :閘極 12CT :擠壓應變閘極 122 :源極/汲極延伸區域 123 :間隙壁 124 :閘極轉換層 124a :拉伸磊晶半導體層
Ο 124b ··擠壓磊晶半導體層 126 ·深源極/>及極區域 128a : η型源極/汲極區域 128b ·· ρ型源極/沒極區域 130 :金屬石夕化物層 152a :第一蝕刻終止襯層 152b :第二蝕刻終止襯層 252 :拉伸應變襯層 252a :第一蝕刻終止襯層 352 :擠壓應變襯層 352a :第一钱刻終止觀層 352b ··第二蝕刻終止襯層 1000 :參考未應變通道類比NMOS電晶體 1152a :姓刻終止概層 1152b :蝕刻終止襯層 2000 :參考未應變通道類比PMOS電晶體
2100、2100a、2100b、2100c :應變通道類比 PMOS 23 200818497 24459pif.doc
電晶體 3100 、 3100a NMOS電晶體 4100 、 4100a NMOS電晶體 5100、5100a NMOS電晶體 G :凹槽 3100b、3100c :應變或未應變通道類比 4100b、4100c :應變或未應變通道气比 5100b 、:應變或未應變通道 类員比
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  1. 200818497 24459pif.doc 十、申請專利範圍： 1·一種半導體元件，包括： 基底； 配置於所述基底上之類比NMOS電晶體； 配置於所述基底上之擠壓應變通道類比PM〇s %曰 體； 、 免晶 覆盍所述NMOS電晶體之第一餘刻終止襯層；以及 覆蓋所電晶體之第二蝕刻終止襯層， 其中分別在500 Hz之頻率下，所以及所诚 PMOS電晶體之閃爍雜訊功率與參考未應變通道類= NMOS以及PMOS電晶體之閃爍雜訊功率相比的相對量_ 結果小於1。 2·如申請專利範圍第1項所述之半導體元件，其中所 述第一蝕刻終止襯層具有小於lxl021/cm3之氫濃度。 、一3·如申凊專利範圍第2項所述之半導體元件，其中所 t第钱刻、冬止襯層為中性姓刻終止襯層，所述元件更包 〇 括· 與所述PMOS電晶體相關聯之通道； 填充形成於所述基底中之凹槽之擠壓磊晶半導體層； 、以及形成於所述擠壓磊晶半導體層中之源極/汲極區 域’其中麵、壓應變於所述PMOS電晶體之所述通道中被誘 發。 、、^4」如申睛專利範圍第2項所述之半導體元件，其中所 ' 】、、、止概層為擠壓應變概層，且擒壓應力由所述 25 200818497 24459pif.doc 第二銳刻終止襯層誘發於所述 5.如申請專利範圍第4項 ，晶體之通道中。 述PMOS電晶體包括▲ 4 “導體元件，其 述基底中之凹ί 的播屋應變，並填充形ί， t二 包括形成於所述_石日ΐ於所 之源極/>及極區域。 土私日日半導體層中 6·如申轉利||圍第2 ί 述第一麵終止襯層為中性韻刻終上脰兀件，、其中所 電晶體為應變通道電晶體，其包括· ·’、^ ’且所逑N]\4〇s 以及具絲成於所述基底中之凹槽之拉伸羞晶半導體層； 拉伸磊晶半導體層中之源極/汲極區域; +、χπΓ 半導體層以及所述源極/¾極區域W 所述NMOS電晶體之通道中的拉伸應變。 U發 —7·如申請專利範圍第2項所述之半導體元件，其中 地弟綱終止襯層為中性钱刻終止襯層，且所述购W U 為應變逋道電晶體，其包括擠壓應變閘極，以誘發 所述nm〇s電晶體之所述通道中的拉伸應變。 又 、斤8·如申請專利範圍第2項所述之半導體元件，其中所 述第一蝕刻終止襯層為拉伸應變襯層，且所述1^1^[〇8電晶 膝為應又通道電晶體，其包括由所述拉伸應變襯層造成應 變之通道。 9·如申請專利範圍第8項所述之半導體元件，其中所 述NMOS電晶體更包括： 26 200818497 24459pif.doc 以及 填充形成麵縣射之凹槽之拉縣晶半導: :層 所導體層中之源極/汲極區域； 所一電晶;極/賴，聲 ί 、ΐ isTot t4專利範圍第8項所述之半導體元件，其中你 ΐ晶體之^^=間極，— ί應晶體，其包括由所述擠壓應變襯層造^ 申請翻翻第11項所述之半導體元件，里φ 和 QS電晶料輕通道電㈣，其包括：、 以及充形成於所述基底中之凹槽之拉躲晶半導體層； υ 开二成於所述拉伸i晶半導體層巾之源極/¾:極區域； f 34㈣羞晶半導體層以及所述 戶斤述NM0S電晶體之通道中的拉伸應變。 如申請專利範圍第u工頁所述之半導體元件，其中 户斤述M0S電晶體為應變通道電晶體，其包括 變 換，以誘發所述_沉電晶體之所述通道中的拉伸^閑 14· —種半導體元件，包括： 一 基底； 27 200818497 24459pif.doc 配置於所述基底上之類比NMOS電晶體； 配置於所述基底上之類比PMOS電晶體； 覆蓋所述NM0S電晶H 小於㈣2 W之氫濃度；以及 _其具有 、、弟一蝕釗終止襯層，其覆蓋所述電晶 所述PMOS電晶體之通道中的播壓應變。 § ί u 所社ϋΐί專姆圍第14顿狀料體元件，其中 w乐 釗終止襯層誘發所述ΝΜ〇 的拉伸應變。 电日日版之逋運中 、丄、16.如中請專利範圍第15項所述之半導體 所地p^os電晶體包括擯、壓蟲晶半導體層，其 α P:S電晶體之所述通道中的擦壓應 ^二= 述基底中之凹槽，且包括源極你極區域。"絲成於所 、丄、17.如申請專利範圍第項所述之半導體 所地NMOS甩晶體為應變通道電，其: 伸⑪半導體層，以及形== 拉伸现曰曰+ ¥體層中以誘發所述NMOS電晶體 之拉伸應變的源極/汲極區域。 之通逞中 18.如申請專_圍第16 所述NMOS電晶體為應變 件，其中 19-種半導體元件=之通迢中的拉伸應變。 基底； 第—餘刻終止襯層，其具有小於lxl〇2w之H 200818497 24459pif.doc 度；以及 應、艾通道類比NMOS電晶體，其配置於所述第一I虫刻 終止襯層與所述基底之間。 20.如申凊專利範圍第19項所述之半導體元件，其中 所述第一蝕刻終止襯層為中性蝕刻終止襯層，且所述 NMOS電晶體為應變通道電晶體，其包括： 填充形成於所述基底中之凹槽之拉 晶半導體層； 以及 开y成於所述拉伸磊晶半導體層中之源極以及極區域； …所返拉伸以半賴層以及所述源極/②極區域誘發 所述NM〇S|晶體之通道中的拉伸應變。 !^刻終止襯層為中性_終止襯層，且所述 以講&為應變迫道電晶體，其包括擠壓應變問極， HNM0S電晶體之通道中的拉伸應變。 u 晶體為應變通道+ :„應變襯層，且所述NM0S電 拉伸應變之通日日脰，其包括由所述拉伸應變襯層造成 所述圍第22項所述之半導體⑽，其中 填充开^曰曰脰為應變通道電晶體，其包括： 以及 、於所述基底中之凹槽之拉伸磊晶半導體層； 、；斤迷拉伸蟲晶半導體層中之源極/沒極區域； 200818497 24459pif.doc 所述拉伸磊晶半導 所述1^]\4〇8電3(^$、8 M 乂及所述源極/汲極區域誘發 %日日肢之逋道中的拉伸應變。 .所述NMOS 22項所述之半導體元件，其中 極，以誘發所』：〇s1f:電晶體，其包括擠壓應變閘 25如申电晶脰之通逞中的拉伸應變。 d第-二 _ 19項所叙半導體元件，且中 所l弟蝕刻終止襯層為擠壓岸變襯声，、 曰曰曰體為應變通道雷晶俨：士襯層且所述_電 擠歷應變之通道:、包括由所述擠屡應變襯層造成. 專利範㈣25項所述之铸體元件，盆中 戶斤μ體麵韻道電晶體，其包括： 填充形成於所述基底巾之凹槽之㈣^辭導體 以及 = 拉伸磊晶半導體層中之源極/汲極區域； 二0St=半導體層以及所述源極/没極區域誘發 戶斤述NMOS电曰曰體之通道中的拉伸應變。 ΛΐοΓ^ΐϋ範園第25項所述之半導體元件，其中 户，應變通道電晶體，其包括擠壓應變問 # ? 28 ° 28.種製斜導體元件之方法，包括. 在赫上形成·b NM0S ^體以及舰腹⑽電 形成具有小於1><1〇21/ 3 & 廣減蓋所述nM0S電晶體；^辰度的第一侧終止襯 30 200818497 24459pif.doc 概層以覆蓋所述PMOS電晶體，所 發所述PMOS電晶體之通道中的擠 29·如申請專利篇圍 方法，盆巾^= 28顿述之製料導體元件之 炊成終止襯層以及所述第二· 終止襯層更包括： 雕·先成拉伸應交則終止襯層以覆蓋所述NM〇s電晶
    I成知£應、交襯層以覆蓋所述刚〇§電晶體；以及 將紫外線照射至所述基底之整個表面上。 一。0.如申明專々!I祀圍第29項所述之製造半導體元件之 乃去’其中形輯述pM〇s電晶體更包括： 在所述基底中形成凹槽； 形成填充所述凹槽之擠壓蟲晶半導體層；以及 在所述擠壓“半導體層巾形錢極/¾極區域。 u 形成第二蝕刻終止 述第二I虫刻終止襯層誘 壓應變。 31.如申請專利範圍第3〇項所述之製造半導體元件之 方法，其中形成所述NMOS電晶體更包括： 在所述基底中形成凹槽； 形成填充所述凹槽之拉伸蟲晶半導體層；以及 在所述拉伸磊晶半導體層中形成源極/汲極區域。 32·如申請專利範圍第30項所述之製造半導體元件之 方法，其中形成所i^NMOSt晶體更包括形成包括擠壓庫、 變閘極之NMOS電晶體。
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US20080036006A1 (en) 2008-02-14
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US8445968B2 (en) 2013-05-21
US20110233611A1 (en) 2011-09-29
JP2007324589A (ja) 2007-12-13
KR100703986B1 (ko) 2007-04-09
TWI365537B (en) 2012-06-01
JP5367955B2 (ja) 2013-12-11
US20130249016A1 (en) 2013-09-26
US7952147B2 (en) 2011-05-31

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