TW200729206A - Method of controlling memory and memory system thereof - Google Patents

Method of controlling memory and memory system thereof

Info

Publication number
TW200729206A
TW200729206A TW095125069A TW95125069A TW200729206A TW 200729206 A TW200729206 A TW 200729206A TW 095125069 A TW095125069 A TW 095125069A TW 95125069 A TW95125069 A TW 95125069A TW 200729206 A TW200729206 A TW 200729206A
Authority
TW
Taiwan
Prior art keywords
address
write
latching
input
data
Prior art date
Application number
TW095125069A
Other languages
English (en)
Other versions
TWI410970B (zh
Inventor
Toshio Sunaga
Norio Fujita
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200729206A publication Critical patent/TW200729206A/zh
Application granted granted Critical
Publication of TWI410970B publication Critical patent/TWI410970B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2218—Late write

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW095125069A 2005-07-29 2006-07-10 控制記憶體的方法及記憶體系統 TWI410970B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005220445 2005-07-29

Publications (2)

Publication Number Publication Date
TW200729206A true TW200729206A (en) 2007-08-01
TWI410970B TWI410970B (zh) 2013-10-01

Family

ID=37683381

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125069A TWI410970B (zh) 2005-07-29 2006-07-10 控制記憶體的方法及記憶體系統

Country Status (7)

Country Link
US (1) US7843742B2 (zh)
EP (1) EP1912222A4 (zh)
JP (1) JP5043662B2 (zh)
KR (1) KR101027181B1 (zh)
CN (1) CN101233575A (zh)
TW (1) TWI410970B (zh)
WO (1) WO2007013491A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108121616A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 存储器电路、多端口存储器电路及其操作方法

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JP4234126B2 (ja) 2005-09-28 2009-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリ、メモリ・アクセス制御方法
KR100923821B1 (ko) * 2007-12-24 2009-10-27 주식회사 하이닉스반도체 불휘발성 메모리 장치의 페이지 버퍼 및 그 프로그램 방법
CN101677019B (zh) * 2008-09-18 2014-07-16 深圳市朗科科技股份有限公司 闪存的流水线读取方法及系统
CN102159622A (zh) 2008-09-23 2011-08-17 聂克斯姆化学有限公司 炔属聚酰胺
US8462561B2 (en) * 2011-08-03 2013-06-11 Hamilton Sundstrand Corporation System and method for interfacing burst mode devices and page mode devices
KR102401271B1 (ko) 2015-09-08 2022-05-24 삼성전자주식회사 메모리 시스템 및 그 동작 방법
KR102471529B1 (ko) * 2016-07-29 2022-11-28 에스케이하이닉스 주식회사 반도체 장치
JP7195913B2 (ja) 2018-12-19 2022-12-26 キオクシア株式会社 半導体記憶装置
CN109977049B (zh) * 2019-03-01 2020-06-23 京微齐力(深圳)科技有限公司 一种控制器及方法、系统
CN112447218A (zh) * 2019-08-29 2021-03-05 台湾积体电路制造股份有限公司 存储器电路和方法
DE102019128331A1 (de) 2019-08-29 2021-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Gemeinsam genutzter decodiererschaltkreis und verfahren

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JP3304577B2 (ja) * 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
JP3170146B2 (ja) * 1994-07-29 2001-05-28 株式会社東芝 半導体記憶装置
JPH10111828A (ja) 1996-09-27 1998-04-28 Internatl Business Mach Corp <Ibm> メモリシステム、データ転送方法
JP3123473B2 (ja) 1997-07-24 2001-01-09 日本電気株式会社 半導体記憶装置
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
JP2000163969A (ja) * 1998-09-16 2000-06-16 Fujitsu Ltd 半導体記憶装置
DE19951677B4 (de) * 1998-10-30 2006-04-13 Fujitsu Ltd., Kawasaki Halbleiterspeichervorrichtung
JP4817477B2 (ja) 1998-10-30 2011-11-16 富士通セミコンダクター株式会社 半導体記憶装置
JP2000163965A (ja) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3362775B2 (ja) * 1998-12-25 2003-01-07 インターナショナル・ビジネス・マシーンズ・コーポレーション Ｄｒａｍ及びｄｒａｍのデータ・アクセス方法
JP4439033B2 (ja) * 1999-04-16 2010-03-24 株式会社ルネサステクノロジ 半導体記憶装置
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JP4569915B2 (ja) 2000-08-11 2010-10-27 エルピーダメモリ株式会社 半導体記憶装置
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108121616A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 存储器电路、多端口存储器电路及其操作方法

Also Published As

Publication number Publication date
JP5043662B2 (ja) 2012-10-10
KR20080036049A (ko) 2008-04-24
EP1912222A4 (en) 2009-05-13
US20100061156A1 (en) 2010-03-11
CN101233575A (zh) 2008-07-30
EP1912222A1 (en) 2008-04-16
JPWO2007013491A1 (ja) 2009-02-12
KR101027181B1 (ko) 2011-04-06
TWI410970B (zh) 2013-10-01
US7843742B2 (en) 2010-11-30
WO2007013491A1 (ja) 2007-02-01

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