TW200721676A - Triplet value pulse generating circuit - Google Patents

Triplet value pulse generating circuit

Info

Publication number
TW200721676A
TW200721676A TW095139107A TW95139107A TW200721676A TW 200721676 A TW200721676 A TW 200721676A TW 095139107 A TW095139107 A TW 095139107A TW 95139107 A TW95139107 A TW 95139107A TW 200721676 A TW200721676 A TW 200721676A
Authority
TW
Taiwan
Prior art keywords
generating circuit
pulse generating
switching
value pulse
triplet value
Prior art date
Application number
TW095139107A
Other languages
English (en)
Chinese (zh)
Other versions
TWI329419B (enExample
Inventor
Takashi Tanimoto
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200721676A publication Critical patent/TW200721676A/zh
Application granted granted Critical
Publication of TWI329419B publication Critical patent/TWI329419B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
TW095139107A 2005-10-26 2006-10-24 Triplet value pulse generating circuit TW200721676A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005310899A JP2007124084A (ja) 2005-10-26 2005-10-26 ３値パルス発生回路

Publications (2)

Publication Number Publication Date
TW200721676A true TW200721676A (en) 2007-06-01
TWI329419B TWI329419B (enExample) 2010-08-21

Family

ID=37985386

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095139107A TW200721676A (en) 2005-10-26 2006-10-24 Triplet value pulse generating circuit

Country Status (5)

Country Link
US (1) US7521979B2 (enExample)
JP (1) JP2007124084A (enExample)
KR (1) KR100787326B1 (enExample)
CN (1) CN100512370C (enExample)
TW (1) TW200721676A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7672393B2 (en) * 2006-08-02 2010-03-02 Richtek Technology Corporation Single-wire asynchronous serial interface
CN101834595B (zh) * 2010-05-04 2012-10-24 宁波大学 一种单功率时钟钟控传输门三值绝热电路及t运算电路
JP6545213B2 (ja) * 2017-03-17 2019-07-17 アンリツ株式会社 ３値信号発生装置及び３値信号発生方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223916A (ja) 1982-06-23 1983-12-26 Nec Corp ３値レベルクロツク発生回路
JPS5985153A (ja) * 1982-11-08 1984-05-17 Hitachi Ltd 冗長化制御装置
JPH02125526A (ja) * 1988-11-04 1990-05-14 Nec Corp 三値論理出力回路
JP2789792B2 (ja) * 1990-06-25 1998-08-20 日本電気株式会社 パルス出力回路
JPH06232702A (ja) * 1991-05-10 1994-08-19 Nec Corp ３値レベルパルス発生回路
FR2709217B1 (fr) * 1993-08-19 1995-09-15 Bull Sa Procédé et dispositif d'adaptation d'impédance pour un émetteur et/ou récepteur, circuit intégré et système de transmission les mettant en Óoeuvre.
JPH0779155A (ja) * 1993-09-06 1995-03-20 Mitsubishi Electric Corp 信号選択装置
US5528168A (en) * 1995-03-29 1996-06-18 Intel Corporation Power saving terminated bus
JPH09205351A (ja) * 1996-01-25 1997-08-05 Sony Corp レベルシフト回路
US5731711A (en) * 1996-06-26 1998-03-24 Lucent Technologies Inc. Integrated circuit chip with adaptive input-output port
KR100207497B1 (ko) * 1996-08-30 1999-07-15 윤종용 반도체장치의 신호 발생회로
JP3867330B2 (ja) 1997-01-08 2007-01-10 ソニー株式会社 固体撮像装置とその製造方法
US5710563A (en) * 1997-01-09 1998-01-20 National Semiconductor Corporation Pipeline analog to digital converter architecture with reduced mismatch error
US6173424B1 (en) * 1997-12-31 2001-01-09 Micron Technology, Inc. Programmable pulse generator and method for using same
JP3595153B2 (ja) * 1998-03-03 2004-12-02 株式会社 日立ディスプレイズ 液晶表示装置および映像信号線駆動手段
US6166670A (en) * 1998-11-09 2000-12-26 O'shaughnessy; Timothy G. Self calibrating current mirror and digital to analog converter
US6288563B1 (en) * 1998-12-31 2001-09-11 Intel Corporation Slew rate control
US6204683B1 (en) * 1999-05-18 2001-03-20 Intel Corporation Apparatus and method for reducing crosstalk in an integrated circuit which includes a signal bus
JP2001119009A (ja) 1999-10-15 2001-04-27 Fuji Film Microdevices Co Ltd 固体撮像装置
JP3600103B2 (ja) * 2000-02-04 2004-12-08 三洋電機株式会社 バッファ回路及びバッファ回路を備えるドライバ
US6366069B1 (en) * 2001-02-01 2002-04-02 Intel Corporation Hysteretic-mode multi-phase switching regulator
JP2003169261A (ja) * 2001-11-29 2003-06-13 Fuji Film Microdevices Co Ltd 駆動用集積回路
US6747475B2 (en) * 2001-12-17 2004-06-08 Intel Corporation Method and apparatus for driving a signal using switchable on-die termination
KR100486260B1 (ko) * 2002-09-11 2005-05-03 삼성전자주식회사 동기식 디램의 고주파수 동작을 위한 비트라인 센스앰프구동 제어회로 및 그 구동 제어방법
JP4155123B2 (ja) * 2003-06-27 2008-09-24 セイコーエプソン株式会社 半導体装置、これを用いた撮像装置および表示装置
KR100610020B1 (ko) * 2005-01-13 2006-08-08 삼성전자주식회사 반도체 메모리 장치에서의 셀 파워 스위칭 회로와 그에따른 셀 파워 전압 인가방법

Also Published As

Publication number Publication date
CN1956489A (zh) 2007-05-02
US20070092026A1 (en) 2007-04-26
US7521979B2 (en) 2009-04-21
KR20070045113A (ko) 2007-05-02
JP2007124084A (ja) 2007-05-17
CN100512370C (zh) 2009-07-08
KR100787326B1 (ko) 2007-12-21
TWI329419B (enExample) 2010-08-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees