TW200717536A - Memory with robust data sensing and method for sensing data - Google Patents

Memory with robust data sensing and method for sensing data

Info

Publication number
TW200717536A
TW200717536A TW095131664A TW95131664A TW200717536A TW 200717536 A TW200717536 A TW 200717536A TW 095131664 A TW095131664 A TW 095131664A TW 95131664 A TW95131664 A TW 95131664A TW 200717536 A TW200717536 A TW 200717536A
Authority
TW
Taiwan
Prior art keywords
data line
sensing
output terminal
data
coupled
Prior art date
Application number
TW095131664A
Other languages
English (en)
Other versions
TWI416534B (zh
Inventor
Bradford L Hunter
Shayan Zhang
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37592334&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW200717536(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200717536A publication Critical patent/TW200717536A/zh
Application granted granted Critical
Publication of TWI416534B publication Critical patent/TWI416534B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
TW095131664A 2005-09-01 2006-08-29 具強健式資料感測之記憶體及感測資料之方法 TWI416534B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/218,135 US7158432B1 (en) 2005-09-01 2005-09-01 Memory with robust data sensing and method for sensing data

Publications (2)

Publication Number Publication Date
TW200717536A true TW200717536A (en) 2007-05-01
TWI416534B TWI416534B (zh) 2013-11-21

Family

ID=37592334

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095131664A TWI416534B (zh) 2005-09-01 2006-08-29 具強健式資料感測之記憶體及感測資料之方法

Country Status (6)

Country Link
US (1) US7158432B1 (zh)
JP (1) JP2009506478A (zh)
KR (1) KR20080046639A (zh)
CN (1) CN101253570B (zh)
TW (1) TWI416534B (zh)
WO (1) WO2007027577A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476781B (zh) * 2007-05-09 2015-03-11 Freescale Semiconductor Inc 關於在記憶體陣列中低電壓資料路徑之電路以及其操作方法

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US8077533B2 (en) 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US7793172B2 (en) * 2006-09-28 2010-09-07 Freescale Semiconductor, Inc. Controlled reliability in an integrated circuit
US7656731B2 (en) 2007-03-30 2010-02-02 Qualcomm, Incorporated Semi-shared sense amplifier and global read line architecture
US7817491B2 (en) * 2007-09-28 2010-10-19 Hynix Semiconductor Inc. Bank control device and semiconductor device including the same
US7688656B2 (en) * 2007-10-22 2010-03-30 Freescale Semiconductor, Inc. Integrated circuit memory having dynamically adjustable read margin and method therefor
US8120975B2 (en) * 2009-01-29 2012-02-21 Freescale Semiconductor, Inc. Memory having negative voltage write assist circuit and method therefor
US20100208538A1 (en) * 2009-02-17 2010-08-19 Freescale Semiconductor, Inc. Sensing circuit for semiconductor memory
KR20140100005A (ko) 2013-02-04 2014-08-14 삼성전자주식회사 등화기 및 이를 구비한 반도체 메모리 장치
US9336890B1 (en) * 2014-10-17 2016-05-10 Cypress Semiconductor Corporation Simultaneous programming of many bits in flash memory
JP6620472B2 (ja) * 2015-09-08 2019-12-18 凸版印刷株式会社 半導体記憶装置
KR102557324B1 (ko) * 2016-02-15 2023-07-20 에스케이하이닉스 주식회사 메모리 장치
CN107305778B (zh) * 2016-04-18 2020-05-01 华邦电子股份有限公司 储存器电路以及储存器电路的预充电方法
US10811081B2 (en) * 2018-12-12 2020-10-20 Micron Technology, Inc. Apparatuses for decreasing write pull-up time and methods of use
US11043276B1 (en) 2020-02-20 2021-06-22 Sandisk Technologies Llc Sense amplifier architecture providing improved memory performance
US11450364B2 (en) * 2020-08-27 2022-09-20 Taiwan Semiconductor Manufacturing Company Ltd. Computing-in-memory architecture
DE102021110222B4 (de) 2021-02-26 2022-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Speicherschaltung und Betriebsverfahren dafür
CN114708896B (zh) 2021-02-26 2025-08-12 台湾积体电路制造股份有限公司 存储器电路及其操作方法
US12283338B2 (en) * 2022-04-29 2025-04-22 Samsung Electronics Co., Ltd. Global data line of multi-array synchronous random access memory (SRAM)
CN116978425A (zh) * 2022-04-29 2023-10-31 三星电子株式会社 多阵列同步随机访问存储器（sram）的全局数据线

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US4964083A (en) 1989-04-27 1990-10-16 Motorola, Inc. Non-address transition detection memory with improved access time
US5657292A (en) * 1996-01-19 1997-08-12 Sgs-Thomson Microelectronics, Inc. Write pass through circuit
JPH10283776A (ja) * 1997-04-04 1998-10-23 Mitsubishi Electric Corp 半導体記憶装置
AU7706198A (en) * 1997-05-30 1998-12-30 Micron Technology, Inc. 256 meg dynamic random access memory
JPH11328965A (ja) 1998-05-20 1999-11-30 Nec Corp 半導体記憶装置
US6198682B1 (en) 1999-02-13 2001-03-06 Integrated Device Technology, Inc. Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers
US6111796A (en) * 1999-03-01 2000-08-29 Motorola, Inc. Programmable delay control for sense amplifiers in a memory
US6137746A (en) 1999-07-28 2000-10-24 Alliance Semiconductor Corporation High performance random access memory with multiple local I/O lines
US6292402B1 (en) * 1999-12-08 2001-09-18 International Business Machines Corporation Prefetch write driver for a random access memory
JP2001291389A (ja) * 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路
US6445216B1 (en) * 2001-05-14 2002-09-03 Intel Corporation Sense amplifier having reduced Vt mismatch in input matched differential pair
JP2003151267A (ja) * 2001-11-09 2003-05-23 Fujitsu Ltd 半導体記憶装置
US6885600B2 (en) * 2002-09-10 2005-04-26 Silicon Storage Technology, Inc. Differential sense amplifier for multilevel non-volatile memory
JP2004213829A (ja) * 2003-01-08 2004-07-29 Renesas Technology Corp 半導体記憶装置
US7242624B2 (en) * 2005-06-14 2007-07-10 Qualcomm Incorporated Methods and apparatus for reading a full-swing memory array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476781B (zh) * 2007-05-09 2015-03-11 Freescale Semiconductor Inc 關於在記憶體陣列中低電壓資料路徑之電路以及其操作方法

Also Published As

Publication number Publication date
US7158432B1 (en) 2007-01-02
CN101253570A (zh) 2008-08-27
JP2009506478A (ja) 2009-02-12
CN101253570B (zh) 2010-09-01
WO2007027577A2 (en) 2007-03-08
TWI416534B (zh) 2013-11-21
KR20080046639A (ko) 2008-05-27
WO2007027577A3 (en) 2007-07-05

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