TW200710946A - Method for manufacturing semiconductor apparatus and the semiconductor apparatus - Google Patents
Method for manufacturing semiconductor apparatus and the semiconductor apparatusInfo
- Publication number
- TW200710946A TW200710946A TW095125481A TW95125481A TW200710946A TW 200710946 A TW200710946 A TW 200710946A TW 095125481 A TW095125481 A TW 095125481A TW 95125481 A TW95125481 A TW 95125481A TW 200710946 A TW200710946 A TW 200710946A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor layer
- formation region
- semiconductor apparatus
- semiconductor
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 15
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 5
- 238000005530 etching Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005203917A JP2007027231A (ja) | 2005-07-13 | 2005-07-13 | 半導体装置の製造方法及び、半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200710946A true TW200710946A (en) | 2007-03-16 |
Family
ID=37609696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095125481A TW200710946A (en) | 2005-07-13 | 2006-07-12 | Method for manufacturing semiconductor apparatus and the semiconductor apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7316943B2 (zh) |
| JP (1) | JP2007027231A (zh) |
| KR (1) | KR100823109B1 (zh) |
| CN (1) | CN1897234A (zh) |
| TW (1) | TW200710946A (zh) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006128428A (ja) * | 2004-10-29 | 2006-05-18 | Seiko Epson Corp | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 |
| JP4867225B2 (ja) * | 2005-07-27 | 2012-02-01 | セイコーエプソン株式会社 | 半導体基板の製造方法及び、半導体装置の製造方法 |
| GB2460471B (en) * | 2008-05-31 | 2011-11-23 | Filtronic Compound Semiconductors Ltd | A field effect transistor and a method of manufacture thereof |
| CN101986435B (zh) * | 2010-06-25 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | 防止浮体及自加热效应的mos器件结构的制造方法 |
| JP5915181B2 (ja) * | 2011-04-05 | 2016-05-11 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| JP5768456B2 (ja) | 2011-04-18 | 2015-08-26 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| JP5659978B2 (ja) * | 2011-07-19 | 2015-01-28 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| CN103545215B (zh) | 2012-07-17 | 2016-06-29 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| US9087869B2 (en) * | 2013-05-23 | 2015-07-21 | International Business Machines Corporation | Bulk semiconductor fins with self-aligned shallow trench isolation structures |
| US10170304B1 (en) | 2017-10-25 | 2019-01-01 | Globalfoundries Inc. | Self-aligned nanotube structures |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04115560A (ja) * | 1990-09-05 | 1992-04-16 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
| KR100246602B1 (ko) * | 1997-07-31 | 2000-03-15 | 정선종 | 모스트랜지스터및그제조방법 |
| US5882958A (en) * | 1997-09-03 | 1999-03-16 | Wanlass; Frank M. | Damascene method for source drain definition of silicon on insulator MOS transistors |
| US6198142B1 (en) | 1998-07-31 | 2001-03-06 | Intel Corporation | Transistor with minimal junction capacitance and method of fabrication |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ |
| KR100332108B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
| JP2002299591A (ja) | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体装置 |
| US6469350B1 (en) | 2001-10-26 | 2002-10-22 | International Business Machines Corporation | Active well schemes for SOI technology |
| KR100485690B1 (ko) * | 2002-10-26 | 2005-04-27 | 삼성전자주식회사 | 모스 트랜지스터 및 그 제조방법 |
| KR100505113B1 (ko) * | 2003-04-23 | 2005-07-29 | 삼성전자주식회사 | 모스 트랜지스터 및 그 제조방법 |
| KR100553683B1 (ko) * | 2003-05-02 | 2006-02-24 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| KR100583725B1 (ko) | 2003-11-07 | 2006-05-25 | 삼성전자주식회사 | 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법 |
| KR100513310B1 (ko) * | 2003-12-19 | 2005-09-07 | 삼성전자주식회사 | 비대칭 매몰절연막을 채택하여 두 개의 다른 동작모드들을갖는 반도체소자 및 그것을 제조하는 방법 |
-
2005
- 2005-07-13 JP JP2005203917A patent/JP2007027231A/ja active Pending
-
2006
- 2006-07-11 CN CNA2006101019424A patent/CN1897234A/zh active Pending
- 2006-07-12 TW TW095125481A patent/TW200710946A/zh unknown
- 2006-07-12 KR KR1020060065377A patent/KR100823109B1/ko not_active IP Right Cessation
- 2006-07-13 US US11/486,849 patent/US7316943B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7316943B2 (en) | 2008-01-08 |
| US20070020828A1 (en) | 2007-01-25 |
| CN1897234A (zh) | 2007-01-17 |
| JP2007027231A (ja) | 2007-02-01 |
| KR20070008442A (ko) | 2007-01-17 |
| KR100823109B1 (ko) | 2008-04-18 |
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