TW200710409A - Method and structures for measuring gate tunneling leakage parameters of field effect transistors - Google Patents

Method and structures for measuring gate tunneling leakage parameters of field effect transistors

Info

Publication number
TW200710409A
TW200710409A TW095116020A TW95116020A TW200710409A TW 200710409 A TW200710409 A TW 200710409A TW 095116020 A TW095116020 A TW 095116020A TW 95116020 A TW95116020 A TW 95116020A TW 200710409 A TW200710409 A TW 200710409A
Authority
TW
Taiwan
Prior art keywords
dielectric layer
structures
thickness
field effect
effect transistors
Prior art date
Application number
TW095116020A
Other languages
English (en)
Inventor
Myung-Hee Na
Edward J Nowak
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200710409A publication Critical patent/TW200710409A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW095116020A 2005-05-09 2006-05-05 Method and structures for measuring gate tunneling leakage parameters of field effect transistors TW200710409A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/908,351 US7011980B1 (en) 2005-05-09 2005-05-09 Method and structures for measuring gate tunneling leakage parameters of field effect transistors

Publications (1)

Publication Number Publication Date
TW200710409A true TW200710409A (en) 2007-03-16

Family

ID=35998739

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095116020A TW200710409A (en) 2005-05-09 2006-05-05 Method and structures for measuring gate tunneling leakage parameters of field effect transistors

Country Status (6)

Country Link
US (1) US7011980B1 (zh)
EP (1) EP1886156A4 (zh)
JP (1) JP4653217B2 (zh)
CN (1) CN101427378B (zh)
TW (1) TW200710409A (zh)
WO (1) WO2006122096A2 (zh)

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US8608080B2 (en) * 2006-09-26 2013-12-17 Feinics Amatech Teoranta Inlays for security documents
US7546671B2 (en) * 2006-09-26 2009-06-16 Micromechanic And Automation Technology Ltd. Method of forming an inlay substrate having an antenna wire
US20080179404A1 (en) * 2006-09-26 2008-07-31 Advanced Microelectronic And Automation Technology Ltd. Methods and apparatuses to produce inlays with transponders
US8240022B2 (en) * 2006-09-26 2012-08-14 Feinics Amatech Teorowita Methods of connecting an antenna to a transponder chip
US7979975B2 (en) * 2007-04-10 2011-07-19 Feinics Amatech Teavanta Methods of connecting an antenna to a transponder chip
US7581308B2 (en) 2007-01-01 2009-09-01 Advanced Microelectronic And Automation Technology Ltd. Methods of connecting an antenna to a transponder chip
US8322624B2 (en) * 2007-04-10 2012-12-04 Feinics Amatech Teoranta Smart card with switchable matching antenna
US7980477B2 (en) * 2007-05-17 2011-07-19 Féinics Amatech Teoranta Dual interface inlays
US8064832B2 (en) * 2007-07-18 2011-11-22 Advanced Micro Devices, Inc. Method and test system for determining gate-to-body current in a floating body FET
US7893494B2 (en) * 2008-06-18 2011-02-22 International Business Machines Corporation Method and structure for SOI body contact FET with reduced parasitic capacitance
CN101447514B (zh) * 2008-12-30 2012-06-20 上海宏力半导体制造有限公司 金属氧化物半导体场效应晶体管
DE112011103554T5 (de) * 2010-10-20 2013-09-05 Peregrine Semiconductor Corp. Verfahren und Vorrichtung zur Verwendung bei der Verbesserung einer Linearität von Mosfets unter Verwendung einer Ladungsakkumulationssenke - Reduktion harmonischer Falten
JP5521993B2 (ja) * 2010-11-17 2014-06-18 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
US8698245B2 (en) 2010-12-14 2014-04-15 International Business Machines Corporation Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure
CN102332394A (zh) * 2011-07-28 2012-01-25 上海宏力半导体制造有限公司 半导体器件、mos晶体管及其形成方法
CN102306644B (zh) * 2011-08-29 2016-02-03 上海华虹宏力半导体制造有限公司 Soi型mos晶体管的测试结构及其的形成方法
CN102683416B (zh) * 2012-05-17 2014-12-17 中国科学院微电子研究所 Soi mos晶体管
DE102016109137B3 (de) * 2016-05-18 2017-06-08 Lisa Dräxlmaier GmbH Überwachungsvorrichtung und Überwachungsverfahren
CN108231899B (zh) * 2017-12-26 2021-07-20 上海集成电路研发中心有限公司 一种soi体接触器件及其制作方法
FR3076398B1 (fr) * 2017-12-29 2019-12-27 X-Fab France Transistor et son procede de fabrication

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Also Published As

Publication number Publication date
CN101427378B (zh) 2011-03-23
EP1886156A2 (en) 2008-02-13
WO2006122096A3 (en) 2008-11-20
JP2008544482A (ja) 2008-12-04
CN101427378A (zh) 2009-05-06
US7011980B1 (en) 2006-03-14
EP1886156A4 (en) 2010-12-29
WO2006122096A2 (en) 2006-11-16
JP4653217B2 (ja) 2011-03-16

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