TW200625547A - Method for forming storage node of capacitor in semiconductor device - Google Patents

Method for forming storage node of capacitor in semiconductor device

Info

Publication number
TW200625547A
TW200625547A TW094119760A TW94119760A TW200625547A TW 200625547 A TW200625547 A TW 200625547A TW 094119760 A TW094119760 A TW 094119760A TW 94119760 A TW94119760 A TW 94119760A TW 200625547 A TW200625547 A TW 200625547A
Authority
TW
Taiwan
Prior art keywords
forming
storage node
insulation layer
contact holes
capacitor
Prior art date
Application number
TW094119760A
Other languages
English (en)
Other versions
TWI281231B (en
Inventor
Jun-Hyeub Sun
Sung-Kwon Lee
Sung-Yoon Cho
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040108694A external-priority patent/KR100721548B1/ko
Priority claimed from KR1020040110083A external-priority patent/KR100623599B1/ko
Priority claimed from KR1020040112821A external-priority patent/KR100733458B1/ko
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200625547A publication Critical patent/TW200625547A/zh
Application granted granted Critical
Publication of TWI281231B publication Critical patent/TWI281231B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335Making a connection between the transistor and the capacitor, e.g. plug
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094119760A 2004-12-20 2005-06-15 Method for forming storage node of capacitor in semiconductor device TWI281231B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020040108694A KR100721548B1 (ko) 2004-12-20 2004-12-20 반도체 소자의 캐패시터 스토리지 노드 형성방법
KR1020040110083A KR100623599B1 (ko) 2004-12-22 2004-12-22 반도체 소자의 캐패시터 스토리지 노드 형성방법
KR1020040112821A KR100733458B1 (ko) 2004-12-27 2004-12-27 반도체 소자의 캐패시터 스토리지 노드 형성방법

Publications (2)

Publication Number Publication Date
TW200625547A true TW200625547A (en) 2006-07-16
TWI281231B TWI281231B (en) 2007-05-11

Family

ID=36594577

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094119760A TWI281231B (en) 2004-12-20 2005-06-15 Method for forming storage node of capacitor in semiconductor device

Country Status (3)

Country Link
US (2) US7410866B2 (zh)
JP (1) JP5294182B2 (zh)
TW (1) TWI281231B (zh)

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US20080050871A1 (en) * 2006-08-25 2008-02-28 Stocks Richard L Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures
CN100468695C (zh) * 2006-12-04 2009-03-11 中芯国际集成电路制造(上海)有限公司 改善多晶硅缺陷的方法
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
KR20100087915A (ko) * 2009-01-29 2010-08-06 삼성전자주식회사 실린더형 스토리지 노드를 포함하는 반도체 메모리 소자 및그 제조 방법
KR20120093731A (ko) * 2011-02-15 2012-08-23 에스케이하이닉스 주식회사 반도체소자의 스토리지노드 형성방법 및 이를 이용한 커패시터 형성방법
US9312222B2 (en) * 2013-03-12 2016-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Patterning approach for improved via landing profile
US10510598B2 (en) 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned spacers and method forming same
DE102017120290B3 (de) * 2017-09-04 2018-11-08 Infineon Technologies Ag Verfahren zum Prozessieren einer Schichtstruktur
US10727123B2 (en) * 2018-06-18 2020-07-28 International Business Machines Corporation Interconnect structure with fully self-aligned via pattern formation
CN111106008B (zh) * 2019-12-09 2022-06-10 福建福顺微电子有限公司 一种平坦化反刻方法
US11276571B2 (en) 2019-12-26 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method of breaking through etch stop layer
TWI762112B (zh) * 2019-12-26 2022-04-21 台灣積體電路製造股份有限公司 半導體裝置的形成方法
US11211291B2 (en) * 2020-04-03 2021-12-28 International Business Machines Corporation Via formation with robust hardmask removal
US20230141895A1 (en) * 2021-11-08 2023-05-11 Nanya Technology Corporation Method for preparing semiconductor device structure with silicide portion between conductive plugs

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JP3532325B2 (ja) * 1995-07-21 2004-05-31 株式会社東芝 半導体記憶装置
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KR20030050052A (ko) 2001-12-18 2003-06-25 주식회사 하이닉스반도체 캐패시터 및 그 제조방법
KR100449321B1 (ko) * 2001-12-24 2004-09-18 동부전자 주식회사 반도체소자의 제조방법
US6548853B1 (en) * 2002-02-13 2003-04-15 Samsung Electronics Co., Ltd. Cylindrical capacitors having a stepped sidewall and methods for fabricating the same
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KR100486273B1 (ko) * 2002-10-16 2005-04-29 삼성전자주식회사 스토리지 전극을 포함하는 반도체 소자 및 그 제조 방법
KR100506816B1 (ko) 2003-01-06 2005-08-09 삼성전자주식회사 반도체 장치 커패시터의 하부 전극 및 이를 형성하기 위한방법
KR100476690B1 (ko) * 2003-01-17 2005-03-18 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100587635B1 (ko) * 2003-06-10 2006-06-07 주식회사 하이닉스반도체 반도체소자의 제조 방법
KR100555512B1 (ko) * 2003-07-31 2006-03-03 삼성전자주식회사 폴리실리콘 식각 마스크를 이용한 반도체 소자의 제조방법
KR100780610B1 (ko) * 2003-11-28 2007-11-29 주식회사 하이닉스반도체 반도체소자 제조 방법
KR100611777B1 (ko) * 2003-12-22 2006-08-11 주식회사 하이닉스반도체 반도체소자 제조 방법
KR100656283B1 (ko) 2005-12-14 2006-12-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법

Also Published As

Publication number Publication date
US20080293212A1 (en) 2008-11-27
TWI281231B (en) 2007-05-11
US20060131630A1 (en) 2006-06-22
JP2006179853A (ja) 2006-07-06
US7790546B2 (en) 2010-09-07
JP5294182B2 (ja) 2013-09-18
US7410866B2 (en) 2008-08-12

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