TW200615976A - Parallel compression test circuit of memory device - Google Patents
Parallel compression test circuit of memory deviceInfo
- Publication number
- TW200615976A TW200615976A TW093139261A TW93139261A TW200615976A TW 200615976 A TW200615976 A TW 200615976A TW 093139261 A TW093139261 A TW 093139261A TW 93139261 A TW93139261 A TW 93139261A TW 200615976 A TW200615976 A TW 200615976A
- Authority
- TW
- Taiwan
- Prior art keywords
- compression test
- parallel compression
- test circuit
- memory device
- input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
- G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040093222A KR100694418B1 (ko) | 2004-11-15 | 2004-11-15 | 메모리 장치의 병렬 압축 테스트 회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200615976A true TW200615976A (en) | 2006-05-16 |
TWI263231B TWI263231B (en) | 2006-10-01 |
Family
ID=36575792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093139261A TWI263231B (en) | 2004-11-15 | 2004-12-17 | Parallel compression test circuit of memory device |
Country Status (3)
Country | Link |
---|---|
US (1) | US7187195B2 (zh) |
KR (1) | KR100694418B1 (zh) |
TW (1) | TWI263231B (zh) |
Families Citing this family (86)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070070740A1 (en) * | 2005-09-28 | 2007-03-29 | Hynix Semiconductor Inc. | Semiconductor memory device having data-compress test mode |
US20070226553A1 (en) * | 2006-03-21 | 2007-09-27 | Khaled Fekih-Romdhane | Multiple banks read and data compression for back end test |
KR100695435B1 (ko) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
KR101202537B1 (ko) * | 2006-05-12 | 2012-11-19 | 애플 인크. | 메모리 디바이스를 위한 결합된 왜곡 추정 및 에러 보정 코딩 |
WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
CN103208309B (zh) | 2006-05-12 | 2016-03-09 | 苹果公司 | 存储设备中的失真估计和消除 |
US8239735B2 (en) * | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
KR100761394B1 (ko) * | 2006-06-29 | 2007-09-27 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US7596729B2 (en) * | 2006-06-30 | 2009-09-29 | Micron Technology, Inc. | Memory device testing system and method using compressed fail data |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US7975192B2 (en) | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) * | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7593263B2 (en) * | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
US7900102B2 (en) * | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US8151166B2 (en) * | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) * | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
CN101715595A (zh) * | 2007-03-12 | 2010-05-26 | 爱诺彼得技术有限责任公司 | 存储器单元读取阈的自适应估计 |
US8001320B2 (en) * | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
KR100878307B1 (ko) * | 2007-05-11 | 2009-01-14 | 주식회사 하이닉스반도체 | 멀티 워드라인 테스트 제어 회로 및 그의 제어 방법 |
US8234545B2 (en) * | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
KR100907927B1 (ko) * | 2007-06-13 | 2009-07-16 | 주식회사 하이닉스반도체 | 반도체메모리소자 및 그의 구동방법 |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
KR100884343B1 (ko) * | 2007-08-23 | 2009-02-18 | 주식회사 하이닉스반도체 | 쓰기 구동 회로 |
US8174905B2 (en) * | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8527819B2 (en) * | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8068360B2 (en) * | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8270246B2 (en) * | 2007-11-13 | 2012-09-18 | Apple Inc. | Optimized selection of memory chips in multi-chips memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) * | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
US8085586B2 (en) * | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
JP5527957B2 (ja) * | 2008-01-30 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びその制御方法 |
US8156398B2 (en) * | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) * | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) * | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) * | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
KR20090114940A (ko) * | 2008-04-30 | 2009-11-04 | 주식회사 하이닉스반도체 | 반도체 메모리 소자와 그의 구동 방법 및 압축 테스트 방법 |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8248831B2 (en) * | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8832354B2 (en) * | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
KR101069677B1 (ko) * | 2009-06-09 | 2011-10-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 이를 위한 프로브 테스트 제어 회로 |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
KR101069681B1 (ko) * | 2009-07-30 | 2011-10-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
KR101033490B1 (ko) * | 2009-11-30 | 2011-05-09 | 주식회사 하이닉스반도체 | 패드를 선택적으로 이용하는 반도체 메모리 장치 |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
KR101083675B1 (ko) * | 2009-12-28 | 2011-11-16 | 주식회사 하이닉스반도체 | 데이터 압축 테스트 회로를 포함하는 반도체 메모리 장치 |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
KR20110088947A (ko) * | 2010-01-29 | 2011-08-04 | 주식회사 하이닉스반도체 | 반도체 메모리의 데이터 출력 회로 |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
KR101188261B1 (ko) * | 2010-07-30 | 2012-10-05 | 에스케이하이닉스 주식회사 | 멀티 비트 테스트 회로 |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
KR101282722B1 (ko) * | 2011-03-09 | 2013-07-04 | 에스케이하이닉스 주식회사 | 메모리 장치 및 메모리 장치의 테스트 방법 |
KR20120121225A (ko) | 2011-04-26 | 2012-11-05 | 에스케이하이닉스 주식회사 | 반도체 칩을 멀티테스트하기 위한 장치 및 방법 |
KR102077072B1 (ko) * | 2013-07-05 | 2020-02-14 | 에스케이하이닉스 주식회사 | 병렬 테스트 장치 및 방법 |
KR20180085418A (ko) * | 2017-01-18 | 2018-07-27 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템 |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2717712B2 (ja) | 1989-08-18 | 1998-02-25 | 三菱電機株式会社 | 半導体記憶装置 |
TW200603B (en) | 1991-04-11 | 1993-02-21 | Hitachi Seisakusyo Kk | Semiconductor memory device |
US6026505A (en) * | 1991-10-16 | 2000-02-15 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
JPH05325598A (ja) * | 1992-05-22 | 1993-12-10 | Texas Instr Japan Ltd | 半導体記憶装置 |
JP3409527B2 (ja) * | 1995-08-17 | 2003-05-26 | 富士通株式会社 | 半導体記憶装置 |
JPH09231794A (ja) * | 1996-02-21 | 1997-09-05 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置および測定回路 |
US5717701A (en) | 1996-08-13 | 1998-02-10 | International Business Machines Corporation | Apparatus and method for testing interconnections between semiconductor devices |
KR100322525B1 (ko) | 1998-03-23 | 2002-06-22 | 윤종용 | 출력드라이버를공유하는병렬비트테스트회로및이를이용한병렬비트테스트방법 |
JP2000067599A (ja) | 1998-08-13 | 2000-03-03 | Texas Instr Inc <Ti> | 半導体素子用ツ―パス多重状態並列試験 |
KR100529394B1 (ko) | 1999-06-28 | 2005-11-17 | 주식회사 하이닉스반도체 | 테스트 구현을 위한 반도체메모리장치의 데이터 압축 회로 |
US6484289B1 (en) | 1999-09-23 | 2002-11-19 | Texas Instruments Incorporated | Parallel data test for a semiconductor memory |
US6307790B1 (en) | 2000-08-30 | 2001-10-23 | Micron Technology, Inc. | Read compression in a memory |
JP2002093162A (ja) | 2000-09-20 | 2002-03-29 | Toshiba Corp | 半導体メモリ集積回路 |
DE10150441B4 (de) | 2001-10-12 | 2004-04-08 | Infineon Technologies Ag | Verfahren zum Testen von Halbleiterspeichern |
JP2003338200A (ja) | 2002-05-17 | 2003-11-28 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US6590799B1 (en) * | 2002-05-29 | 2003-07-08 | Agilent Technologies, Inc. | On-chip charge distribution measurement circuit |
US6714469B2 (en) * | 2002-07-02 | 2004-03-30 | Agilent Technologies, Inc. | On-chip compression of charge distribution data |
-
2004
- 2004-11-15 KR KR1020040093222A patent/KR100694418B1/ko not_active IP Right Cessation
- 2004-12-10 US US11/008,298 patent/US7187195B2/en not_active Expired - Fee Related
- 2004-12-17 TW TW093139261A patent/TWI263231B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US20060123291A1 (en) | 2006-06-08 |
KR100694418B1 (ko) | 2007-03-12 |
TWI263231B (en) | 2006-10-01 |
KR20060054611A (ko) | 2006-05-23 |
US7187195B2 (en) | 2007-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI263231B (en) | Parallel compression test circuit of memory device | |
EP2276169A3 (en) | High reliability RF generator architecture | |
GB0418944D0 (en) | Method for envelope clipping | |
GB2434494B (en) | Low noise amplifier | |
EP1959563A3 (en) | Doherty amplifying apparatus using a harmonic control circuit | |
WO2004027983A3 (en) | Saturated power amplifier with selectable and variable output power levels | |
EP1846660B8 (de) | Verfahren zur optimierung des betriebs mehrerer verdichteraggregate und vorrichtung hierzu | |
TW200721192A (en) | Device for controlling on die termination | |
GB2446350A (en) | Method and apparatus for reducing current consumption of mimo systems | |
WO2008042709A3 (en) | Enhanced doherty amplifier with asymmetrical semiconductors | |
TW200622547A (en) | Differential power supply controller and method therefor | |
TW200703884A (en) | Miller-compensated amplifier | |
ATE515105T1 (de) | Leistungsverstärker | |
GB2446351A (en) | Method and apparatus for optimizing current consumption of amplifiers with power control | |
TWI266331B (en) | Parallel compression test circuit of memory device | |
TW200713809A (en) | Surge absorption circuit | |
WO2009139814A3 (en) | Modified distributed amplifier to improve low frequency efficiency and noise figure | |
WO2009123828A3 (en) | Compact circuit-simulation output | |
WO2008078468A1 (ja) | 送信装置及び通信装置 | |
EP1566886A3 (en) | Power amplification apparatus, and mobile communication terminal apparatus | |
TW200719348A (en) | Load-balnaced apparatus of memory | |
TWI256048B (en) | A circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof | |
WO2007137947A3 (en) | High-speed low-power integrated circuit interconnects | |
TW200640144A (en) | Clock generating method and circuit thereof | |
TW200644373A (en) | Surge absorption circuit and laminated surge absorption device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |