TW200532871A - Resin-sealed semiconductor device and method of manufacturing the same - Google Patents
Resin-sealed semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- TW200532871A TW200532871A TW094104584A TW94104584A TW200532871A TW 200532871 A TW200532871 A TW 200532871A TW 094104584 A TW094104584 A TW 094104584A TW 94104584 A TW94104584 A TW 94104584A TW 200532871 A TW200532871 A TW 200532871A
- Authority
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- Taiwan
- Prior art keywords
- wafer
- resin
- aforementioned
- semiconductor device
- item
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229920005989 resin Polymers 0.000 claims abstract description 92
- 239000011347 resin Substances 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 235000012431 wafers Nutrition 0.000 claims description 159
- 239000004020 conductor Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 3
- 238000000465 moulding Methods 0.000 abstract description 3
- 238000001721 transfer moulding Methods 0.000 abstract description 3
- 239000008188 pellet Substances 0.000 abstract 3
- 238000009413 insulation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 240000005343 Azadirachta indica Species 0.000 description 1
- 241000283690 Bos taurus Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 235000013500 Melia azadirachta Nutrition 0.000 description 1
- 206010033799 Paralysis Diseases 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 150000007974 melamines Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920013636 polyphenyl ether polymer Polymers 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 βτ resin (_) Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
200532871 ,九、發明說明: 【發明所屬之技術領域】 於關於一種半導體裝置,更具體而言,係關 裝置及其:造=“件以樹脂封裝之樹脂封裝型半導體 【先前技術】 行封與電阻等晶片元件利用鑄模樹脂進 二 裝置為。其注入鑄模樹脂之方法 ' ' ranSferraoldlng)法(例如:參照專利文獻j
及專利文獻2)。 …畎L 移鑄模法進行樹脂封裝過”,要施加較高 ^於 卜刀。尤其是在追求裝置之超薄化時,由於垂 施二=旨之流動方向之剖面積減少,因而更高的壓力 二:^分。由於注入之鑄模樹脂之壓力,使連接半 模:r之^與導線電極等之接合線(bonding Wlre)在鑄 杈树月曰之流動方向受力。 接合線間之接觸,而有 卜^接合線之剝落及相鄰 詈之制、主自σ方 成不良。口的可能,成為半導體裝 置之衣k良口口率降低的重要原因。 f利文獻1·曰本專利特開平9 —⑺匕號公報 【發明内容】 本專料開平1卜况344號公報 ,發明係鑒於上述問題而研創者,其目的在於提供一 口匕=接合線斷線及接合線間接觸等引起之接觸不良之 衣型切體裝置及樹脂料料導體裝置之製造方 316778 5 200532871 t 法0 本發明之樹㈣裝型半導體裝置之第 、 備:設置有導體電路之絕緣美执 、,7心寸喊為具 、土材,5又置於前述絕缕其 與前述導體電路以導後接人< · u 、·巴、,彖基材上、 泽綠接合(wlre bonding)之半導邮ΰ · 安裝於前述絕緣基材上之福 千V肢片, 半導體片與前述複數曰片硬以及封裝前述 、钹数日日片7G件之封裝樹脂,其中, 丽述樹脂之際,至少在丨個 在/主入 前述丰導妒Μ、ώ# 方向,方;用以遮蔽前述樹脂對 ί:體“動的位置配置有前述複數個晶片元件。 猎由上述構成,注人樹脂時之朝半導體片之^ 之流動係受到晶片元件遮蔽,故緩和施加在半導體片2 之注入樹脂的壓力,可抑制導線接合之連接不良。 本發明之樹脂封裝型半導體裝置之 備:設置有導體電路乐办心特斂為其 盘前述導置於前述料基材上、 複數個晶片元件:;;月:以=裝前,半導趙片與前述 封衣樹月曰,其中,丽述複數個晶片元件 ’料“粗片的四邊予以包圍,且前述複數個晶片元件 的長度方向係朝向_定的方向。 片兀件 曰 據上述構成,藉由使注入樹脂之流動方向垂直於各 士片匕元:之長度方向’以緩和施加於半導體片周邊之注人 树月曰之壓力’從而可抑制導線流動,減少導線接合之連接 良使由半$體片之邊與長度方向設置為相同方向之晶 片兀件構成之晶片元件列與半導體片之距離越靠近,命能 有效將施加於半導體周邊之注人樹脂之壓力予以緩和了 316778 6 200532871 • 本&明之樹脂封裝型半導俨穿詈之坌-;^ & 備:設置有導體電路之絕峻其: 弟二形悲特徵為具 與前述導體電路基材;設置於前述絕緣基材上、 基材上之複數個晶=合之半導體片;安裝於前述絕緣 複數個晶片元件之封裝樹脂以=:物體 將前述半導體片之曰八,刖述複數個晶片元件 • 片之四邊予以包圍, .之各邊設置之晶片元件列中所包含之晶、=2體片 係朝向沿前述半導體片之各邊之方向。件之長度方向 體片: = 吏將注入樹脂之流動方向朝向半導 樹脂之虔力,從而^可緩和施加於半導體片周邊之注入 良。複數個晶流動,減少⑽ 效將施加於半導體周套半¥體片之距離越靠近,則愈能有 σ邊之注入樹脂之壓力予以緩和。 柄明之樹脂封裝型半導體裝置 備:設置有導體電 #四幵八^政為具 癱與前料體電㈣前述絕緣基材上、 •基材上之複數個晶片:°之+導體片;安裝於前述絕緣 複數個晶片元件之封二:以::裝前述半導體片與前述 係沿前述絕緣基材之ί = ’其中’前述複數個晶片元件 長度方向乃朝向—定=核設,前述複數個晶片元件之 晶片元件之長=向猎由使注入樹脂之流動方向垂直於各 樹脂之-力,二;緩和施加於半導體片周邊之注入 卜 *而抑制導線流動,減少導線接合之連接不 316778 7 200532871 本發明之樹脂封裝型半導體裝置之第五形態特徵為呈 備:設置有導體電路之絕緣基#;設置於前述絕緣基材上、 與前述導體電路以導線接合之半導體片;安裝於前述絕緣 基材上之複數個晶片元件;以及封裝前述半導體片與 t數:晶片元件之封裝樹脂,其中,前述複數個晶片元; T b月j 基材之周緣部配設,對應於前述絕緣基材之 =置之晶片元件列所包含之晶片元件之長度方向係朝 向沿刖述絕緣基材之各邊的方向。 藉由t述構成,即使注入樹脂之流動方向朝向絕緣基 才之任一达方向’也可緩和施加於半導體 脂之屋力,從而抑制導線流動,減少導線接合之連接不入良树 備:設本=導=旨封裝型半導體裝置之第六形態特徵為具 盥于^雕、币版%路之絕緣基材;設置於前述絕緣基材上、 /、别電路以導線接合之半 基材上之複數個Β ΰ _ π 文衣於則述絶緣 複數個晶片元以及封裝前述半導體片與前述 元件構成之2列、 月日’其中,將由前述複數個晶片 一,以上晶片元件列配置於前述半導體片之某 邊附近’使前述複數 a 導體片之某—邊^ 件之長度方向朝向前述半 件在曰片:彼 向’各晶片兀件列中所包含之各晶片元 含之各s 7財向之位置係與相鄰之晶片元件列中所包 各日日片元件偏移成相互錯開。 晶片元St氕藉由使注入樹脂之流動方向垂直於各 入樹脂之壓力,二::之長度方向’可更有效地緩和注 冋4更有效地抑制導線流動。 316778 8 .200532871 一 本每明之樹脂封裝型丰 備:設置有導料路之料形態特徵為具 ^ ^ ^ 、·象基材,s又置於珂述絕緣基材上、 與刚述導體電路以導線接合 基材上之複數個晶片元件. 片,^於前述絕緣 裝樹脂,其中,將由前述複數晶片元
件構成之曰曰片兀件列gp署你A 使前述複數個晶片元件之二 ==之某-邊附近, 一 之長度方向朝向前述半導體片之某 元件。° ’且在前述晶片元件列上設置有虛擬(du_y)晶片 不俨:=这:成’即使樹脂封裝型半導體裝置在結構上 = 設在期望位置,藉由在不能配設晶片元 之、、主入m f 4疑晶片元件’也可確實遮蔽朝向半導體片 之/主入樹脂之流動的去路。 本發明之半導體裝置之萝# 體電路之㈣W卜 之錢方,去,係將設置於設有導 與前述導體電路以導線接合之半導 ,::人表面封裝型之複數個晶片元件以樹脂進行封裝者, 個!:為r:沿前述半導體片之至少-邊配置前述複數 俾使晶片元件之長度方向朝向前述-邊方向 :::;?前述絕緣基材放置在模具成型器之模槽,使前 向固:片凡件之長度方向實質上垂直於前述樹脂之注 件^之"驟;以及相對於前述半導體片與前述晶片元 件’將耵述樹脂注入之步驟。 動係述半導體裝置之製造方法,由於注入樹脂之流 '、曰硬數個晶片兀件遮蔽,故可抑制連接到半導體片 316778 9 200532871 之導線接合的導線流動,從 之連接不&。 ㈣树月曰封裝時之導線接合 再者,將上述各要素進行適當 本案申請中對於專利申請 亦包3在 【實施方式】 回要求保瘦之本發明之範圍。 (實施例1) 弟1圖為貫施例1之半導 圖為沿第!圖之Η線之俯視圖’第2 I緣基材2〇、半導體片3〇、複數個===〇包括有絕 樹脂50。半導體片3〇 = 〇、以及鑄模 美姑川卜“丄 是數個日日片兀件40係設置於絕緣 ㈣,在第:Γ用轉移铸模法成型之鑄模樹脂5°封裝。 在4 1圖之俯視时省略鑄模樹脂50。 =:W2。之材料可為例如:βτ樹脂(_)等 一承fl胺(melamine)衍生物、洛曰取人此
丁玍物液日日聚合物、環氧樹脂、PPE 亞胺樹脂、氣樹脂、㈣樹脂、 如blsmaieimide)等熱硬化 = 基材20可為單層也可為多層。 f導體片30之電極塾32係藉由導線接合與形成絕緣 土 〇上之導體電路(未圖示)的導線電極22電性連接, 金線接合3 4係連接雷#執q 9 22〇 逆接书極墊32與絕緣基材20側之導線電極 晶片元件40係以包圍半導體片3〇之四邊之 置雕與設於絕緣基材2G上之導體電路連接。日日日片元工件^ 具體為電容器、電感器、電阻器等。晶片元件4〇之尺寸係 316778 10 200532871 ,規格化為一定形狀,可適當使用所謂「1〇〇5尺寸」、「〇6〇3 尺寸」及「0402尺寸」。這裡所謂「1〇〇5尺寸」是指晶片 元件40之尺寸為ι.〇_χ 〇 5_χ 〇 5_,所謂「〇6〇3尺寸」 疋指晶片凡件40之尺寸為〇. 6mmx 〇· 3mmx 〇. 3_,所謂 「0402尺寸」是指晶片元件4〇之尺寸為〇 4_χ 〇 2_χ 〇.2_。如此’晶片元件4〇之長度方向與垂直方向之投影 面積會比寬度方向與垂直方向之投影面積大。鑄模樹脂5〇 之厚度至少比晶片元件4〇之高度還厚。 構成鑄模樹脂5 〇之材料可例如為環氧樹脂等熱硬化 性树如。且鑄模樹脂5〇可含有玻璃等填充物。 在實施例1中’包圍各半導體片3;之複數個晶片元件 長度方向係朝向一定方向。利用轉移鑄模法注入鎢模 樹脂5 0時,配置镱@w 、 T配置輪杈剛之+導體裝置10,使晶片元件4〇 ΐ導二==於鑄模樹脂50之流動成垂直。據此,朝向 t二妨樹脂5〇之流動係藉由晶片元件40而有 :=,故可降低連接於半導體片3〇之金線接 了 來自士所注入之鑄模樹月曰匕5〇之壓力。因此,在注入缚模齡
:’可抑制因導線流動使金線接合%自電極 戈J 線Ϊ極22脫落,或相鄰之金線接合34彼此間接觸的現^ =導_10之金線接合34之連接不 線接合3 4之遠技I㊁ , 牛低金 造良品率。 良,將有助於提高半導體褒置10之製 下面說明之實施例2以後之半導體|置1() 除晶片元件40之配晉衣置1〇的基本構成 配置不同外,均與實_!相同,故與實 3】6778 1) 200532871 =;::目同時’適當省略其說明,以下僅對本實施例 之%被構成加以說明。 (實施例2) 圖中:】:為實施例2之半導體裝置10之俯視圖。在第3 對库夂丰1~模樹脂5°。在實施例2之半導體裝置1", ==體片30之各邊設置之複數個晶片元件40的長 :移鑄模:向沿半導體片30之各邊之方向。因此,在利用 置10的杯主入城樹月旨50時’即使將鑄模前之半導體裝 入半導雕^邊相對於鑄模樹月旨50的流動作配置,由於流 =〇之鑄模樹脂50的流動會受到晶片元件40 可抑制半導體裝置1Q之金線接合%之導線 可降低金線接合34之連接不良。 (實施例3) 圖中2圖為實施例3之半導體裝置1G之俯視圖。在第4 I數個樹脂5G。在實施例3之半導體裝置10中’ 用轴# Ρ “ 、又方向朝向一定方向。藉由上述構成,在利 導體樹脂5。時’亦藉由設置鑄模前之半 ^ 使排成—定方向之晶片元件40之長度方向 脂50二:樹脂5〇之流動’使流向半導體片3〇之鑄模樹 机動稭由晶片元件40而有效遮蔽,故可抑制半 之金線接合34之導線流動,且降低金線接合以 (實施例4) 316778 12 200532871 第5圖為實施例4之半導體裝置1〇之俯視圖 5 圖中也省略I#模樹脂5〇。在實施例4之半導體裝置Μ中, 複數個晶片元件4〇與實施例3相同,也沿絕緣基材別 周緣部配設’但各晶片元件4G之長度方向係朝向沿半導麵 片30之各邊方向。因此,在利用轉移鑄模法注入鑄模樹: 50時,即使將鑄模前之半導體 樹脂5。之流動作配置,流1半二3〇邊朝向鎮模 的流動也由於晶片元件4 =;:片,模樹脂5。 (實施例5) 件4〇而被遮敵,從而抑制導線流動。 第6、圖為實施例5之半導體裝置1〇之俯視圖。在第6 :也名略•模樹脂50。在實施例5之半導體裝置工", 晶片兀件40係於半導體片3〇之—邊附 “平狀晶片7^列42及晶Η件列44而配置。配I 於晶片元件列42及晶片元件列44 配3又 7 J μ心曰曰月το件4 0之真疮士 =向;各行方向相同之方向。再者,自與列方向::直 方向硯看’晶片元件列42之晶片元件40,相對於晶片 凡件列44之晶片元件4〇係配置成相互錯開。亦即,曰片 :件列42,晶片元件4〇間之間隙位置,係相對於晶:元 列44之晶片7〇件4〇間之間隙位置,於行方 晶片元件40之長度方向的半個長度。藉由:開 轉移鑄模法注入鑄模樹脂5〇時, / 利用 裝置1〇,使晶片元件列42及曰:_由:置㈣之半導體 丨Τ〜以汉日日片兀件 向半導體片3◦之物则的流動。亦即,如第= 316778 13 200532871 .示,流向半導體片30之鑄模樹脂5〇之流動首先由晶片元 件列42遮蔽去路,使壓力衰減。然後,鱗模樹脂之泣 動通過晶片元件列42之晶片元件4〇間之間隙,: 件列44再次遮蔽去路,使壓力衰減。 aa/i 構成再=在實施例5中’晶片元件列可配置為3行以上 構成,自與行方向垂直之方向觀看,各晶片 •元件㈣對於相鄰之晶片元件狀晶^件4 = 互錯開’可更加有效地遮蔽流向半導體 鑄成相 _ 50之流動。 心%衩树月曰 (實施例6) 二8'圖為實施例6之半導體裝置心俯視圖。在第8 "’略鑄模樹脂5〇。在實施例6之半導體穿置1〇中 在半導體片30之一邊附近,與該 配中, 元件40及至少一户擬曰mi ^十订配置有複數個晶片 虛Μ日日片兀件46。在此,卢龆曰μ 一从 46係指對於半導體穿 隹此虛挺晶片π件 一从 衣置10之動作無用之元件。虛擬曰η :牛46可使用不與絕緣基材2〇上 : 40、或盥a Η 」Λ π < 日日片7G件 β + 同型之模型(m〇ck)等。晶片元株4η 及虛擬晶片元件46 ’号日日片兀件40 向。_由兮Μ & &又方向係朝向與行方向相同之方 +導體裝置的動作上,ί。構上或在 位置,或沒有必要將晶月-杜曰片几件40配設在期望 藉由在期望位晉蚀田:t兀40配設在期望位置時,也可 體片30之庐模行,广晶片元件46,確實遮蔽朝向半導 u之、拉树脂5〇之流動去路。 (半導體裝置之製造方法) 316778 14 200532871 準備絕緣基材,在絕緣基材設置導體電路 切出半導體片,將切出之半導體片黏著(m〇unt) 口上 !導==之電極墊與設於導體電路上之導㈣ 連接。在黏著於絕緣基材之半導體片的周邊設 一 由 _戶例6所不之任一配置的複數個晶片 凡件或虛擬晶片元件。 然後’以樹脂將半導體片及複數個晶 9圖表示半導體襄置10之封裝方法的順序。 ⑴將固恶鑄模樹脂片106設置於模具成型器⑽之容 m)iG4。將安裝有半導體片3g及晶片元件4g之絕緣 " 设置於模具成型器100之模槽102内。第10圖為 ^莫具成型器、100之模槽1〇2内設置實施例1之安裝有半 :體片3 G及晶片元件4 Q之絕緣基材2 Q時之俯視圖。在模 曰102内載置絕緣基材2(),俾使晶片元件μ之長度方向 垂直於經流動化之鑄模樹脂之流動方向。 返=第9圖,⑵在模具溫度為17〇至18〇。〇之條件 下的使“杈树脂片1〇6熔融,施加壓力,使其流入模具成 型為100内之流道(runner) 108。 ()將藉由杈具成型為100所注入之鑄模樹脂予以加 堅45至90秒,待鑄模樹脂熱硬化後,打開模具成型器 100,取出成型有鑄模樹脂之絕緣基材。 -、胃1此,在利用轉移鑄模法注入樹脂時,藉由將配設在 片30周邊附近之晶片元件4〇之長度方向垂直於樹 力方向,使晶片元件4〇更加有效地遮蔽樹脂之流 316778 15 .200532871 動。因此,可減低樹脂的壓力引起之金線接八一 • σ 〇 4 <損壞, 且可保持金線接合34於良好連接狀態。再者,樹脂之节動 方向與配設在半導體片30周邊附近之晶片元件4 = 足長度 方向所形成的角度最好垂直,但該角度並沒有必要嚴密地 垂直,只要該角度至少在垂直角度± 1〇度以内的角度^ 域,就可藉由晶片元件40之長度方向之側壁遮斷樹流 動,即屬於本發明之「垂直」之概念。 a 使用上述製造方法,製作上述實施例丨至實施例6中 φ各形態之半導體裝置後可確認,導線流動被抑制,且 接合之連接不良降低。 ~ 另外並確認,在晶片元件40尺寸為「1 005尺寸」、「〇6〇3 尺寸」及「0402尺寸」,鑄模樹脂50之厚度為晶片元件4〇 之2倍咼度以下時,抑制導線流動之效果顯著。 此外並確認’晶片元件4〇的尺寸並非一種,例如混合 「1005尺寸」和「〇603尺寸」配設有複數尺寸的晶片元件 40時,鑄模樹脂50的厚度係以在尺寸最大之晶片元件4〇 籲之2倍咼度以下時,抑制導線流動之效果顯著。 本發明不限於上述各實施形態,亦可根據業内人士之 知識對上述實施形態進行各種設計變更等變形,進行該種 變形之實施形態也屬於本發明之範圍。 再者,在上述實施例中,雖在絕緣基材上安裝有半導 體片及晶片元件,但本發明也適用於作為無心SIp(System in Package ;系統級封裝)而廣為所知之ISB(Integrated System in Board :註冊商標),該無心sip不使用具有由 16 316778 200532871 銅等形成之配線圖案且同時用以支持半導體片等之磁心。 【圖式簡單說明】 f1圖為實施例1之半導體裝置之俯視圖。 第2圖為沿第1圖之A—A線之剖視圖。 2 3圖為實施例2之半導體裝置之俯視圖。 f 4圖為實施例3之半導體裝置之俯視圖。 :5圖為實施例4之半導體裝置之俯視圖。 f 6圖為實施例5之半導體裝置之俯視圖。 弟7圖為表不貫施例5之本墓麟爿士 樹脂流動圖。 +泠肢衣置她曰封裝時之 第8圖為實施例6之半導體裝置之俯視圖。 之流。圖至第9C圖為表示半導體裝置之封裝方法順序 之安裝 苐10圖為在模呈点刑哭、β w 有半導成型為之模槽内設置實施例
r士 U 70件之絕緣基材時之俯視圖。 [主要元件符號說明】 20 30 34 42、44 50 102 106 絕緣基材 半導體片 金線接合 晶片元件列 鑄模樹脂 模槽 鑄模樹脂片 10 半導體裝置 22 導線電極 32 電極墊 晶片元件 46 虛擬晶片元件 100 模具成型器 1〇4 容器 流道 316778 17
Claims (1)
- 200532871 十、申請專利範圍: 1.-種樹脂封裝型半導體裝置,其特徵為包括有·· 絕緣基材,設置有導體電路; 半導體片’設置於前述絕緣基材 路以導線接合; j 月且兒 複數個晶片元件,安裝於前述絕緣基材上;以及 件,封衣⑽旨’封裝前述半導體片與前述複數個晶片元 其中,在注入前述封裝樹脂時,至 遮蔽前述樹脂對前述半導體片流動的位置,:置二: 複數個晶片元件。 *酉己置有則述 2· ^申圍第1項之樹脂㈣型半導體裝置,其 包圍:二/:片元件係將前述半導體片之四邊予以 ^圍則述複數個晶片元件之長度方向係朝向一定方 3· 專m請第1項之樹脂封裝型半導體裝置,其 1複數個晶片元件係將前述半 包圍,而對應於前述半導體片 透于以 列所包含之晶片元件的長度方向H而設置之晶片元件 片之各邊之方向。 朝向沿前述半導體 4.如申請專利範圍第丨 中,前以型半導體裝置’其 咬,!^ t 元件係沿前述絕緣基材之周緣部配 。又,别述複數個晶片元件之長度方向係 己 5·如申請專利範圍第丨項之樹 σ疋向。 貝树月曰封裝型半導體裝置,其 18 200532871 t,前述複數個S y - μ ^ ^ 曰曰片凡件係沿前述絕緣基材之周緣部配 :而對應於則述絕緣基材之各邊設置之晶片元件列中 之晶片元件的長度方向係朝向沿前述絕緣基材 之各邊之方向。 6·如申請專利範圍第1項之樹脂封裝型半導體裝置,立 :’由前_個晶片元件構成之2列以上晶片元件列 :配:於丽述半導體片之某一邊附近,且前述複數個晶 兀4之長度方向係朝向前述半導體片之某一邊方 > ^而各晶片元件列所包含之各晶片元件在晶片元件列 D之位置係與相鄰晶片元件列所包含之各晶片元 偏移成相互錯開。 7.如申」青專利範圍第i項之樹脂封裝型半導體裝置,其 中:刖述封裝樹脂之厚度為前述複數個晶片元件高度之 2倍以下。 &如申」青專利範圍第2項之樹脂封裝型半導體裝置,其 t,耵述封裝樹脂之厚度為前述複數個晶 ^ 2倍以下。 丁阿度之 9’如申凊專利範圍第3項之樹脂封裝型半導體裝置,| 中,耵述封裝樹脂之厚度為前述複數個 择、 2倍以下。 5兀件π度之 1 〇.如申睛專利範圍第4項之樹脂封裝型半導體裝置,其 中,前述封裝樹脂之厚度為前述複數個晶 /、 。 兀件呵度之 11.如申請專利範圍第5項之樹脂封裝型半導體裝置,其 316778 19 200532871 ‘ 巾&相4樹脂之厚度為冑述複數個晶片&件高度之 2倍以下。 12. 如專利_第6項之樹脂封裝料導體裝置,其 中別述封4樹脂之厚度為前述複數個晶片元 2倍以下。 13. 如申^專利範圍第丨項之樹脂封裝型半導體裝置,其 =月ί述封1樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 _ 14.如tjt專利範圍第2項之樹脂封裝型半導體裝置,其 I’前述封裝樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 15. 如申請專利範圍第3項之樹脂封裝型半導體裝置,其 I ’前述封裝樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 16. 如申請專利範圍第4項之樹脂封裝型半導體裝置,其 春 I,前述封裝樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 17. 如申請專利範圍第5項之樹脂封裝型半導體裝置,其 f ’前述封裝樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 18. 如申請專利範圍第6項之樹脂封裝型半導體裝置,其 :’前述封裝樹脂之厚度為前述複數個晶片元件中尺寸 最大之晶片元件高度之2倍以下。 19. 一種樹脂封裝型半導體裝置,其特徵為包括有: 316778 20 200532871 絕緣基材,設置有導體電路; 半導體片,設置於前述絕緣基材上,與前述導體電 路以導線接合; 衩數個晶片元件,安裝於前述絕緣基材上;以及 封裝樹脂,封裝前述半導體片與前述複數個晶片元 件, 其中’由前述複數個晶片元件構成之晶片元件列係配置於前述半導體片之某一邊附近,且前述複數個晶片 元件之長度方向係朝向前述半導體片之某一邊方向,而 在刚逃晶片元件列上係設置有虛擬晶片元件。 20.二種樹脂封裝型半導體裝置之製造方法’係藉由樹脂將 〇又,於°又有導體電路之絕緣基材上,且與前述導體電路 以:ί接合之半導體片;以及表面安裝型之複數個晶片 兀予以封裝之樹脂封裝型半導體裝置之製造 特徵為包括: 、乃沄其 ^ 疋置刖述複數個晶片 :件,俾使晶片元件之長度方向朝向前述-邊方向之步 :則述絕緣基材載置於模 複數個晶U件之長度方向 ^:之_’使前述 注入方向之步驟;以及、、*直於前述樹脂之 相對於則述半導體片與 述樹脂注入之步驟。 文數個日日片兀件,將前 3 ] (S7-7o 21
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JP2004088054A JP4429054B2 (ja) | 2004-03-24 | 2004-03-24 | 樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法 |
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JP2007294664A (ja) * | 2006-04-25 | 2007-11-08 | Pioneer Electronic Corp | 電子基板及びその製造方法 |
KR20140033245A (ko) * | 2006-05-24 | 2014-03-17 | 다이니폰 인사츠 가부시키가이샤 | 부품 내장 배선판, 부품 내장 배선판의 제조 방법 |
JP5067399B2 (ja) * | 2009-06-23 | 2012-11-07 | 株式会社デンソー | 電子装置の製造方法 |
DE102010063048A1 (de) * | 2010-12-14 | 2012-06-21 | Robert Bosch Gmbh | Verfahren zur Herstellung einer elektronischen Baugruppe mit Formkörper |
JP5668866B2 (ja) * | 2011-10-14 | 2015-02-12 | 株式会社村田製作所 | 部品内蔵樹脂基板 |
US9257412B2 (en) | 2012-09-12 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus |
JP6281506B2 (ja) * | 2015-02-24 | 2018-02-21 | トヨタ自動車株式会社 | 半導体モジュール |
US10325783B2 (en) * | 2015-06-09 | 2019-06-18 | Infineon Technologies Ag | Semiconductor device including structure to control underfill material flow |
CN110600432A (zh) * | 2019-05-27 | 2019-12-20 | 华为技术有限公司 | 一种封装结构及移动终端 |
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JPH04164352A (ja) * | 1990-10-29 | 1992-06-10 | Nec Corp | 混成集積回路装置 |
JPH0917912A (ja) | 1995-06-27 | 1997-01-17 | Rohm Co Ltd | 樹脂封止型半導体装置 |
JPH1131704A (ja) | 1997-07-10 | 1999-02-02 | Denso Corp | 半導体装置の製造方法 |
JPH11251344A (ja) | 1998-03-02 | 1999-09-17 | Hitachi Cable Ltd | ホールセンサの製造方法 |
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JP2001326238A (ja) * | 2000-05-17 | 2001-11-22 | Toshiba Corp | 半導体装置、半導体装置の製造方法、樹脂封止金型及び半導体製造システム |
JP3558595B2 (ja) * | 2000-12-22 | 2004-08-25 | 松下電器産業株式会社 | 半導体チップ,半導体チップ群及びマルチチップモジュール |
JP2003078077A (ja) | 2001-09-05 | 2003-03-14 | Sanyo Electric Co Ltd | カメラモジュール |
JP2003234364A (ja) | 2002-02-06 | 2003-08-22 | Hitachi Ltd | ワイヤ変形予測装置およびワイヤ変形予測方法 |
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