TW200532756A - Multi-chip package - Google Patents

Multi-chip package Download PDF

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Publication number
TW200532756A
TW200532756A TW094100815A TW94100815A TW200532756A TW 200532756 A TW200532756 A TW 200532756A TW 094100815 A TW094100815 A TW 094100815A TW 94100815 A TW94100815 A TW 94100815A TW 200532756 A TW200532756 A TW 200532756A
Authority
TW
Taiwan
Prior art keywords
pad
substrate
power
ground
semiconductor wafer
Prior art date
Application number
TW094100815A
Other languages
English (en)
Inventor
Ki-Myung Yoon
Heung-Kyu Kwon
Hee-Seok Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200532756A publication Critical patent/TW200532756A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
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    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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Description

20053¾ 九、發明說明： 曰本申睛案主張於2004年1月13號向韓國智慧財產局 提出申請之韓國專利申請案第10-2004-0002373號的優先 權’該專利申請案所揭露之内容係併入本案參考之。 【發明所屬之技術領域】 本發明是關於多晶片封裝，特別是關於其内之每一晶 片之間都插有間隙物（spacer)並呈垂直堆積之多晶片封 _ I ’此間隙物將會如被動元件(passive elements)般作用。 _ 【先前技術】 在可攜帶型電子設備的市場中，一個重要的挑戰為盡 可能地將許多元件封裝於設備當中。 有數種方法可用以完成較細、較小及/或較輕的元件， 晶片上系統(system-on_a-chip，SOC)技術可將許多個別的 元件整合於單一晶片中，而封裝内系統 (system-in-package，SIP)技術可將許多個別的元件整合於 單一封裝中。 • 封裝内系統技術類似於傳統的多晶片模組(multi-chip module，MCM)方法，可將許多矽晶片水平地或垂直地裝 配於單一封裝中。根據多晶片模組方法，可將許多矽晶片 裝配於水平方向。根據封裝内系統技術，可將晶片裝配於 垂直方向。 被動元件如電阻(resistors)、電容器（capacitors)及/或感 應器（inductors)，會在考慮眾多堆積晶片及/或降低能量輸 入雜訊等特性的情況下而排列及/或裝配於系統板上。 200532756 15682pif.doc 電容杰之感應度（inductance)可由測量整合於每一晶 片=之其他與電容器接近的元件而得。將電容器靠近整合 於母曰曰片中之其他元件時感應度會降低。在封裝内系統 技術中，許多晶片會呈垂直堆積，在上層及下層晶片間之 間隙物可提供空間以進行焊線接合(wire b〇nding)。 由於這些方法提供了電容器及間隙物，故會限制了多 晶片封裝體積的縮減。 I 【發明内容】 、本發明提供了一個多晶片封裝，可增加電氣特性，並 /或在維持焊線接合穩定度的情況下縮減封裝體積。 夕本奄月的較佳貝施例可提供一個包括基板(substrate) 之多晶片封裝。至少包括動力墊(p〇wer)及接地墊(gr〇und PadS)之許多的基板接合墊(substrate bonding pads)會形成 =基板之上，且有許多端子(terminals)會形成於基板下方。 第半導體晶片（flrst semiconductor chip)會形成於基板上 並具有至少包括動力墊及接地墊之許多墊。間隙物會形成 • 於第^半導體晶片上並至少有-個至少具有動力墊及接地 墊之被動it件會形成於間隙物上。第二半導體晶片（sec〇nd semiconductor chip)會形成於間隙物上並具至少包括動力 塾及接地墊之許多墊。這許多墊可使第一半導體晶片及第 二半導體晶片、間隙物之動力墊及接地墊與基板接合墊之 動力墊及接地墊達到電氣連接的作用。 曰本發明的其他杈佳實施例為提供一個包括基板之多 晶片封裝。至少包括動力墊及接地墊之許多的基板接合墊 200532756 15682pif.doc 會形成於基板上，且有許多端子會形成於基板下方。第一 半導體晶月會形成於基板上並具有至少包括動力墊及接地 墊之許多墊。間隙物會形成於第一半導體晶片上，且至少 有-個至少具動力墊及接地墊之被動元件會形成於間隙物 上。此被動元件在兩者互相垂直的第一方向及第二方向至 少其中之一，會較第一半導體晶片為長。第二半導體晶片 會形成於_物上並具有至少包㈣力墊及接地墊之許多 墊這絝夕墊會使第一半導體晶片及第二半導體晶片、間 隙物之動力墊及接地墊與基板接合墊之動力墊及接地塾達 到電氣連接的作用。 一第二，導體晶片在第一方向有一長度，而在垂直於第 二方向上有另一長度。第二半導體晶片會在間 物為短弟一方向及第二方向至少其中之一的長度上較間隙 用之間除物的動力及將如電谷器的電極般作
曰本發明的其他較佳實施例可提供一個包括A ;:二=括動力塾及接地塾之許多的基^反接合i —半有許多端子會形成於基板下方。第 塾之許具至少包括動力墊及接地 -個至少且右=會形成於弟一半導體晶片上並至少有 上。至少在塾及接地塾之被動元件會形成於間隙物 半導體晶片、第二半導體晶片及間隙物之 200532756 15682pif.doc 中-者的選擇為要使每一個所選擇的第 二半導體晶片及間隙物在第—方向 ^片、第 之-的長度大於、等於或小於未自此以=少其中 第二半導體晶片會形成於間隙物 ^者。 動力墊及接地墊之許多墊。使得第少包括 ¥體曰曰片、間隙物之動力墊及接地墊 2 墊及接地墊達到電氣連接的作用。 口墊之動力 間隙物是由石夕所形成的，並具80〜120 _之 隙物中之被動元件包括電容器以及 t = 用之間隙物的動力墊及接地墊。 電合-的電極般作 本發明的其他較佳實施例可提供—種製造多晶 ^支術，包括在基板上方形成之包括動力塾及接地塾之^ 夕的基板接合墊、在基板下方形成之許多端子上、至 括動力墊及接地塾之許多塾會形成於第一半導體晶片上、 一個ΐ少具動力墊及接地墊之被動元件會形成於間 、主心至〉、包括動力墊及接地墊之許錄墊會形成於第
Lti片上。第一半導體晶片、第二半導體晶片、間 隙物衣配於基板上且/或與基板達到電氣連接的作用，且至 (第半導體晶片、第二半導體晶片及間隙物之中二者的 選擇為要使每-個所選擇的第一半導體晶片、第二半導體 晶片及間隙物在第-方向及第二方向至少其中之一的長度 大於、等於或小於未自此族群中所選擇者。第一及第二方 向是彼此垂直的。 8 2005職
f實施方式J 為讓本發明之特徵及優點能更明顯易懂，下 較佳實施例，並配合所附圖式，作詳細說明如下。雖然: =明佳實施例揭露於下文，然其並非用以限定本發 各可作此技勢者，在不脫離本發明之精神和範圍内， 加明二:):層更:c::nr及位置會減少或增 會被認為是形成Ϊ另:案化覆蓋參考層時， 根據本發明的較佳實施例;： 圖3以得卿細的描述。 4封裝可參考圖！至 麥考圖1至圖3，在本發明的 片20裝配於基板1〇上，在勺^土貫施例中’第—晶 η、口及13，在基板之下方;:成=基板接合墊 基板接合墊11會連接至第—:夕缒子15。 會連接至間隙物30，Β9片2G，基板接合墊U 片40。 基板接合墊^則會連接至第二晶 會較f:=。—4片20上的間隙物3。，在第-方向上 為短。第一方向及第二方向二:方垂向==? 會接附在間隙物3G上的第二日μ方向及水平方向。 上較間隙物3G為短，而在水^ 4G’會在垂直方向 1向會較間隙物30為長。 200532756 15682pif.doc 間隙物30是由矽所形成的。許多隔離墊31會在間隙 物30上形成，而隔離墊31會大到足以進行雙重焊線接合 (double wire-bonded) 〇 第一晶片20及第二晶片40為邊緣墊形式晶片（edge pad type chips)。晶片墊(chip pad)21會形成於第一晶片2〇 的兩個相對角落上，且晶片墊41及42會沿著第二晶片4〇 的四邊而形成。在第一晶片20及第二晶片4〇表面上形成 晶片塾2卜41及42的表面是為活性表面(active surfaces)， 而其活性表面的相反面為無活性表面（inactiVe surfaces)，第 一晶片20及第二晶片40之活性表面會朝向相同方向。第 一晶片20及第二晶片40的非活性表面可用以接合第一晶 片20及第二晶片40與多晶片封裝中的其他元件。第一晶 片20、第二晶片40及/或間隙物3〇可使用絕緣粘合劑 (dielectric adhesive)來相互接合。 間隙物30包括了裝配於其中的被動元件，以及會如 同動力墊及/或接地墊般地作用，提供動力電壓（p〇wer _ V〇ltage)及接地電壓（ground voltage)給被動元件之隔離墊 31中的部份或全部，此被動元件可為電容界。 —可如動力墊及/或接地墊般作用之隔離墊31，將如電 容器的電極般地作用’而由销形成之間隙物3 q的部份將 Γη包t隔離墊31 ’將如電容器的絕緣層般地作用。間隙物 3〇之厚度為80〜200 μηι。 200532756 卜每一個隔離墊31都可達到電氣連接的作用，以使得 第一晶片40的晶片墊42可經由隔離墊31而與第二基板接 合墊12達到電氣連接的作用。 第二晶片40的動力墊及/或接地墊會經由隔離墊31 的動力墊及/或接地墊而與第二基板接合墊12連接，可增 加多晶片封裝的電氣特性，例如感應性。 曰
第一晶片20的晶片墊21可使用第一接合線(fim bonding wire)5i而與第一基板接合墊u達到電氣連接的 作用。第一接合線51線圈的高度取決於第一晶片2〇及第 二晶片40之間的間隙物30的高度。第二晶片4〇上的晶片 墊41可使用第二接合線52而與第三基板接合墊13彼此 到電氣連接的作用。 $ 第二晶片40的晶片墊42會經由隔離墊31其中之一 使用第三接合線53及/或第四接合線54而與第二基板接人 墊12彼此達到電氣連接的作用。 σ 在本發_較佳實_之中，晶μ 42會經由隔離 墊31其中之一而與第二基板接合墊12彼此達到電氣連接 的作用。晶片墊42可使用單-接合線而與第二基板接合塾 彼此連接(例如直接連接）。 如動力墊及/或接地墊般作用之隔離墊31，可與第一 用或第二晶片4〇的動力塾及/或^ 第一 曰曰 52、53、54 片20、第二晶片40、間隙物3〇、接合線、 以及其中的連接部份都會被包含(例如封裝)於
封裝體(paCkingb〇dy)60中。焊接球⑽der_7〇會如外 部端點(e血nal node)般接附於基板1〇下方的每一個端子 15上。¥接球7G會經由在基板1Q所形成的電路交聯 (imerc〇nnecti〇n)(未展示）和第—至第三基板接合墊 11 〜13 連接’而與第一晶片20、間隙物3〇及第二晶片4〇達到電 氣連接的作用。 根據本發明較佳實施例之多晶片封裝，間隙物3〇會
如被動元件般作用。可藉由間隙物3〇使第二晶月4〇及第 -基板接合墊12進行料接合以增加焊線接合的穩定性。 在本發明的其他較佳實施例中，可參考圖4及圖5， 第一晶片20裝配於基板1G之上，會形成許多基板接合塾 於基=上，以及許多端子15會形成於基板下方。 見度及/或長度小於第一晶片2〇之間隙物3 第一晶片20上。 曰牧订％ 片40會接附於 寬度及/或長度小於間隙物30之第二晶 間隙物30上。
—S曰片4〇在垂直方向及/或水平方向可較間隙物30 長，顯示於圖12至圖14。
間隙物30是由石夕所形成的，且在間隙物3〇上 許多隔離墊31。隔離墊31為雙重焊線接合。 曰V 第曰曰片20及第二晶月40為邊緣墊形式晶片。曰 墊21及晶片㈣會沿著第一晶片2〇的四邊而形成曰晶 片墊41則會沿著第二晶片4()的四邊而形成。第—^ 的曰曰片墊22會大於晶片墊21，以進行雙重焊線接合。 200532756 15682pif.doc 在第一晶片20及第二晶片4〇上，形成晶片墊21及 22(或晶片墊41)之表面是為活性表面，而第一晶片2〇及第 二晶片40上其餘的表面是為非活性表面。第一晶片2〇及 第二晶片40之活性表面會朝向相同的方向。第一晶片2〇 及第二晶片40之非活性表面可用以接合第一晶片2〇及第 =晶片40與多晶片封裝中的其他元件。第一晶片2〇及間 隙物30可使用絕緣黏合劑來彼此接合，且間隙物30及第 二晶片40也可使用絕緣黏合劑來彼此接合。 間隙物30包括了被動元件，以及會如同動力墊及/或 接地墊般作用，以提供動力電壓及接地電壓給被動元件之 隔離墊31中的部份或全部，此被動元件可為電容器。 可如動力墊及/或接地墊般作用之隔離墊31，可如電 ^器的電極般地作用，由矽所形成之間隙物3〇，不包括隔 離墊31，其將如電容器的絕緣層般地作用。間隙物3〇之 厚度為80〜200 μηι。 每個隔離墊31都可提供電氣連接以使得第二晶片4〇 的晶片墊4!可與第二基板接合墊η達到電氣連接的作 用第一曰曰片40的動力墊及/或接地墊會經由隔離墊Η的 動力墊及/或接地墊而與第二基板接合墊12連接，可增加 夕日日片封I的電氣特性，例如感應性。 一第一晶片的晶片墊21及22可使用第一接合線51而 與第一基板接合墊11達到電氣連接的作用。 13 200532756 隔離墊31可經由第一晶片20之晶片墊22使用第一 接合線51及/或第二接合線52，而與第一基板接合墊11 達到電氣連接的作用。 第二晶片40之晶片墊41可分別經由隔離墊31及第 一晶片20之晶片墊22使用第一接合線51、第二接合線52 及第三接合線53，而與第一基板接合墊11達到電氣連接 的作用。在較佳實施例中，第二晶片40之晶片墊41可經 由隔離墊31及/或第一晶片2〇之晶片墊22而與第一基板 接合墊11達到電氣連接的作用。第二晶片4〇之晶片墊41 會經由隔離墊31或第一晶片20之晶片墊22而與第一基板 接合墊11達到電氣連接的作用。第二晶片40之晶片墊41 也會與第一基板接合墊11連接。 一可如動力墊及/或接地墊般作用之隔離墊3】，合盥第 :二ΐ或第二晶片40之動力墊及/或接地墊i到電 52 . 53 ^ 3〇 > 51 . 封裝體60中。悍接球1 會被包含(例如封震)於 下方的每1端子15上;°外部端點般接附於基板10 成的電路交聯(未展示)和第，球70會經由在基板1〇所形 接，而與第〜晶 弟三基板接合墊η〜 連接的作用。 間隙物30及第二晶片4〇達到電^ 穩定性 t間隙物30會如被動 之 凡件般作用，以增加焊線接合 14 200532756 15682pif.doc 在本發明之其他較佳實施例中，可參考圖6至圖8， 第一晶片20裝配於基板1〇上，會形成許多基板接合墊於 基板上，以及許多端子15會形成於基板下方。 第一基板接合墊11會在垂直方向形成，且/或第二基 板接合墊12會在水平方向形成。 間隙物30會接附於第一晶片2〇上。間隙物3〇在垂
直方向會較第為長，而在水平方向則會較第一晶 片20為短。 於間寬度較間隙物30為短之第二晶片40會形成 離32^ 3〇疋由石夕所形成的。第—隔離墊31及第二隔 i隹2會形成於間隙㈣之上。第-隔離墊3 i會在垂直= 3°1及離墊32會在水平方向上形成。隔離墊 及^離墊32可進行雙重焊線接合。 及42二：第二的兩個相對角落上，且晶片塾41 重焊線接合。 ^成。曰曰片墊21可進行雙 一面=二= -晶心:;=:=_向。第 …第二晶片40與多晶片封;合;:ί 200532756 15682pif.doc 二3及，物30可使用絕緣黏合劑來彼此接合，且間隙 及乐二晶片40可使用絕緣黏合劑來彼此接合。 描徂Γ1+、物3G包括—被動元件’以及可作為對被動元件 或對地電壓之動力墊及/或接地墊之隔離 2。此被動元件可為電容器。 六可作為動力墊及/或接地墊之隔離墊31及32，將如電 二。之電極般作用，而不包括隔離墊31及”之部 =是由销形成，將會如電容器之絕緣層 隙 物3〇之厚度為80〜2〇〇μιη。 盘笛I们^離塾31及32都可與經由隔離墊31及32而 i楚板接合墊11及第二基板接合塾12進行封線接合 使ΐ 晶片墊41及42達到電氣連接的作用。以 7曰曰片的晶片墊41及42與第一基板接合墊11 第了基板接合墊12達到電氣連接的作用。 第^晶片40的動力墊及/或接地塾可經由每一隔離塾 、、之動力塾及/或接地墊而與第-基板接合塾11連 妾’ t增加多晶片封聚之電氣特性，如感應性。 笛—f 一晶片2G之晶片墊21可使用第-接合線51而盘 弟-基板接合墊11達到電氣連接的作用。 ” _第一隔離墊31可經由第-晶片20之晶片墊21使用 接合線51及第二接合線52來與第—基板接合塾^ 達到電氣連接的作用。 16 200532756 15682pif.doc 在第—晶片4〇上之晶片離4 I第一 π > /可分別經由第一 31及第-晶片2。之晶片墊： 51〜53’而與第一基板接合 用弟至弟二接“泉 第二_2可使用第四接4:線電=作=接 合墊12達到電氣連接的作用/ °線54而與第二基板接 第二晶片20上之晶片執40 _
用第四接合線54及第五接人線55 ^由第二隔離墊32使 達到電氣連接的作用。相而與第二基板接合墊12 片2〇ΓΓ-動日力Η墊及/或接轉之隔離塾31，會與第一晶 作用 之動力墊及/或接地墊達到電氣連接的 52、ί片2G、第二晶片4G、間隙物3G、接合線5:1、 3、54、55以及其中的連接部份都會被包含(例如封 裝體=中。焊接球7G會如外部端點般接附於基板 所^ 2二個端子15上。焊接球7〇會經由在基板10 >成的電路父聯（未展示）和第一至第三基板接人 〜;3連接，而與第一晶片2〇、間隙物3〇及第二晶片、 嚷則電氣連接的作用。 ^本發明之其他較佳實施例中，可參考圖9A至圖 〜第一晶片20之非活性表面在基板10上是固定的。第 W至第三基板接合墊11〜13會形成於基板10之上，且許多 15 ^ ^/成於基板1 〇之下方’可使用如環氧基 p〇Xy)、絕緣膠帶(dielectric tape)之類的粘合劑。 17 200532756 15682pif.doc 可使用第-接合線51如金線等來完成最初的焊線接 a ’使得“墊21可與基板1G上之第―基板接 達到電氣連接的作用。 5圖，至圖1GC，可使用钻合劑來接合間隙物如 及弟-4 2G’以使得_物％在垂直方向上一曰 片20為長且/或在水平方向上較第一晶片2〇為短。曰曰 -芩考m、目ιΐΑ及圖11B，可使用丰占合劑來接合 7片4〇及間隙物30 ’以使得第二晶片40在水平方向上 車父間隙物3 0為長且/或在垂直方向上較間隙物3 〇為短。 接合可使用第二至第四接合線52〜54來完成第二次的焊線 來4第二 片墊41可使用第二接合線52 i接=㈣進行封線接合.以使彼此達到電氣 在第二晶片4〇上之晶片墊42可使用 :與隔離塾31進行封線接合，以使彼此達到電 第-基板接口塾12可使用第四接合 31進行封祕合，叫彳__氣連接的作t 如圖2及圖3所示，封梦 /用 r，等製造’以使得第二由如5魏樹脂(W 1接合線51〜54^复=°:第二晶片40、間隙物 面。焊接球70會如外部端=伤都被包括(或封裝)在裡 丨而點般接附於端子15上。 "多的多晶片封裝是以批次方式製造並各自分離的。 200532756 15682pif.doc 步成itr發明之較佳實施例中可得知，基板接合塾會 瞭解才且許多端子會形成於基板下方，但必須要 精神和範圍 内二此墊及端子是可視 雙重^财可壯，祕塾可進行 圍内’此隔離神和範 雖然本發明可胁杜一 人之職接合。 式作詳細說日i，彳並配合所附圖 藝者，在兀盼咕4·々非用限疋本發明，任何熟悉此技 動與潤#，r/之精神和範圍内’當可作些許之更 _界定者本發明之_範圍當視後附之申請專利範 間隙：ϊί::二多=' 用’增加焊線接合·61隙物的作用如被動元件般作 【圖式簡單說日^疑’及/或多晶片封裝之電氣特性。 圖。圖1為根據本發明的較佳實施例之多晶片封震之平面 圖2為圖1之水平剖面圖。 圖3為圖1之垂直剖面圖。 平面Γ為根據本發明的其他較佳實施例之多晶片封襄之 圖5為圖4之剖面圖。 2〇〇53275£ 圖6為根據本發明的其他較佳實施例之多晶片封裝之 平面圖。 圖7為圖6之水平剖面圖。 圖8為圖6之垂直剖面圖。 圖9A、圖9B及圖9C分別為根據本發明的其他較佳 實施例之多晶片封裝來說明製造方法部份之平面圖、水平 剖面圖及垂直剖面圖。 圖10A、圖10B及圖10C分別為根據本發明的其他較 ® 佳實施例之多晶片封裝來說明製造方法其他部份之平面 圖、水平别面圖及垂直剖面圖。 圖11A及11B分別為根據本發明的其他較佳實施例之 多晶片封裝說明製造方法其他部份之平面圖、水平剖面圖 及垂直刹面圖。 圖12為根據本發明的其他較佳實施例之多晶片封裝 所變化之平面圖。 圖13為圖12多晶片封裝之水平剖面圖。 • 圖14為圖12多晶片封裝之垂直剖面圖。 【主要元件符號說明】 10 :基板 11 :第一基板接合墊 12 :第二基板接合墊 13 :第三基板接合墊 15 :端子 20 :第一晶片 20 200532756 15682pif.doc 21 :晶片墊 22 :晶片墊 30 :間隙物 31 ··第一隔離墊 32 ··第二隔離墊 40 :第二晶片 41 :晶片墊 42 :晶片墊 51 :第一接合線 52 :第二接合線 53 :第三接合線 54 ··第四接合線 55 :第五接合線 60 :封裝體 70 :焊接球
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Claims (1)

  1. 200532756 15682pif.doc 十、申請專利範圍： h 一個多晶片封裝，包括： 夕 個基板，在其上形成至少包括動力墊及接地墊之气 多基板接合墊，且有許多端子形成於基板下方； 。 一個第一半導體晶片，形成於基板上並具有至少包括 動力墊及接地墊之許多基板接合墊； 一個間隙物，形成於第一半導體晶片上，至少具有一 個至少具動力墊及接地墊形成於其上之被動元件； 一個第二半導體晶片，形成於間隙物上並具有至少包 括動力墊及接地墊之許多基板接合墊；以及 其中第一及第二半導體晶片、間隙物之動力墊及接地 墊與基板接合墊之動力墊及接地墊達到電氣連接的作用。 2· —個多晶片封裝，包括： 一個基板，在其上形成至少包括動力墊及接地墊之許 多基板接合墊，且有許多端子形成於其下方； 一個第一半導體晶片，形成於基板上並具有至少包括 動力墊及接地墊之許多基板接合墊； 一個間隙物，形成於第一半導體晶片上，至少有一個 至少具動力墊及接地墊形成於其上之被動元件，此被動元 件至少在第-方向及第二方向兩者其中之—的長度，較第 一半導體晶片為長’第-方向及第二方向此兩者是互相垂 直的； 一個第二半導體晶片，形成於間隙物上並具有至少包 括動力墊及接地墊之許多基板接合墊；以及 夕匕 22 200532756 其中第-半導體晶片及第二半導體晶片、間隙物 力墊及接地墊與基板接合墊之動力墊及接地墊 接的作用。 』电乳運 3·如申請專利範圍第2項所述之多晶片封裝， 二ΐ導體晶片在第-方向上有m在垂直於第：：= 之弟二方向上有另一長度，且至少在第一方 三 兩者其中之-的長度較間隙物為短。 弟—方向 1 專利範圍第3項所述之多晶片封裝，其t第 -+導體4之動力纽接地墊經 f 地塾而與基板之動力塾及接地塾達到電氣連接^，及接 二半導專利範圍第4項所述之多晶片封裝，其中第 地整以由間隙物之動力塾及接 力塾及接地4:=::::及接地㈣與基板之動 6·如申請專利範圍第5 隙物是由石夕所形成並具8〇〜12〇陣之=片襄，其中間 少一被動元件包括電容器，以及將如電^ ^物中之至 之隔離物的動力墊及接地墊。 °。勺電極般作用 焊線=申請專利範圍第6項所述之多晶片封夺，m 知線接合而達到電氣連接的仙。 于衣其中由 8.如申請專利範圍第7 一半導體晶片、第-半㈣曰H =曰曰片封裝，其中第 份都是被封裝的 片、間隙物及其中之連接部 23 200532¾ -本实興^專视圍弟項所述之多晶片封裝，苴中第 達到電氣連接的作用。 -基板之動力塾及接地墊 隙物^，專利範圍第9項所述之多晶片封裝，其中間 少一ί動成並具80〜12,之厚度’間隙物中之至 之間隙物的動力墊及接地塾。 的电極般作用 由^^請專利㈣第1G項所叙多晶片封裝，里中 予、、友接5而達到電氣連接的作用。 部份都是的弟二半導體晶片、間隙物及其中之連接 二半i3體如曰申Λ專利範圍第3項所述之多晶片封裳，其中第 曰曰片至少會在間隙物的第一方向及第二方向苴中 之的長度較間隙物為短。 八 第二專利範圍第13項所述之多晶片封裝，其中 技从勒體曰曰片之動力墊及接地墊經由間隙物之動力墊及 而與基板之動力墊及接地墊達到電氣連接的作用。 第一 15^\申請專利範圍第14項所述之多晶片封裝，其中 j —半導體晶片之動力墊及接地墊經由間隙物之 力—半導體晶片之動力塾及接地塾而與基板之動 力塾及接地墊達到電氣連接的作用。 ,、16g如申凊專利範圍第15項所述之多晶片封裝，其中 曰隙物是由矽所形成並具80〜120 μιη之厚度，間隙物/中之 24 200532Z56 至少-被動元件包括電容器， 用之間隙物的動力墊及接地墊。^ 電極㈣ 由π H申請專補㈣16項所述之多“封裝，並中 友接s而達到電氣連接的作用。 部份都是被:ί的導體晶片、間隙物及其中之連接 第-Γ=α申請專利範圍帛14項所述之多晶片封裝，盆中 整達到電塾及接地塾與基板之動力塾及接地 間隙^7 f專利範圍第19項所述之多晶片封裳，其中 至少矽所形成並具80〜120卿之厚度，間隙物中之 用之間;:::==及將如電容器的電極般作 _===述之_封裝… 第42= 專利範圍第21項所述之多晶片封裳，其中 部份都是㈡的第二半導體晶片、間隙物及其— 23·—個多晶片封裝，包括： 多基== 反’在其上形成至少包括動力塾及純墊之許 動力塾======基板上並具有至少包括 妾a整’且有許多端子形成於基板下方· ‘之許多基板接合墊 25 200532756 15682pif.doc 一個間隙物，形成於第一半導體晶片上，至少有一個 至少具動力墊及接地墊形成於其上之被動元件，此至少一 個被動元件至少在第一方向及第二方向任何之一較第一半 導體晶片為短，第一方向及第二方向兩者是相互垂直的， 一個第二半導體晶片，形成於間隙物上且具有至少包 括動力墊及接地墊之許多基板接合墊；以及 其中第一半導體晶片及第二半導體晶片、間隙物之動
    力墊及接地墊與基板接合墊之動力墊及接地墊達到電氣連 接的作用。 24·如申請專利範圍第23項所述之多晶片封裝，其中 第二半導體晶片在第一方向有一長度而在垂直於第一方向 之第二方向上有另一長度，至少在第一方向及第二方向兩 者其中之一的長度較間隙物為短。 々如申請專利範圍第24項所述之多晶片封裝，其中 第一半導體晶片之動力墊及接地墊經由間隙物之動力墊及 接地墊而與基板之動力墊及接地墊達到電氣連接的作用。 第二26:如申請專利範圍第25項所述之多晶片封裝，其中 拉導體晶片之動力墊及接地墊經由間隙物之動力墊及 Λ執及第一半導體晶片之動力墊及接地墊而與基板之動 墊及接地墊達到電氣連接的作用。 間二7二專:圍二2:項所狀⑻縣，其中 至少一被_Γ=^Γ120;：之^，間隙物中之 用之間隙物的動力墊及接^墊二，如⑨^的電極般作 26 200532756 15682pif.doc 28·如申請專利範圍第27項所述之多晶片封裝，其中 由焊線接合而達到電氣連接的作用。 29·如申請專利範圍第28項所述之多晶片封裝，其中 第一半導體晶片、第二半導體晶片、間隙物及其中之連接 部份都是被封裝的。 30· —個多晶片封裝，包括：
    一個基板’在其上形成至少包括動力墊及接地墊之許 多基板接合墊，且有許多端子形成於基板下方； 一個第一半導體晶月，形成於基板上並具有至少包括 動力墊及接地墊之許多基板接合墊； 一個間隙物，形成於第一半導體晶片上，至少有一個 至少具動力墊及接地墊形成於其上之被動元件；以及 一個第二半導體晶片，具有至少包括動力墊及接地墊 之許多基板接合墊；其中 第一半導體晶片、第二半導體晶片及間隙物都置於基 板上’ 第一半導體晶片、第二半導體晶片及間隙物之動力塾 及接地墊與基板接合狄動力钱舰墊_職連接的 作用，以及 至少弟一半導體晶片、第二半導體晶片及間隙物的力 群之中選擇二者使其至少在第—方向及第二方向二者其^ 之-的長度大於、小於或等於此族群中未被選擇者。 31·—種多晶片封裝方法，包括： 27 200532756 15682pif.doc 於基板上形成許多至少包括動力墊及接地墊的基板 接合墊，且有許多端子形成於基板下方； 形成至少包括動力墊及接地墊之許多基板接合墊於 第一半導體晶片上； ^ 形成至少一個至少包括動力墊及接地墊於間隙物上 之被動元件； 形成至少包括動力墊及接地墊形成於其上之許多美 板接合墊於第二半導體晶片上； 將第-半導體晶片、第二半導體晶片及間隙物置於 板之上；以及 第-半導體晶片、第二半導體晶片及間隙物之動力 及接地墊與魏接合墊之動力墊及祕㈣ 作用；其中 W 至少第一半導體晶片、第-主 + +導體晶片及間隙物的族 群之中=一者使其至少在第一方向及第二方 之-的長度大於、小於或等於自此_中未被選擇者。、 28
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