TW200522295A - Semiconductor package with flip chip on leadframe - Google Patents

Semiconductor package with flip chip on leadframe Download PDF

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Publication number
TW200522295A
TW200522295A TW092136315A TW92136315A TW200522295A TW 200522295 A TW200522295 A TW 200522295A TW 092136315 A TW092136315 A TW 092136315A TW 92136315 A TW92136315 A TW 92136315A TW 200522295 A TW200522295 A TW 200522295A
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TW
Taiwan
Prior art keywords
chip
pins
scope
item
package structure
Prior art date
Application number
TW092136315A
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English (en)
Other versions
TWI317991B (en
Inventor
Chien Liu
Hsueh-Te Wang
Meng-Jen Wang
Chi-Hao Chiu
Tai-Yuan Huang
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092136315A priority Critical patent/TWI317991B/zh
Priority to US11/014,165 priority patent/US7253508B2/en
Publication of TW200522295A publication Critical patent/TW200522295A/zh
Application granted granted Critical
Publication of TWI317991B publication Critical patent/TWI317991B/zh

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

200522295 五、發明說明（1) 發明所屬之技術領域 一括m係有關於一種半導體封裝結構，特別係有關於 一種導線架上覆晶半導體封裝結構。 【先前技術】 半導體封裝結構依客戶端需求有各種之封裝型 ，其中一種係為「覆晶在導線架上」〔Fiip chip 〇n I^eadframe〕，即將一覆晶晶片以在其主動面之複數個凸 導線架之複數個引腳上’❿不需要以打線之銲 ::電性連接’然而供覆晶接合之導線架係略有不同習知 Ϊ ΐί丄供覆晶接合之導線架係在該些引腳之上表面内端 形成適虽之凸塊接合區，以對應於該晶片之該些凸·塊以 防止該晶片之凸塊在銲接時濕潤至該些引腳之其它部位。 一我國專利第463342號〔其美國專利案號為65〇712〇〕 揭不有一種「覆晶式四方扁平無接腳構裝」，主要包含 複數個接腳、一以複數個凸塊接合在該些接腳之晶片以及 一包覆該些接腳與該晶片之封膠材料，其中，該些接腳之 上表面形成有一防銲層〔solder mask layer，即俗稱之 綠漆〕，且該防銲層係具有開口，對應於該些凸塊連接的 位f，以限制該晶片之凸塊在該些接腳之濕潤接合面積， 但是習知防銲層係以印刷方式形成於一基板或印刷電路 板，防銲層在線路之間可被基板之樹脂層承載，若將防銲 層印刷在導線架之接腳上表面，該些接腳之厚度遠高於習 知基板之線路層’且因在該些接腳下並無支撐層，因此使 得形成防銲層時困難及易導致導線架與機台污染，此外，
200522295
五、發明說明（2) 該覆晶式四方扁平益技胞；祕壯Μ , rr，. Q , n十…、接腳構裝僅能適用晶片尺寸封裝 (Chip Scale Package rep „ a — *从 丄 g ’ CSP〕 ’即該些接腳相當地短， i $彳# & μ妯& 十往外延伸時，該些接腳之 長度僅旎延伸到一定之县许 -^ ^ 又且由於該些接腳不具有可與 兮射膜絲:4丨=口之結構设計，因此愈長的接腳愈容易與 且其相鄰之接腳容易造成短路接觸。 【發明内容】 本發明之 體封裝結構， 銲凹陷部〔S 0 銲凹陷部係鄰 可供一封膠體 散，而省略習 充於該些阻銲 本發明之 體封裝結構， C solder-res 部之截面以倒 複數個凸塊在 片之該些凸塊 主要目的係在 利用複數個引 lder-resist 接該些引腳上 填充，使得覆 知在導線架上 凹陷部而使該 次一目的係在 利用在導線架 i s t concave 「Ω」形為佳 該些引腳之凸 在銲接時對該 於提供一種導線架上覆晶半導 腳之上表面係形成有複數個阻 concave portion〕，該些阻 表面内端之凸塊接合區，其並 晶晶片之凸塊不致過度潤溼擴 防銲層構件，並因該封膠體填 些引腳内端具有穩固之功效。 於提供一種導線架上覆晶半導 引腳之上表面的阻銲凹陷部 port ion〕，且該些阻銲凹陷 ，其係用以有效限制一晶片之 塊接合區内銲著，並防止該晶 些引腳之產生過度擴散覆蓋。 本發明之再一目的係在於提供一種導線架上覆晶半導 體封裝結構，利用複數個引腳之下表面形成有複數個卡掣 孔〔locking hole〕，以供一封膠體填覆，該些引腳之下 表面在該些卡掣孔之内端與外端分別形成有共平面之支撑 200522295 五、發明說明（3) 區與外接區 定。 本發明 結構之導線 阻銲凹陷部 阻銲凹陷部 佳地，該些 制一晶片之 可供一封膠 塊不致過度 在導線架上 依本發 包含有由一 體，每一引 之上表面内 表面外端係 式設於該些 該些引腳之 腳，而該些 引腳之上表 部係鄰接該 些阻銲凹陷 可形成有一 成有複數個 ’使得南度延伸之引腳能確實被該封膠體所固 之另一目的係在於提供一種 架’利用複數個引腳之上表 C solder-resist concave 係鄰接該些引腳上表面内端 阻銲凹陷部之截面係為倒「 複數個凸塊在該些引腳之凸 體填充該些阻銲凹陷部中， /閏渥擴散至該些引腳之其它 防鲜層構件。 明之導線架上覆晶半導體封 導線架形成之複數個引腳、 腳係具有一上表面及一下表 端係形成有複數個凸塊接合 形成有複數個外接區，該晶 引腳之上表面，該晶片之凸 凸塊接合區，該封膠體係包 引腳之外接區係顯露於該封 面係形成有複數個阻銲凹陷 些凸塊接合區並填充有該封 部係具有倒「Ω」形截面， 上升區〔upset area〕或在 卡擎孔〔locking hole 〕， 覆晶式半導體封裝 面係形成有複數個 portion 〕，該些 之凸塊接合區，較 Ω」形，以有效限 塊接合區熔銲，並 使得覆晶晶片之凸 部位，而省略習知 裝結構，其係主要 一晶片及一封膠 面，其中 區’該些 片係以覆 塊係接合 覆該晶片 膠體，其 部，該些 膠體，較 此外，該 其下表面 以增進該 該些引腳 引腳之下 晶接合方 該晶片與 與該些引 中，該些 阻銲凹陷 佳地，該 些引腳係 之中段形 些引腳在
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【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 請參閱第1圖，依據本發明之第一具體實施例，一種 導線架上覆晶半導體封裝結構丨〇 〇係主要包含有複數個引 腳1 1 0、一晶片1 2 0及一封膠體1 3 0，該些引腳1 1 〇係由一如 銅、鐵或其合金之導線架所形成，例如四方扁平無外接腳 〔Quad Flat Non-leaded, QFN〕或小尺寸外觀無外接腳 〔Small Outline Non-leaded，SON〕之導線架，該些引
腳11 0係可依需求不同而設計成如排列於該封膠體丨3()底面 四側邊或是排列於該封膠體1 30底面其中二側邊。每一引 腳11 0係具有一上表面11 1及一下表面丨丨2 ,在本實施例
中’ ”亥些引腳110係具有扇出設計〔fan — 〇ut design〕， 且具有一適當延伸之長度約在60 0 以上，但其往外延伸 長度以不超出該封膠體130過長為佳，該些引腳11Q之上表 面111内端係形成有複數個凸塊接合區i i 3，以對應該晶片 1 2 0之複數個凸塊1 2 3或電性連接端，該些引腳丨丨〇之下表 面11 2外端係形成有複數個外接區11 5，以供外部電性連 接，較佳地，該些外接區115可形成有一導電接著層116， 如錫鉛銲料、鎳金層、錫或其它習知接著材料，而該些引 腳110之上表面111係形成有複數個阻銲凹陷部114 〔solder-resist concave porti〇n〕，如溝槽〔si〇t〕 或孔穴〔cavity〕狀，該些阻銲凹陷部114係鄰接該些凸 塊接合區113，其係可被該封膠體丨3〇填充，較佳地，該些
200522295 五、發明說明（5) 阻鮮凹陷部1 14沿對應引腳1 1〇之截面係為倒r Ω」形，即 該些阻銲凹陷部1 1 4與該些引腳1 1 〇之上表面丨丨1之連接處 為銳角結構，以使得凸塊1 2 3、銲料或銲接材料無法溼潤 摊散至該些阻銲凹陷部1 1 4，該些阻錄凹陷部11 4係可利用 半姓刻〔ha 1 f-etching〕或模具壓合成形，由於在本實施 例中’§亥些引腳11 〇係經半餘刻處理，該些阻銲凹陷部114 之深度約為5 0微米〔m〕，且在該些阻銲凹陷部1 1 4形成 之同時，可在該些引腳110之下表面112之蝕刻形成有複數 個卡掣孔117〔 locking hoi e〕，其深度可在1〇〇 左 右，以供該封膠體130之填覆。 該晶片1 2 0係覆晶接合於該些引腳11 〇，該晶片1 2 〇係 為覆晶型態，該晶片1 2 0係具有一主動面1 21及一對應之背 面1 2 2，在該主動面1 2 1係設有複數個凸塊1 2 3，如錫鉛凸 塊或無鉛凸塊，以作為該晶片1 2 〇之内部積體電路與外部 連接之電性連接端，在本實施例中，該些凸塊丨2 3係排列 於該主動面121之周邊，在覆晶接合後，該晶片120之主動 面1 2 1係朝向該些引腳11 〇，且該些凸塊丨2 3係熔銲接合於 該些引腳11 〇之凸塊接合區1 1 3，由於該些阻銲凹陷部1 1 4 具有防止該些凸塊1 2 3熔接時過度濕潤擴散之功效，因此 該些凸塊1 2 3將有效被限制在該些引腳11 〇之凸塊接合區 11 3而不會擴散至該些引腳1 1 〇之上表面丨丨1其它部位，其 係省略習知在導線架上防鋒層〔s〇lder mask layer〕之 構件。此外，該些引腳1 1 〇在下表面11 2内端可形成有複數 個支撐區1 1 8，其係對應該些凸塊接合區1 1 3並與該些外接
200522295 五、發明說明（6) '--1 區11 5為共平面，以利在覆晶接合時支撐該些引腳丨丨〇之 端。 該封膠體1 3 0係包覆該些引腳1丨〇與該晶片丨2 〇，並填 充至該些引腳110之阻銲凹陷部1 14及填覆該些引腳11〇之 卡掣孔11 7，以有效穩固結合該些引腳丨丨〇與該封膠體 · 130，該封膠體130係可利用習知壓模〔m〇lding〕技術形 ， 成’而該些引腳110之外接區115與支撐區118係顯露於^ 封膠體130之底面。因此，本發明係利用在該些引_u〇^之 具倒「Ω」形截面之阻銲凹陷部11 4鄰接該些引腳丨丨〇之上 表面11 1内端之凸塊接合區1 1 3，以限制該晶片1 2 〇之凸塊 I 23在該些凸塊接合區11 3接合及避免擴散污染至該些引腳ji II 0之其它部位，並且，該些阻銲凹陷部丨丨4係被該封膠體 130所填充’以穩固該些引腳11〇之内端。 在本實施例中，請參閱第2圖，可在形成該封膠體13() 之後，將一耐熱膠膜 140〔High temp. resistanee. film〕貼固於§亥些引腳110之支撐區118，當該導線架上覆 曰曰半導體封裝結構1 〇 〇表面接合至一外部印刷電路板6 2 q 時，該些引腳110之外接區2 15係形成有銲膏61〇 〔presolder〕或其它導接物質，以結合至該外部印刷電 路板620 ’利用該財熱膠膜140可避免在該些外接區jig上 f 之銲奮610污染至該些支撲區118而造成短路，且可穩固該 些引腳110之内端，並且該耐熱膠膜140係提供有一表面接 合之高度差，可提高該封裝體之可靠度，該耐熱膠膜丨4〇 係為一種可耐高溫不變形並且不具有導電性之樹脂，該耐
第14頁 200522295 五、發明說明（7) 熱膠膜140之厚度約在5〇〜1〇〇 ，形成該耐熱膠膜140之 方法係可利用黏貼或液態塗佈後加以固化等方式。 在本發明之第二具體實施例中，請參閱第3圖，另一 導線架上覆晶半導體封裝結構2 〇 〇係主要包含有複數個引 腳210、一晶片2 20及一封膠體23 0，該晶片220係覆晶接合 於该些導線2 1 0且被該封膠體2 3 〇包覆，其中，每一引腳 210係具有一上表面211及一下表面212，該些引腳21〇之上 表面2 1 1内端係形成有凸塊接合區2丨3以及鄰接之阻銲凹陷
部214，該些阻銲凹陷部214係具有倒「Ω」形之截面為較 佳’以阻止在該晶片2 2 0主動面2 2 1之凸塊2 2 2過度濕潤擴 散’並且該些阻銲凹陷部2 1 4係可供該封膠體23 〇填充，該 些引腳210在與該晶片22 0之覆晶接合處係彎折形成有一上 升區216〔 upset area〕，使得除了在其外端之外接區215 ，外’该些引腳21 〇之其它下表面21 2係被該封膠體230覆 蓋穩固’該封膠體2 3 0係包覆該些引腳21 〇與該晶片2 2 〇， 因此，利用該些引腳2 1 〇之該些阻銲凹陷部2丨4有效限制該 些凸塊222在該些引腳210之凸塊接合區213之接合而不致 過度擴散’省略導線架上防銲層之構件，較佳地，該些引 腳210在該上升區216之下表面212貼固有一耐熱膠膜24〇,
以穩固該些引腳210之内端，保持該些引腳21〇之凸塊接合 區213在平整水平面，並且可利用該耐熱膠膜24〇之張力特 14 以承文6亥晶片220的重量，避免該些引腳21〇向下彎 曲0 在本發明之第三具體實施例中，請參閱第4圖，一
第15頁 —1 200522295 五、發明說明（8) 線架上覆晶半導體封裝結構3 0 0係主要包含有複數個引腳 310、一第一晶片320、一封膠體330以及一内置散熱片 340，其中該些引腳310、第一晶片3 20、封膠體330係與第 二具體實施例之引腳210、晶片2 20、封膠體230大致為相 同元件，該些引腳3 1 0之上表面3 1 1係形成有内端之凸塊接 合區3 1 3以及鄰接該些凸塊接合區3 1 3且具有倒「Q」形截 面之阻銲凹陷部3 1 4，該些阻銲凹陷部3 1 4係用以阻止在該 第一晶片320主動面321之凸塊322在該些引腳310在該些凸 塊接合區3 1 3之外的其它上表面3 11過度濕潤擴散，並且該 些阻銲凹陷部314係被該封膠體3 30所填充，而該内置散熱 片3 4 0亦設置於該封膠體3 3 0内，且其係以一黏膠層3 41貼 設該些引腳310在該上升區316之下表面312，以支樓該些 引腳310之凸塊接合區313並且增進散熱，該些引腳31〇之 下表面3 1 2外端係形成有複數個外接區31 5，其係顯露於該 封膠體3 3 0 ’以供外部電性連接。此外，本發明係不局限 於單一晶片之覆晶封裝，該導線架上覆晶半導體封裝結構 300係另包含有一第二晶片3 50，該第二晶片350係為覆晶 型態’在該第二晶片3 5 0之主動面3 5 1係形成有凸塊3 5 2， 該第二晶片3 5 0係以凸塊3 5 2覆晶接合於該第一晶片3 2 〇。 在本發明之第四具體實施例中，請參閱第5圖，一導 線架上覆晶半導體封裝結構4 0 0係主要包含有複數個引腳 410、一第一晶片420、一封膠體430、一内置散熱片440以 及至少一第二晶片450，其中該些引腳41〇、第一晶片 420、封膠體430與第二晶片450係與第三具體實施例之引
第16頁 200522295
腳310、第一晶片320、封膠體330與第二晶片350大致為相
同元件，該些引腳410之上表面411係形成有内端之凸塊接 合區413以及鄰接該些凸塊接合區413且具有倒「Q」形截 面之阻銲凹陷部4 1 4，該些阻銲凹陷部4 1 4係用以阻止在該 第一晶片420主動面421之凸塊422在該些引腳41〇在該些凸 塊接合區41 3之外的其它上表面4 11過度濕潤擴散，該些引 腳4 1 0之下表面4 1 2外端則形成有複數個不被該封膠體4 3 〇 覆蓋之外接區415，在該第二晶片450之主動面451係形成 有凸塊452，該第二晶片450係以凸塊452覆晶接合於該第 一晶片420之主動面421，該内置散熱片440係裝設於該些 引腳410之上表面411，該内置散熱片440係具有位於邊緣 之一固定接觸端441，以黏著貼設在該些引腳41 〇之上表面 411，該内置散熱片440之固定接觸部441係位在該些阻銲 凹陷部414之外側，並且可在該内置散熱片440與該第一晶 片420之背面配置有一導熱膠442，以增進散熱效果。 在本發明之第五具體實施例中，請參閱第6圖，一導 線架上覆晶半導體封裝結構5 〇 〇係主要包含有複數個引腳 510、一第一晶片520、一封膠體530、一第二晶片540，其
中該些引腳510、第一晶片5 20、封膠體530係與第二具體 實施例之引腳210、晶片220、封膠體230大致為相同元 件’該些引腳510之上表面511係形成有内端之凸塊接合區 5 1 3以及鄰接該些凸塊接合區5丨3且具有倒「Ω」形截面之 阻銲凹陷部514，該些引腳5 1〇之下表面512外端係形成有 複數個外接區515，且該些外接區515係不被該封膠體43〇
第17頁 200522295 五、發明說明（10) 所覆蓋’而第一晶片520在主動面521之複數個凸塊522係 接合於該些引腳51 0之凸塊接合區51 3，且在該些阻銲凹陷、 部5 1 4之限制下不擴散至該些引腳51 〇之上表面5 11其它部 位’該第二晶片5 4 0係以一黏膠層5 4 1貼設於該第一晶片 520之背面，並以複數個銲線542〔如金線〕電性連接該第 二晶片540至該些引腳51〇之上表面511。 一引腳具有一鄰接
此外’本發明並不局限在所有的每一 凸塊接合β 之凸塊接 具有阻銲 〔bus bai 本發 為準， 為準，任 圍内所作之任何變化與修改， 200522295 - — —·---_____ __— ____ 圖式簡單說明 【圖式簡單說明】 第1圖··依據本發明之第一具體實施例，一導線架上覆晶 半導體封裝結構之截面示意圖； 第2圖：依據本發明之第一具體實施例，該導線架上覆晶 半導體封裝結構結合於一外部印刷電路板之截面 示意圖； 第3圖：依據本發明之第二具體實施例，一導線架上覆晶 •半導體封裝結構之截面示意圖；
第4圖·依據本發明之第三具體實施例，一導線架上覆晶 半導體封裝結構之截面示意圖； 第5圖：依據本發明之第四具體實施例，一導線架上覆晶 •半導體封裝結構之截面示意圖；及 第6圖·依據本發明之第五具體實施例，一導線架上覆晶 半導體封裝結構之截面示意圖。 元件符號簡單說明： 1 0 0半導體封裝結構 11 2下表面 11 5 外接區 118支撐區 122背面 140耐熱膠膜 2 1 2下表面
110引腳 111上表面 113凸塊接合區 114阻銲凹陷部 116導電接著層 117卡掣孔 1 2 0晶片 1 21主動面 123凸塊 130封膠體 2 0 0半導體封裝結構 210引腳 211上表面
第19頁 200522295 圖式簡單說明 2 1 3凸塊接合區 216 上升區 222 凸塊 300半導體封裝結 310引腳 ° 31 3凸塊接合區 316 上升區 322凸塊 341黏膠層 352凸塊 4〇〇半導體封裝結 410引腳 41 3凸塊接合區 420第一晶片 430封膠體 441固定接觸端 4 5 0第二晶片 5〇〇半導體封裝 510引腳 51 3凸塊接合區 516上升區 5 2 2凸塊 5 41黏膠層 610 銲膏 2 1 4阻銲凹陷部 2 2 0晶片 2 3 0封膠體 構 3 1 1上表面 3 1 4阻銲凹陷部 320第一晶片 3 3 0封膠體 35〇第二晶片 構 4 11上表面 4 1 4阻銲凹陷部 4 2 1主動面 440内置散熱片 442導熱膠 4 5 1主動面 構 511上表面 51 4 阻銲凹陷部 52〇第一晶片 5 3 0封膠體 542銲線 6 2 0印刷電路板 21 5外接區 221主動面 240耐熱膠膜 312下表面 3 1 5外接區 3 2 1主動面 340内置散熱片 351主動面 412下表面 41 5外接區 422凸塊 4 5 2凸塊 512下表面 51 5外接區 521主動面 540第二晶，片

Claims (1)

  1. 200522295 六、申請專利範圍 --1 【申請專利範圍】 1、 一種導線架上覆晶半導體封裝結構，包含： 複數個引腳，每一引腳係具有一上表面及一下表面， 其中該些引腳之上表面内端係形成有複數個凸塊接合 區，该些引腳之下表面外端係形成有複數個外接區； 一第一晶片，其係設於該些引腳之上表面； 、 複數個凸塊，其係接合該第一晶片與該些引腳之凸塊 接合區；及 一封膠體，其係包覆該第一晶片與該些引腳，而該些 引腳之外接區係顯露於該封膠體； 其中，該些引腳係具有至少一阻銲凹陷部，其係形成· 於對應引腳之上表面，該阻銲凹陷部係鄰接對應·引腳之 凸塊接合區並填充有該封膠體。 2、 如申請專利範圍第丨項所述之導線架上覆晶半導體封 裝結構，其中該阻銲凹陷部係具有倒「Ω」形截面。 3、 如申睛專利範圍第丨項所述之導線架上覆晶半導體封 裝結構，其中該阻銲凹陷部係由半蝕刻形成。 4、 如申凊專利範圍第丨項所述之導線架上覆晶半導體封 裝、口構其中4阻銲凹陷部係具有約5 0 // m之深度。 5、 如申請專利範圍第J項所述之導線架上覆晶半導體封彳· 装結構’其中該些導腳係具有大於6〇〇 之長度。 6、 如申請專利範圍第丨項所述之導線架上覆晶半導體封 裝結構，其中該些引腳之下表面係形成有複數個卡掣 孔，其係被該封膠體所填覆。
    第21頁 200522295 申請專利範圍
    7、 如申睛專利範圍第6項所述之導線架上覆晶半導體封 裝結構，其中該些卡掣孔係具有約1 00 “ m之深度。 8、 如申請專利範圍第丨或7項所述之導線架上覆晶半導 體封裝結構，其中該些引腳之下表面内端係形成有複數 個支樓區’其係對應於該些凸塊接合區。 9、 如申請專利範圍第8項所述之導線架上覆晶半導體封 裝結構，其另包含有一耐熱膠膜，其係貼固該些引腳之 支撐區。 10如申叫專利範圍第8項所述之導線架上覆晶半導體
    封裝結構，其中該些引腳之支撐區係與該些外接區 共平面。 11請專利範圍第10項所述之導線架上覆晶半導體 .、口構其中δ亥些引腳之支撲區係顯露於該封膠 12、 如申請專利 封裝結構，其 區，使得該些 它下表面被該 13、 如申請專利 封裝結構，其 係貼設於該些 14、 如申請專利 封裝結構，其 散熱片與該些 範圍第1項所述之導線架上覆如 中該些引腳之内端係彎折形成於一上 外接區顯露於該封膠體而該些引腳之 封膠體覆蓋。 ^
    範圍第12項所述之導線架上覆晶半马 另包含有一内置散熱片，該内置散熱 引腳在該上升區之下表面。 範圍第13項所述之導線架上覆晶半驾 另包含有一黏膠層，其係形成在該内 引腳在該上升區之下表面之間。
    200522295 、申請專利範圍 15、如申請專利範圍第1項所述之導線架上覆晶半導體 ，裝結構，其另包含有一第二晶片，其係覆晶接合於 5亥第一晶片之主動面。 16 17 18 &上覆晶半導體 其係貼設於該第 、如申請專利範圍第1項所述之導線 封裝結構，其另包含有一第二晶片， 一晶片之背面。 、如申請專利範圍第1項所述之導線架上覆晶半導體 封裝結構，其另包含有一内置散熱片，其係設於該些 引腳之上表面，且該内置散熱片接觸該些引腳之上表 面之部位係在該些阻銲凹陷部之外側。 、、一種覆晶式半導體封裝結構之導線架，其係包含有 複數個引腳，每一引腳係具有一上表面及一下表面， 其中該些引腳之上表面内端係形成有複數個凸塊接合 區，該些引腳之下表面外端係形成有複數個外接區， 該些引腳係具有至少一阻銲凹陷部，該阻銲凹陷部係 形成於對應引腳之上表面且鄰接對應引腳之凸塊接合 1 9、如申請專利範圍第丨8項所述之覆晶式半導體封裝結 構之導線架，其中該阻銲凹陷部係具有倒「Ω」形截 面0 〇、如申請專利範圍第18項所述之覆晶式半導體封裝結 構之導線架，其中該阻銲凹陷部係由半蝕刻形成。 1、如申請專利範圍第丨8項所述之覆晶式半導體封裴結 構之導線架，其中該阻銲凹陷部係具有約5 0 // m之深 200522295 六、申請專利範圍^ ' " " " - 一| 度。 22、 如申請專利範圍第1 8項所述之覆晶式半導體封裝結、 構之導線架，其中該些導腳係具有大於600 之長 度。 23、 如申請專利範圍第丨8項所述之覆晶式半導體封裝結 構之導線架，其中該些引腳之下表面係形成有複數個 卡掣孔，以供一封膠體之覆蓋。 24、 如申請專利範圍第丨8項所述之覆晶式半導體封裝結 構之導線架，其中該些卡掣孔係具有約1 0 0 // m之深 度。 2 5、如申請專利範圍第1 8項所述之覆晶式半導體封裝結_ 構之導線架，其中該些引腳之下表面内端係形成有複 數個支撐區’其係對應於該些凸塊接合區。 26、 如申請專利範圍第25項所述之覆晶式半導體封裝結 構之導線架，其中一耐熱膠膜係貼固該些引腳之支樓 (ft 〇 27、 如申請專利範圍第25項所述之覆晶式半導體封裝結 構之導線架，其中該些引腳之支撐區係與該些外接區 為共平面。 28、 如申請專利範圍第18項所述之覆晶式半導體封裝結 構之導線架，其中該些引腳之内端係彎折形成於一上 升區。 29、 如申請專利範圍第28項所述之覆晶式半導體封装結 構之導線架’其另包含有一内置散熱片，該内置散熱
    第24頁 200522295 ^、尹請專利範圍 片係貼設該些引腳在該上升區之下表面。 30、如申請專利範圍第29項所述之覆丰 置散Hi 一黏膠層’其係形成在該内 散熱片與该些引腳在該上升區之下表面之間。 士申。月專利範圍第1 8項所述之覆晶式 線架，其另包含有-内置散熱片，其係設二 之上表面，且該内置散熱片接觸該些引腳之上 之"卩位係在該些阻銲凹陷部之外側。
    第25頁
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TWI394255B (zh) * 2008-10-14 2013-04-21 Texas Instruments Inc 具有用以局限焊料毛細現象之溝槽式導線的半導體裝置
US20220238421A1 (en) * 2021-01-22 2022-07-28 Semiconductor Components Industries, Llc Molded packaging for wide band gap semiconductor devices
US12087677B2 (en) * 2021-01-22 2024-09-10 Semiconductor Components Industries, Llc Molded packaging for wide band gap semiconductor devices

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US20050133896A1 (en) 2005-06-23
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