201019426 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種増 進散熱之無外引腳式半導體封裝構造及其組合。 【先前技術】 無外引腳式半導體封裝構造是一種能符合小尺寸封 裝的導線架基底半導體封裝構造。無外引腳式半導號封 0 裝構造通常是利用在底面的引腳外表面焊接至一外部 印刷電路板，而能應用到各式電器產品’如筆記型電 腦、手機或個人數位助理（PDA)等等。由於晶片在運作 時會發出高熱，因此’若無適時將熱氣散逸，必定會影 響其正常的運作，導致執行速度降低甚或影響其使用壽 命。傳統上能解決散熱之技術手段，一般係採用熱傳導 之方式’而晶片所產生的熱量需先經由晶片承座傳導， 再透過印刷電路板將熱量擴散出來，再以印刷電路板的 • 内外表面散熱到大氣，導致整個電器產品都會發熱。 請參閱第1圖所示，為習知無外引腳式半導體封裝 構造接合至一外部印刷電路板之截面示意圖。該無外引 腳式半導體封裝構造100係利用銲料21與22表面接合 在一印刷電路板1〇上。該無外引腳式半導體封裝構造 100主要包含一晶片承座110、複數個引腳120、一晶 片130、複數個銲線141與142以及一封膠體150。 該晶片承座11〇係具有一上表面111以及一下表面 11 2。該些引腳12 〇係排列在該晶片承座11 〇之兩側或 201019426 四側周邊’並且每一引腳120具有一内表面121以及 外表面122。該晶片130係設置在該晶片承座110之該 上表面111，並具有複數個電極131。該些銲線141係 ❿201019426 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to an externally mounted semiconductor package structure and a combination thereof. [Prior Art] The lead-free semiconductor package structure is a lead frame base semiconductor package structure that can conform to a small-sized package. The external lead-free semi-conductor seal 0-mount construction is usually soldered to an external printed circuit board using the outer surface of the pin on the bottom surface, and can be applied to various electrical products such as notebook computers, mobile phones or personal digital assistants ( PDA) and so on. Since the wafer emits high heat during operation, if the heat is dissipated in a timely manner, it will definitely affect its normal operation, resulting in a slower execution speed or even an impact on its service life. Traditionally, the technical means of solving heat dissipation is generally to use heat conduction. The heat generated by the wafer needs to be conducted through the wafer holder, and then the heat is diffused through the printed circuit board, and then the inner and outer surfaces of the printed circuit board are dissipated. To the atmosphere, the entire electrical product will heat up. Referring to Fig. 1, a cross-sectional view of a conventional unleaded semiconductor package structure bonded to an external printed circuit board is shown. The outer lead type semiconductor package structure 100 is bonded to the surface of a printed circuit board 1 by the surfaces of the solders 21 and 22. The leadless semiconductor package structure 100 mainly includes a wafer holder 110, a plurality of pins 120, a wafer 130, a plurality of bonding wires 141 and 142, and a gel 150. The wafer holder 11 has an upper surface 111 and a lower surface 11 2 . The leads 12 are arranged on either side of the wafer holder 11 or on the four sides of the 201019426 and each pin 120 has an inner surface 121 and an outer surface 122. The wafer 130 is disposed on the upper surface 111 of the wafer holder 110 and has a plurality of electrodes 131. The welding wires 141 are ❿
電性連接該晶片130之該些電極13ι至該些引腳120， 至少一銲線142係電性連接該晶片13〇之對應電極m 至該晶片承座110。該封膠體150係密封該晶片13〇與 該些銲線141與142，並結合該些引腳120與該晶片承 座no，但顯露該晶片承座11()之該下表面112以及該 些引腳120之該外表面i 22。基本上，該晶片承座u〇 之該下表面112以及該些引腳120之該外表面122是與 該封勝髖150之底面為共平面。. 該印刷電路板10係具有一第一表面u、一第二表 面12以及複數個填入有導熱物質之導熱孔該 印刷電路板10更具有複數個接墊14與複數個導熱區塊 16與17 ’該些導熱區塊16與17係分別設置在該第一 表面11與該第二表面12’為面積遠大於該些接墊14 的金屬墊，並以該些導熱孔13連接這兩個導熱區塊16 與17。該銲料21係固接該些引腳12〇之外表面122至 該印刷電路板10之該些接墊14，以達成訊號傳輸。該 銲料22則固接該晶片承座11〇之下表面ιΐ2至該印刷 電路板10之該導熱區塊16,以建立導熱路徑。該晶片 13〇在運作時所產生的熱量，會先經由該晶片承座ιι〇 以及銲料22熱傳導到該印刷電路板1〇之該導熱區塊 16,再透過該些導熱孔13將熱量傳導至該導熱區塊 6 201019426 17’才可將該晶片130產生之熱量以熱傳導方式傳遞到 至該印刷電路板10 ’再散熱到外界大氣，而達到散熱 效果。此種熱傳導的散熱效果與該晶片承座110之下表 面11 2的面積大小息息相關’當無外引聊式半導體封裝 構造1〇〇微小化設計時，該晶片承座110之下表面112 也會變得更小’導致散熱效果不佳。 此外，此種熱傳導的散熱方式也會增加該印刷電路 參板1〇與銲料21、22的溫度，導致該印刷電路板1〇以 及連接在該印刷電路板10的其它元件（如被動元件或其 它積體電路7G件）產生功能衰退或劣化。此外，該印刷 電路板10需設計成具有該些導熱孔13與該些導熱區塊 16與17，且在該些導熱孔13内還必須填入導熱物質 30，才能使熱量傳遞至並分散於該印刷電路板1〇，故 該印刷電路板10之製造方法更為複雜且成本增加。 【發明内容】 • 為了解決上述之問題’本發明之主要目的係在於提 供一種增進散熱之無外引腳式半導體封裝構造，能以熱 對流方式進行無外引腳式半導體封裝構造之散熱，不會 因微小化而影響散熱效率，亦不會增加被表面接合的印 刷電路板的溫度。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示—種增進散熱之無外引腳式半 導體封裝構造’主要包含一導線架之一呈中空狀之晶片 承座與複數個引腳、一第一晶片、複數個第-銲線以及 7 201019426 .一封膠體。該晶片承座係具有一上表面、一下表面與一 貫穿之熱對流鏤空區，每一引腳係具有一内表面與一外 表面。該第一晶片係設置於該晶片承座之該上表面並對 準覆蓋至該熱對流鏤空區，該第一晶片係具有複數個第 一電極。該些第一銲線係連接該第一晶片之該些第一電 極至該些引腳之該些内表面β該封膠禮係密封該第一晶 片與該些第一銲線並結合該些引腳與該晶片承座，該封 膠體之一底面係顯露出該些引腳之該些外表面與該晶 片承座之該熱對流鏤空區，使該第一晶片之一背面具有 一不被該封膠體密封的中央顯露區。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述無外引腳式半導體封裝構造中，該晶片承座 之該熱對流鏤空區係可以蝕刻方式形成。 在前述無外引腳式半導體封裝構造中，該晶片承座 # 之該下表面係可呈墊塊狀而與該些引腳之外表面為尺 寸對應。 在前述無外引腳式半導體封裝構造中，藉由該熱對 流鏤空區以使該第一晶片之該背面係可相對凹入該封 膠體之該底面。 在前述無外引腳式半導體封裝構造中，該晶片承座 之周邊係可形成有一高於該上表面之突出部。 在前述無外引腳式半導體封裝構造中，可另包含有 矣少一第二銲線，其係連接該第一晶片之其中一該些第 8 201019426 一電極呈該晶片承座之該突出部。 在前述無外引腳式半導體封裝構造中 一第二晶片，其係設置於該第一晶片上並： 二電極。 在前述無外引腳式半導艘封裝構造中 複數個第三銲線，係連接該第二晶片之該 該些引腳之該些内表面。 Φ 在前述無外引腳式半導體封裝構造中 至少一第四銲線，其係連接該第二晶片之 二電極炱該第一晶片之該些第一電極。 在前述無外引腳式半導體封裝構造中 該底面係可形成有至少一凹入的排氣槽， 對流鎮空區至該底面之一邊緣。 本發明還揭示適用於前述的無外引腳 構造之組合，主要包含至少一上述之無外 傷 封裴構造、一印刷電路板以及銲料。該印 有一第一表面、一相對之第二表面以及複 一表面與該第二表面之氣孔，該銲料結合 半導體封裝構造之該些引腳之該些外表 路板之該第一表面，並且該些氣孔係對準 流鋒空區，以使該第—晶片與該印刷電路 熱對流腔室。 由以上技術方案可以看出，本發明之 外弓丨腳式半導體封裝構造及其組合，具有 ，可另包含有 良有複數個第 ’可另包含有 些第二電極至 ’可另包含有 其中一該些第 ，該封膠體之 其係連通該熱 式半導體封裝 引腳式半導體 刷電路板係具 數個貫穿該第 該無外引腳式 面至該印刷電 連通至該熱對 板之間形成一 增進散熱之無 以下優點與功 9 '201019426 . 效： 一、 利用晶片承座之熱對流鏤空區顯露於封 面，使得晶片背面具有一不被封膠體密 焊料填滿的中央顯露區，故能在晶片與 之間形成熱對流腔室’利用熱對流方式 裝構造内晶片直接排出到外界空氣，以 刷電路板溫度的方式進行良好散熱。此 參 到封裝構造微小化的影響而導致散熱效 二、 藉由熱對流鏤空區使第一晶片之背面相 體之底面並為局部顯露，故能增強第一 散熱效果，並在對外接合時，避免銲料 晶片之背面。 三、 由於封膠體之底面另形成有凹入的排氣 氣槽連通熱對流鏤空區至底面之邊緣， 片熱量的空氣可經由排氣槽對外排出。 • 四、藉由位於晶片承座周邊且高於晶片承座 突出部，能阻擋黏晶膠體溢流到晶片承 位（即突出部）。 【實施方式】 以下將配合所附圖示詳細說明本發明之 應注意的是，該些圓示均為簡化之示意圖， 法來說明本發明之基本架構或實施方法故 案有關之元件與組合關係，圖中所顯示之元 際實施之數目、形狀、尺寸做等比例繪製， 膠體之一底 封也不會被 印刷電路板 將熱源由封 不會增加印 外，不會受 率變差。 對凹入封膠 晶片的直接 污染到第一 槽，並且排 以使攜帶晶 之上表面的 座的打線部 實施例，然 僅以示意方 僅顯示與本 件並非以實 某些尺寸比 10 .201019426 . 例與其他相關尺寸比例或已誇張或是簡化處理’以提供 更清楚的描述。實際實施之數目、形狀及尺寸比例為一 種選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種增進散熱之無 外引腳式半導體封裝構造舉例說明於第2圖之截面示 意圖與第3圖之仰視圖。該無外引腳式半導體封裝構造 2 00主要包含一導線架201、一第一晶片230、複數個 φ 第一銲線241以及一封膠體25〇。其中，該導線架201 係包含一晶片承座210與複數個引腳220，該晶片承座 210係呈中空狀《該導線架201之材質係可為鐵、鋼或 其合金等金屬材料。該晶片承座210與該些引腳220係 為該導線架201之一部分，故具有該導線架201之相同 金屬材質。 請參閱第2圖所示，該晶片承座210係具有一上表 面211、一下表面212與一熱對流鏤空區213，該熱對 ® 流鏤空區213係貫穿該上表面211與該下表面212。每 一引腳220係具有一内表面221與一外表面222。該晶 片承座210之該上表面211係為承載該第一晶片230之 黏晶面’並且不外露於該封膠體250。該晶片承座210 之該下表面212則是外露於該封膠體25〇。該熱對流鏤 a區213係位於該晶片承座210之中央。在此所指「熱 子流縷二區」係指一個空間區域的氣體存在著高於周邊 的度，使得它處溫度較低的氣體往該空間區域流動， 工間區域的岗溫氣體則被擠壓排出。在本實施例中， 11 201019426 • 該晶片承座21 0之該熱對流鏤空區213係可藉由蝕 式形成。該熱對流鏤空區213的形狀係可為矩形凹 請參閱第3圖所示，該些引腳220係分別排列在該 承座210之兩相對的平行側邊。請參閱第2圖所示 些引腳220之該些内表面221位於該封膠體250内 位是作為與該第一晶片230的内部電性連接面。該 腳220之該些外表面222係顯露於該封膠醴250， φ 對外接合至一印刷電路板40(如第4圖所示）。 請參閱第2圖所示，該第一晶片230係設置於 片承座210之該上表面211。該第一晶片230係對 蓋該熱對流鏤空區213，以使該熱對流鏤空區213 對該第一晶片230空氣接觸。該第一晶片230係具 數個第一電極231。具體而言，該第一晶片230係 一黏晶膠體260將該第一晶片230之一背面232之 黏貼在該晶片承座210之該上表面211。該黏晶膠想 ® 係可為Β階膠體或液態膠，可利用點膠或印刷方式 在該晶片承座210之該上表面211。在本實施例中 第一晶片230之該些第一電極231係可為銲墊，如 或銅墊。該些第一電極23 1係可設置於該第一晶片 之主動面側邊，如兩對應側邊或四周側邊。 請參閱第2圖所示，該些第一鲜線241係連接 一晶片230之該些第一電極231至該些引腳220之 内表面221。該些第一銲線241係可利用打線方 成’其材質可為金或銅。該些第一銲線241之兩端 刻方 穴。 晶片 ，該 的部 些引 以供 該晶 準覆 内可 有複 利用 側邊 I 260 形成 ，該 鋁勢 230 該第 該些 式形 打線 12 201019426 * 接合點的形成方式係可採用超音波接合、熱壓接合或上 述兩者組合方式，以電性連接該第一晶片230與該些引 腳 220 ° 請參閱第2圖所示，該封膠體25 0係密封該第一晶 片230與該些第一銲線241並結合該些引腳22〇與該晶 片承座210。該封膠體25〇之一底面251係顯露出該些 引腳220之該些外表面222與該晶片承座21〇之該熱對 • 流鏤空區213 ’使該第一晶片230之該背面232具有一 中央顯露區233。該中央顯露區233係不被該封膠體250 密封。該封膠體250係為一種内含矽氧填充物的絕緣性 熱固性樹知’如環氧模封化合物（EMC，epoxy molding compound) ’可利用模封（或稱轉移成形）方法形成。在 不同實施例中，或可利用印刷或點塗方法形成該封膠體 250。因此，藉由該熱對流鏤空區213以使該第一晶片 230之該背面232係可相對凹入該封膠艎250之該底面 粵 251 ’故在該熱對流鏤空區213的空氣可接觸到該第一 晶片230之該中央顯露區233。請參閱第4圖所示，當 該無外引腳式半導體封裝構造200在接合至該印刷電 路板40時，能避免銲料52污染到該第一晶片230之該 背面232，並可提供熱對流產生的熱氣體容納空間。請 參閱第3圖所示，較佳地，該封勝趙250之該底面251 係可形成有至少一凹入的排氣槽252。該排氣槽252係 連通該熱對流鏤空區213至該底面25 1之一邊緣253。 具體而言，該排氣槽25 2與該熱對流鏤空區213係可組 13 .201019426 成為具有兩端開放口之長條狀凹槽。當該無外引腳式半 導體封裝構造200對外接合時，該晶片承座210之該下 表面212連通有該排氣槽252之邊緣253將不會被該銲 料52封閉，以使該第一晶片230所散發之熱量可傳到 該熱對流鏤空區213，再經由該排氣槽252排出。 請再參閱第2圖所示，較佳地，該晶片承座210之 周邊係可形成有一突出部214。該突出部214係高於該 % 晶片承座210之該上表面211，該突出部214係可為環 狀或指狀。在本實施例中，該無外引腳式半導體封裝構 造20 0可另包含有至少一第二銲線242，其係連接該第 一晶片23 0之其中一該些第一電極231至該晶片承座 21〇之該突出部214。因此，該突出部214可用以阻檔 該黏晶膠艘26〇溢流至打線連接區域。 為了因應其他功能需求或為了增加記憶體容量，在 . 可容許的封膠厚度下可以往上堆疊晶片。該無外引腳式 半導體封裝構造200可另包含有一第二晶片270，其係 設置於該第—晶片230上並具有複數個第二電極271。 該第一晶片270之尺寸係為小於或等於該第一晶片230 之尺寸’但應不覆蓋該些第一電極231。該無外引腳式 半導體封裝構造2〇〇可另包含有複數個第三銲線243, 係連接該第二晶片27〇之該些第二電極271至該些引脚 220之該些内表面221。該無外引腳式半導體封裝構造 200可另包含有至少一第四銲線244，其係連接該第二 晶片270之其中一該些第二電極271至該第一晶片23〇 14 .201019426 .之該些第一電極231。 本發明還揭示適用於前述的無外引腳式半導體封裝 構造之一種組合，舉例說明於第4圖之截面示意圖。該 無外引腳式半導體封裝構造之組合主要包含至少一上 述之無外引腳式半導體封裝構造200、一印刷電路板4〇 以及銲料51與52。其中，該印刷電路板40係具有一 第一表面41、一相對之第二表面42以及複數個氣孔 參 43。該些氣孔43係貫穿該第一表面41與該第二表面 42。該些氣孔43係可採用機械穿孔或雷射鑽孔之方式 形成。具體而言，該印刷電路板40更具有複數個接墊 44與45，該些接墊44與45係設置於該第一表面41， 以供電性接合該無外引腳式半導體封裝構造200 ^在本 實施例中，該無外引腳式半導體封裝構造200係以表面 黏著（SMT)技術安裝至該印刷電路板40。該銲料51結 合該無外引腳式半導體封裝構造200之該些引腳220之 ❹ 該些外表面222至該印刷電路板40之該些接塾44，該 銲料52係結合該無外引腳式半導體封裝構造2〇〇之該 晶片承座210之該下表面212至該印刷電路板40之該 些接墊45。其中’該銲料51與52係可以網版印刷 (screen print)方式預先形成於該印刷電路板4〇之該上 表面211之該些接墊44與45。當該無外引腳式半導體 封裝構造200放置於該印刷電路板4〇之該上表面211， 可利用回焊以達到表面黏著。較佳地，該第一晶片23 0 與該印刷電路板40之間係為非密閉，故有利於將在該 15 .201019426 熱對流鏤空區2 1 3的氣體排出。 ❹The electrodes 113 of the wafer 130 are electrically connected to the pins 120, and at least one bonding wire 142 is electrically connected to the corresponding electrode m of the wafer 13 to the wafer holder 110. The encapsulant 150 seals the wafer 13 and the bonding wires 141 and 142, and combines the pins 120 with the wafer holder no, but exposes the lower surface 112 of the wafer holder 11 ( ) and the The outer surface i 22 of the pin 120. Basically, the lower surface 112 of the wafer holder u and the outer surface 122 of the pins 120 are coplanar with the bottom surface of the sealing hip 150. The printed circuit board 10 has a first surface u, a second surface 12 and a plurality of heat conducting holes filled with a heat conductive material. The printed circuit board 10 further has a plurality of pads 14 and a plurality of heat conducting blocks 16 and 17 ' The heat conducting blocks 16 and 17 are respectively disposed on the first surface 11 and the second surface 12 ′, and the metal pads are larger than the pads 14 , and the two heat conducting holes 13 are connected Thermal block 16 and 17. The solder 21 is fixed to the outer surface 122 of the pins 12 to the pads 14 of the printed circuit board 10 for signal transmission. The solder 22 is secured to the lower surface ι 2 of the wafer holder 11 to the thermally conductive block 16 of the printed circuit board 10 to establish a thermally conductive path. The heat generated by the wafer 13 during operation is first transferred to the heat conducting block 16 of the printed circuit board 1 through the wafer holder ιι and the solder 22, and the heat is transmitted through the heat conducting holes 13 to The heat conducting block 6 201019426 17' can transfer the heat generated by the wafer 130 to the printed circuit board 10' in a thermally conductive manner to dissipate heat to the outside atmosphere to achieve a heat dissipation effect. The heat dissipation effect of the heat conduction is closely related to the area of the lower surface 11 2 of the wafer holder 110. When the external design of the semiconductor package is not miniaturized, the lower surface 112 of the wafer holder 110 is also Getting smaller 'causes poor heat dissipation. In addition, the heat dissipation of the heat conduction also increases the temperature of the printed circuit board and the solder 21, 22, resulting in the printed circuit board 1 and other components connected to the printed circuit board 10 (such as passive components or other The integrated circuit 7G) causes a function degradation or deterioration. In addition, the printed circuit board 10 is designed to have the heat conducting holes 13 and the heat conducting blocks 16 and 17, and the heat conducting material 30 must be filled in the heat conducting holes 13 to transfer heat to and distribute the heat. Since the printed circuit board is compact, the manufacturing method of the printed circuit board 10 is more complicated and costly. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide an external lead type semiconductor package structure for improving heat dissipation, which can heat-dissipate a heatless convection-free semiconductor package structure without The heat dissipation efficiency is affected by miniaturization, and the temperature of the surface-bonded printed circuit board is not increased. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses an externally mounted semiconductor package structure that enhances heat dissipation. The main structure comprises a hollow wafer holder and a plurality of leads, a first wafer, a plurality of first bonding wires, and 7 201019426 . A colloid. The wafer holder has an upper surface, a lower surface and a continuous thermal convection hollow region, each pin having an inner surface and an outer surface. The first wafer is disposed on the upper surface of the wafer holder and is in contact with the thermal convection hollow region. The first wafer has a plurality of first electrodes. The first bonding wires are connected to the first electrodes of the first wafer to the inner surfaces of the pins. The sealing ceremony seals the first wafer and the first bonding wires and combines the first bonding wires. a pin and the wafer holder, a bottom surface of the encapsulant exposing the outer surfaces of the pins and the thermal convection hollow region of the wafer holder, so that one of the back sides of the first wafer has a The central exposed area of the sealant seal. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing external lead type semiconductor package structure, the heat convection hollow region of the wafer holder may be formed by etching. In the above-described external lead type semiconductor package structure, the lower surface of the wafer holder # may be in the form of a spacer and correspond to the outer surface of the pins. In the foregoing external lead type semiconductor package structure, the thermal convection hollow region is such that the back surface of the first wafer can be relatively recessed into the bottom surface of the encapsulant. In the foregoing external lead type semiconductor package structure, the periphery of the wafer holder may be formed with a protrusion higher than the upper surface. In the foregoing non-outer-pin type semiconductor package structure, a second bonding wire may be further included, which is connected to one of the first electrodes of the first wafer, and the first electrode is the protrusion of the wafer holder. . In the foregoing external lead type semiconductor package structure, a second wafer is disposed on the first wafer and has two electrodes. In the foregoing external leadless semiconductor package structure, a plurality of third bonding wires are connected to the inner surfaces of the pins of the second wafer. Φ In the foregoing external lead type semiconductor package structure, at least one fourth bonding wire is connected to the second electrodes of the second wafer and the first electrodes of the first wafer. In the foregoing external lead type semiconductor package structure, the bottom surface may be formed with at least one recessed exhaust groove, and a convection hollow space to an edge of the bottom surface. The present invention also discloses combinations suitable for use in the aforementioned external leadless construction, primarily comprising at least one of the above described non-invasive sealing structures, a printed circuit board, and solder. The first surface, an opposite second surface, and the air holes of the second surface and the second surface are printed, the solder bonding the first surface of the surface boards of the pins of the semiconductor package structure, and the The vents are aligned with the flow front region to cause the first wafer to thermally convect the chamber with the printed circuit. It can be seen from the above technical solutions that the externally-arranged semiconductor package structure and the combination thereof of the present invention have, and may further comprise a plurality of 'the other two electrodes may be further included to the 'may include one of the other The first sealing body of the sealing body is connected to the thermal semiconductor package, and the pin-type semiconductor brush circuit board is connected to the first non-outer pin surface to the printed electrical connection to form between the heat-to-board There is no advantage and improvement of the heat dissipation 9 '201019426 . Effect: 1. The heat convection hollow area of the wafer holder is exposed on the front cover, so that the back side of the wafer has a central exposed area which is not filled with the sealing body tight solder, so A heat convection chamber is formed between the wafers. The inner wafer is directly discharged to the outside air by a heat convection method, and the heat is cooled by brushing the temperature of the circuit board. The effect of miniaturization of the package structure leads to heat dissipation. Second, the bottom surface of the back surface of the first wafer is partially exposed by the heat convection hollow region, so that the first heat dissipation effect can be enhanced, and when externally joined, Avoid the back side of the solder wafer. 3. The bottom surface of the sealant is further formed with a concave exhaust gas groove connecting the heat convection hollow area to the edge of the bottom surface, and the piece of heat of the air can be discharged to the outside through the exhaust groove. • 4. By the periphery of the wafer holder and above the wafer holder protrusion, the adhesive colloid can be blocked from overflowing to the wafer support (ie, the protrusion). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the present invention will be described in detail with reference to the accompanying drawings, which are a simplified schematic diagram illustrating the elements and combinations of the basic architecture or implementation method of the present invention. The number, shape and size of the meta-implementation shown in the figure are drawn in equal proportions. One of the seals of the gel will not be sealed by the printed circuit board, and the heat source will not increase the printing, and the rate will not be deteriorated. Directly contaminating the recessed encapsulated wafer to the first groove, and arranging the wire-bonding portion of the seat carrying the upper surface of the crystal, but only the schematic is shown only to some size ratio of the piece is not actual. 2010. The case is proportional to other related dimensions or has been exaggerated or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, an externally mounted semiconductor package structure for enhancing heat dissipation is illustrated in a cross-sectional view of Fig. 2 and a bottom view of Fig. 3. The leadless semiconductor package structure 200 mainly includes a lead frame 201, a first wafer 230, a plurality of φ first bonding wires 241, and a gel 25 〇. The lead frame 201 includes a wafer holder 210 and a plurality of pins 220. The wafer holder 210 is hollow. The material of the lead frame 201 can be metal materials such as iron, steel or alloys thereof. The wafer holder 210 and the pins 220 are part of the lead frame 201 and thus have the same metal material of the lead frame 201. Referring to FIG. 2, the wafer holder 210 has an upper surface 211, a lower surface 212, and a heat convection hollowed out region 213. The heat pairing/flowing hollow region 213 extends through the upper surface 211 and the lower surface 212. . Each pin 220 has an inner surface 221 and an outer surface 222. The upper surface 211 of the wafer holder 210 is a doped surface that carries the first wafer 230 and is not exposed to the encapsulant 250. The lower surface 212 of the wafer holder 210 is exposed to the encapsulant 25'. The thermal convection a region 213 is located in the center of the wafer holder 210. The term "hot sub-flow zone" as used herein refers to the fact that the gas in a space region has a higher degree than the surrounding area, so that the gas at a lower temperature flows to the space region, and the hot gas in the work area is Squeeze out. In the present embodiment, 11 201019426 • the heat convection hollow region 213 of the wafer holder 210 can be formed by etching. The shape of the heat convection hollow region 213 may be a rectangular recess. As shown in Fig. 3, the pins 220 are respectively arranged on opposite parallel sides of the socket 210. Referring to FIG. 2, the inner surfaces 221 of the pins 220 are located inside the encapsulant 250 as an internal electrical connection surface with the first wafer 230. The outer surfaces 222 of the legs 220 are exposed to the sealant 250, and φ is externally bonded to a printed circuit board 40 (as shown in FIG. 4). Referring to FIG. 2, the first wafer 230 is disposed on the upper surface 211 of the sheet holder 210. The first wafer 230 is directed to cover the thermal convection hollow region 213 such that the thermal convection hollow region 213 is in air contact with the first wafer 230. The first wafer 230 is provided with a plurality of first electrodes 231. Specifically, the first wafer 230 is adhered to the upper surface 211 of the wafer holder 210 by a backing 232 of the first wafer 230. The adhesive layer can be a colloidal or liquid glue which can be dispensed or printed on the upper surface 211 of the wafer holder 210. In the embodiment, the first electrodes 231 of the first wafer 230 may be solder pads, such as copper pads. The first electrodes 23 1 may be disposed on the side of the active surface of the first wafer, such as two corresponding sides or peripheral sides. Referring to FIG. 2, the first fresh lines 241 are connected to the first electrodes 231 of a wafer 230 to the inner surface 221 of the pins 220. The first bonding wires 241 can be formed by wire bonding, and the material thereof can be gold or copper. The two ends of the first bonding wires 241 are engraved with a square hole. a portion of the wafer, the portion of which may be formed by the reuse side I 260. The aluminum potential 230 is formed by the patterning line 12 201019426 * The bonding point is formed by ultrasonic bonding, Thermocompression bonding or a combination of the two to electrically connect the first wafer 230 and the pins 220 °. Referring to FIG. 2 , the encapsulant 25 0 seals the first wafer 230 and the first A bonding wire 241 is combined with the pins 22 and the wafer holder 210. One of the bottom surfaces 251 of the encapsulant 25 exposes the outer surface 222 of the pins 220 and the thermal pair 镂 213 of the wafer holder 21 such that the back surface 232 of the first wafer 230 There is a central revealing area 233. The central exposed area 233 is not sealed by the sealant 250. The encapsulant 250 is an insulating thermosetting resin containing an oxygen-containing filler. For example, an epoxy molding compound (EMC) can be formed by a molding (or transfer molding) method. In various embodiments, the encapsulant 250 can be formed using a printing or spot coating process. Therefore, the heat convection hollow region 213 is such that the back surface 232 of the first wafer 230 can be relatively recessed into the bottom surface of the sealant 250. Therefore, the air in the heat convection hollow region 213 can be contacted. The central exposed area 233 of the first wafer 230. Referring to FIG. 4, when the outer lead type semiconductor package structure 200 is bonded to the printed circuit board 40, the solder 52 can be prevented from contaminating the back surface 232 of the first wafer 230, and heat convection can be provided. The generated hot gas accommodates the space. Referring to FIG. 3, preferably, the bottom surface 251 of the Fengsheng Zhao 250 may be formed with at least one concave exhaust groove 252. The venting groove 252 is connected to the heat convection hollowed out region 213 to an edge 253 of the bottom surface 251. Specifically, the venting groove 25 2 and the heat convection hollowed out area 213 can be set as 13 . 201019426 as an elongated groove having open ports at both ends. When the outer lead-type semiconductor package structure 200 is externally bonded, the lower surface 212 of the wafer holder 210 communicates with the edge 253 of the exhaust groove 252 that will not be closed by the solder 52, so that the first wafer The heat dissipated by 230 can be transferred to the heat convection hollow zone 213 and discharged through the exhaust vent 252. Referring to FIG. 2 again, preferably, the periphery of the wafer holder 210 may be formed with a protrusion 214. The projection 214 is higher than the upper surface 211 of the % wafer holder 210, and the projection 214 can be annular or finger shaped. In this embodiment, the lead-free semiconductor package structure 20 may further include at least one second bonding wire 242 connecting one of the first electrodes 231 of the first wafer 230 to the wafer. The protrusion 21 of the socket 21 is. Therefore, the protrusion 214 can be used to block the adhesive gel 26 from overflowing to the wire bonding region. In order to meet other functional requirements or to increase the memory capacity, the wafers can be stacked up at a permissible sealant thickness. The lead-free semiconductor package structure 200 can further include a second wafer 270 disposed on the first wafer 230 and having a plurality of second electrodes 271. The size of the first wafer 270 is less than or equal to the size of the first wafer 230 but should not cover the first electrodes 231. The external lead type semiconductor package structure 2 另 further includes a plurality of third bonding wires 243 connected to the second electrodes 271 of the second wafer 27 to the inner surfaces of the pins 220 221. The lead-free semiconductor package structure 200 can further include at least one fourth bonding wire 244 that connects one of the second electrodes 271 of the second wafer 270 to the first wafer 23〇14.201019426 . The first electrodes 231. The present invention also discloses a combination of the above-described external leadless semiconductor package constructions, exemplified in a cross-sectional view of Fig. 4. The combination of the external lead type semiconductor package structure mainly comprises at least one of the above-described external lead type semiconductor package structure 200, a printed circuit board 4A, and solders 51 and 52. The printed circuit board 40 has a first surface 41, an opposite second surface 42, and a plurality of air holes 43. The air holes 43 extend through the first surface 41 and the second surface 42. The air holes 43 can be formed by mechanical perforation or laser drilling. Specifically, the printed circuit board 40 further includes a plurality of pads 44 and 45. The pads 44 and 45 are disposed on the first surface 41 to electrically connect the external lead type semiconductor package structure. In the present embodiment, the leadless semiconductor package structure 200 is mounted to the printed circuit board 40 by surface mount (SMT) technology. The solder 51 is combined with the pins 220 of the lead-free semiconductor package structure 200 and the outer surfaces 222 to the pads 44 of the printed circuit board 40. The solder 52 is coupled to the external pins. The semiconductor package structure 2 includes the lower surface 212 of the wafer holder 210 to the pads 45 of the printed circuit board 40. The solders 51 and 52 are pre-formed on the pads 44 and 45 of the upper surface 211 of the printed circuit board 4 by screen printing. When the outer lead type semiconductor package structure 200 is placed on the upper surface 211 of the printed circuit board 4, reflow can be utilized to achieve surface adhesion. Preferably, the first wafer 230 and the printed circuit board 40 are non-sealed, so that the gas in the heat convection hollow zone 2 1 3 of the 15 .201019426 is advantageously discharged. ❹
此外，請參閱第4圖所示’該些氣孔43係對準連通 至該熱對流鏤空區2 1 3，以使該第一晶片23 〇與該印刷 電路板40之間形成一熱對流腔室，其高度是由該第一 晶片230之該背面232之該中央顯露區233至該印刷電 路板40之該第一表面41之距離，大於該無外引腳式半 導體封裝構造200至該印刷電路板40之接合缝隙，使 得該熱對流鏤空區213内可容納較多的熱空氣。而上述 在該熱對流鏤空區213内的熱空氣係由該第一晶片23〇 在運作所產生的熱量所造成。當在該熱對流鏤空區213 的氣體溫度上升，會與在該印刷電路板4〇之該第二表 面42外的冷空氣或室溫空氣產生溫度差。在該印刷電 路板40之第二表面42之冷空氣可經由該些氣孔43導 入至該熱對流鏤空區213,形成熱對流作用。而在該熱 對流鏤空區213的熱空氣受擠壓後會透過該排氣槽252 向外排出。因此，利用該晶片承座2〗〇之該熱對流鏤空 區213,可使冷空氣或室溫空氣可直接導入至該第一晶 片230之該背面232之該中央顯露區233，以達到熱對 流的散熱效果，故能夠以不會增加印刷電路板溫度的方 式進行良好散熱。此外，不會受到封裝構造微小化的影 響而導致散熱效率變差。 / 此外，該印刷電路板40 能以熱對流方式達到散熱之 板之導熱孔與散熱片的設計 僅需形成多個氣孔43，便 效果，不需要習知散熱型基 。因此，相較於習知的印刷 201019426 . 電路板40之設計，本發明之該印刷電路板40更具有低 成本與易於製作之功效。 請參閱第4圖所示，該無外引腳式半導體封裝構造 2 00之組合可另包含一加壓器60，係設置於該印刷電絡 板40之該第二表面42，以使該些氣孔43在朝向該第 二表面42的孔端係具有大於該熱對流鏤空區213之氣 壓。在本實施例中，該加壓器60係為一風扇。該加蘑 φ 器60能促進由該些氣孔43充填冷空氣至該熱對流鏤空 區213，以利熱空氣由該熱對流鏤空區213之周邊排 出，增強熱對流的散熱效率，快速的將多餘的熱量排 出，不會過度傳熱到該印刷電路板40。 依據本發明之第二具體實施例，另一種增進散熱之 無外引腳式半導體封裝構造舉例說明於第5圖之仰視 圖。談無外引腳式半導體封裝構造300所包含之主要元 件係與第一具體實施例的導線架、晶片230、第一銲線 Φ 以及封膠體250大致為相同’故以第一具體實施例之元 件符號標示之或可省略說明。該導線架包含一呈中空狀 之晶片承座210與複數個引腳220,其中該晶片承座210 係具有一貫穿之熱對流鏤空區213。該晶片230之背面 23 2係具有一顯露於該熱對流鏤空區213内之中央顯露 區233，以使該晶片230不被該封膠體250完全密封。 在本實施例中，該晶片230之尺寸係可大於該熱對流鏤 空區213 。 請參閱第5圖所示，該封膠體25 0係具有一底面 17In addition, referring to FIG. 4, the air holes 43 are aligned and connected to the heat convection hollow area 21 to form a heat convection chamber between the first wafer 23 and the printed circuit board 40. The height is from the central exposed area 233 of the back surface 232 of the first wafer 230 to the first surface 41 of the printed circuit board 40, which is greater than the outer lead type semiconductor package structure 200 to the printed circuit. The joint gap of the plate 40 allows the hot convection hollowed out zone 213 to accommodate more hot air. The hot air in the heat convection hollow region 213 is caused by the heat generated by the operation of the first wafer 23 . When the temperature of the gas in the heat convection hollow region 213 rises, a temperature difference is generated from the cold air or room temperature air outside the second surface 42 of the printed circuit board 4. Cool air at the second surface 42 of the printed circuit board 40 can be conducted through the air holes 43 to the heat convection hollow region 213 to form a heat convection effect. The hot air in the hot convection hollow area 213 is discharged through the exhaust groove 252 after being squeezed. Therefore, by using the heat convection hollow area 213 of the wafer holder 2, cold air or room temperature air can be directly introduced into the central exposed area 233 of the back surface 232 of the first wafer 230 to achieve thermal convection. The heat dissipation effect enables good heat dissipation without increasing the temperature of the printed circuit board. In addition, the heat dissipation efficiency is not deteriorated by the influence of the miniaturization of the package structure. In addition, the design of the heat conducting hole and the heat sink of the heat-dissipating plate of the printed circuit board 40 can be formed by heat convection only by forming a plurality of air holes 43. The effect is that a conventional heat-dissipating type base is not required. Therefore, the printed circuit board 40 of the present invention has a lower cost and ease of fabrication than the conventional printing 201019426. Referring to FIG. 4, the combination of the external lead type semiconductor package structure 200 may further include a presser 60 disposed on the second surface 42 of the printed circuit board 40 to enable the The air vent 43 has a gas pressure greater than the heat convection hollow region 213 at the end of the hole toward the second surface 42. In this embodiment, the pressurizer 60 is a fan. The mushroom φ 60 can promote the filling of the cold air into the hot convection hollow area 213 by the air holes 43, so that the hot air is discharged from the periphery of the heat convection hollow area 213, thereby enhancing the heat dissipation efficiency of the heat convection, which is quick and redundant. The heat is discharged without excessive heat transfer to the printed circuit board 40. In accordance with a second embodiment of the present invention, another heat-dissipating, external-lead semiconductor package construction is illustrated in Figure 5 in a bottom view. The main components included in the lead-free semiconductor package structure 300 are substantially the same as those of the lead frame, the wafer 230, the first bonding wire Φ, and the encapsulant 250 of the first embodiment, so that the first embodiment is The symbol of the component is indicated or may be omitted. The leadframe includes a hollow wafer holder 210 and a plurality of pins 220, wherein the wafer holder 210 has a heat convection hollowed out region 213 therethrough. The back surface 23 2 of the wafer 230 has a central exposed region 233 exposed in the thermal convection hollow region 213 so that the wafer 230 is not completely sealed by the encapsulant 250. In this embodiment, the wafer 230 may be larger in size than the thermal convection hollow region 213. Referring to Figure 5, the encapsulant 25 0 has a bottom surface 17
201019426 25卜在該底面251’顯露出該些引腳220之夕 該晶片承座210之下表面212、以及該熱； 2 1 3。在本實施例中’該晶片承座2 1 〇之該 係可呈多個墊塊狀’而該下表面212係與每 2 20之外表面222可為尺寸對應，以避免連 承座210之該下表面212的焊料迴焊成大 地，該些引腳220係排列在該封膠體25〇之 之四側邊緣。而該晶片承座21〇之該下表面 列於該熱對流鎮空區2i3之邊緣。因此，由 產生的熱量會經由中央顯露區233傳導至 空區213内的空氣，使其成為熱空氣，再由 式半導體封裝構造300與接合後印刷電路 出，達成熱對流散熱功效，大幅度減少熱量 印刷電路板’故印刷電路板與連接兩者之間 產生高溫’元件或烊接點不會損壞或劣化， 的可靠度。此外，不會受到封裝構造微小化 致散熱效率變差。 以上所述’僅是本發明 士技e h 的較佳實施例而 本發明作任何形式上的限制 加担帝l 』雖然本發明已 例揭露如上，然而並非用 Λ限定本發明，任 技術者’在不脫離本發明之 s ^ ^ 筏術範圍内，所 單修改、等效性變化與修錦 岣仍屬於本發 圍内。 放 【圖式簡單說明】 卜表面222、 對流鏤空區 下表面212 一該些引腳 接在.該晶片 球。更具體 該底面2 5 1 2 1 2係可排 該晶片2 3 0 該熱對流鏤 該無外引腳 板之缝隙排 傳導到外部 的焊料不易 以維持產品 的影響而導 已，並非對 以較佳實施 何熟悉本項 作的任何簡 明的技術範 18 201019426 第1圖：為習知無外引腳式半導體封裝構造接合至一外 部印刷電路板之截面示意圖。 第2圖：為依據本發明之第一具體實施例的一種増進散 熱之無外引腳式半導體封裝構造之截面示意 圖。 第3圖：為依據本發明之第一具體實施例的無外引腳式 半導體封裝構造之仰視圖。 第4圖：為依據本發明之第一具體實施例的無外引腳式 半導體封裝構造接合至一外部印刷電路板之 截面示意圖。 第5圖：為依據本發明之第一具體實施例的另一種增進 散熱之無外引腳式半導艘封裝構造之仰視 【主要元件符號說明】 10 印刷電路板 11 第一表面· 12 第二表面 13 導熱孔 14 接墊 16 導熱區塊 17 導熱區塊 21 銲料 22 銲料 30 導熱物質 40 印刷電路板 41 第一表面 42 第二表面 43 氣孔 44 接墊 45 接墊 51 銲料 52 銲料 60 加壓器 100 無外引腳式半導體封裝構造 110 晶片承座 111 上表面 112 下表面 120 引腳 121 内表面 122 外表面 19 201019426201019426 25b shows the lower surface 212 of the wafer holder 210 and the heat; 2 1 3 at the bottom surface 251'. In the present embodiment, the system of the wafer holder 2 1 can be in the form of a plurality of blocks, and the lower surface 212 can be sized corresponding to the outer surface 222 of each 2 20 to avoid the connection of the socket 210. The solder of the lower surface 212 is reflowed to the ground, and the pins 220 are arranged on the four side edges of the encapsulant 25 . The lower surface of the wafer holder 21 is listed at the edge of the heat convection hollow area 2i3. Therefore, the generated heat is conducted to the air in the empty area 213 via the central exposure area 233 to become hot air, and then the semiconductor package structure 300 and the printed circuit are bonded to achieve heat convection heat dissipation, which is greatly reduced. The thermal printed circuit board 'so the high temperature of the printed circuit board and the connection between the two components or the joints will not be damaged or deteriorated. In addition, the package structure is not miniaturized, resulting in poor heat dissipation efficiency. The above description is merely a preferred embodiment of the present invention, and the present invention is not limited to the above. However, the present invention has been disclosed above, but is not intended to limit the present invention. Within the scope of s ^ ^ 筏 本 , , , 所 所 所 所 所 所 所 所 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Picture of the drawing] The surface 222 and the lower surface 212 of the convection hollow area are connected to the wafer ball. More specifically, the bottom surface 2 5 1 2 1 2 can discharge the wafer 2 3 0. The heat convection of the solder which is not conducted to the outside of the slot of the outer lead plate is not easy to maintain the influence of the product, and is not 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Fig. 2 is a cross-sectional view showing the structure of an externally-leaded semiconductor package having a thermal insulation according to a first embodiment of the present invention. Fig. 3 is a bottom plan view showing the structure of the leadless semiconductor package in accordance with the first embodiment of the present invention. Figure 4 is a cross-sectional view showing the bonding of an external lead type semiconductor package structure to an external printed circuit board in accordance with a first embodiment of the present invention. Figure 5 is a bottom view of another heat-insulated, external-lead semi-conductor package structure according to the first embodiment of the present invention. [Main component symbol description] 10 Printed circuit board 11 First surface · 12 Second Surface 13 Thermal via 14 Pad 16 Thermal block 17 Thermal block 21 Solder 22 Solder 30 Thermally conductive material 40 Printed circuit board 41 First surface 42 Second surface 43 Air hole 44 Pad 45 Pad 51 Solder 52 Solder 60 Pressurizer 100 Outer Pinned Semiconductor Package Construction 110 Wafer Mount 111 Upper Surface 112 Lower Surface 120 Pin 121 Inner Surface 122 Outer Surface 19 201019426
130 晶片 131 電極 141 銲線 142 銲線 200 無外引腳 式半導體封裝構造 201 導線架 210 晶片承座 211 上表面 213 熱對流鏤 空區 214 突出部 220 引腳 221 内表面 230 第一晶片 231 第一電極 233 中央顯露 1¾ 241 第一銲線 242 第二銲線 244 第四銲線 250 封膠體 251 底面 253 邊緣 260 黏晶膠體 270 第二晶片 300 無外引腳 式半導體封裝構造 150封膠體 212下表面 222外表面 232背面 243第三銲線 252排氣槽 271第二電極130 wafer 131 electrode 141 bonding wire 142 bonding wire 200 without external lead semiconductor package structure 201 lead frame 210 wafer holder 211 upper surface 213 heat convection hollow region 214 protruding portion 220 pin 221 inner surface 230 first wafer 231 first Electrode 233 centrally exposed 13⁄4 241 first bonding wire 242 second bonding wire 244 fourth bonding wire 250 encapsulant 251 bottom surface 253 edge 260 adhesive colloid 270 second wafer 300 no external lead semiconductor package structure 150 lower surface of the encapsulant 212 222 outer surface 232 back surface 243 third bonding wire 252 exhaust groove 271 second electrode