TW200515574A - Method of fabricating lead frame and method of fabricating semiconductor device using the same, and semiconductor device and portable apparatus and electronic apparatus comprising the same - Google Patents

Method of fabricating lead frame and method of fabricating semiconductor device using the same, and semiconductor device and portable apparatus and electronic apparatus comprising the same

Info

Publication number
TW200515574A
TW200515574A TW093127834A TW93127834A TW200515574A TW 200515574 A TW200515574 A TW 200515574A TW 093127834 A TW093127834 A TW 093127834A TW 93127834 A TW93127834 A TW 93127834A TW 200515574 A TW200515574 A TW 200515574A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
same
fabricating
lead frame
electronic apparatus
Prior art date
Application number
TW093127834A
Other languages
English (en)
Other versions
TWI355729B (en
Inventor
Ichiro Kishimoto
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of TW200515574A publication Critical patent/TW200515574A/zh
Application granted granted Critical
Publication of TWI355729B publication Critical patent/TWI355729B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
TW093127834A 2003-10-06 2004-09-15 Method of fabricating lead frame and method of fab TWI355729B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003347415A JP4372508B2 (ja) 2003-10-06 2003-10-06 リードフレームの製造方法およびそれを用いた半導体装置の製造方法、ならびに半導体装置ならびにそれを備えた携帯機器および電子装置

Publications (2)

Publication Number Publication Date
TW200515574A true TW200515574A (en) 2005-05-01
TWI355729B TWI355729B (en) 2012-01-01

Family

ID=34539999

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093127834A TWI355729B (en) 2003-10-06 2004-09-15 Method of fabricating lead frame and method of fab

Country Status (5)

Country Link
US (2) US7354804B2 (zh)
JP (1) JP4372508B2 (zh)
KR (1) KR20050033498A (zh)
CN (1) CN100397599C (zh)
TW (1) TWI355729B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI811617B (zh) * 2020-01-30 2023-08-11 日商大口電材股份有限公司 引線框架

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI338358B (en) * 2003-11-19 2011-03-01 Rohm Co Ltd Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same
WO2008084920A1 (en) * 2007-01-08 2008-07-17 Pusan National University Industryuniversity Cooperation Foundation Curved surface forming method of a metal plate
US7838339B2 (en) 2008-04-04 2010-11-23 Gem Services, Inc. Semiconductor device package having features formed by stamping
JP5120037B2 (ja) * 2008-04-10 2013-01-16 住友金属鉱山株式会社 リード露出型パッケージ用リードフレーム
CN102437055A (zh) * 2011-12-14 2012-05-02 成都中科精密模具有限公司 基于轴向二极管生产线的压扁贴片塑封二极管的生产方法
CN103594448A (zh) * 2013-11-15 2014-02-19 杰群电子科技（东莞）有限公司 一种引线框架
US9293395B2 (en) * 2014-03-19 2016-03-22 Freescale Semiconductor, Inc. Lead frame with mold lock structure
JP6840466B2 (ja) * 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
CN106129049A (zh) * 2016-07-26 2016-11-16 苏州查斯特电子有限公司 一种矩阵式整流桥堆二极管
JP6783128B2 (ja) * 2016-12-06 2020-11-11 三菱電機株式会社 リード加工装置

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JP2837064B2 (ja) * 1993-05-25 1998-12-14 ローム株式会社 ボンディングパッド面の圧印加工方法
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KR100230515B1 (ko) * 1997-04-04 1999-11-15 윤종용 요철이 형성된 리드 프레임의 제조방법
JP2924854B2 (ja) * 1997-05-20 1999-07-26 日本電気株式会社 半導体装置、その製造方法
JP2951308B1 (ja) * 1998-03-13 1999-09-20 松下電子工業株式会社 リードフレームの製造方法
JP3562311B2 (ja) * 1998-05-27 2004-09-08 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
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JP4390317B2 (ja) * 1999-07-02 2009-12-24 株式会社ルネサステクノロジ 樹脂封止型半導体パッケージ
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI811617B (zh) * 2020-01-30 2023-08-11 日商大口電材股份有限公司 引線框架

Also Published As

Publication number Publication date
TWI355729B (en) 2012-01-01
JP2005116705A (ja) 2005-04-28
CN1606141A (zh) 2005-04-13
JP4372508B2 (ja) 2009-11-25
US20050104174A1 (en) 2005-05-19
KR20050033498A (ko) 2005-04-12
CN100397599C (zh) 2008-06-25
US20070001276A1 (en) 2007-01-04
US7354804B2 (en) 2008-04-08

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