TW200508631A - Semiconductor testing apparatus and controlling method thereof - Google Patents

Semiconductor testing apparatus and controlling method thereof

Info

Publication number
TW200508631A
TW200508631A TW093117611A TW93117611A TW200508631A TW 200508631 A TW200508631 A TW 200508631A TW 093117611 A TW093117611 A TW 093117611A TW 93117611 A TW93117611 A TW 93117611A TW 200508631 A TW200508631 A TW 200508631A
Authority
TW
Taiwan
Prior art keywords
waveform
common
pattern waveform
semiconductor devices
individual
Prior art date
Application number
TW093117611A
Other languages
English (en)
Other versions
TWI317430B (en
Inventor
Kazuhiko Sato
Sae-Bum Myung
Hiroyuki Chiba
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of TW200508631A publication Critical patent/TW200508631A/zh
Application granted granted Critical
Publication of TWI317430B publication Critical patent/TWI317430B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW093117611A 2003-06-19 2004-06-18 Semiconductor testing apparatus and controlling method thereof TWI317430B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003174477 2003-06-19
JP2003185679A JP4334285B2 (ja) 2003-06-19 2003-06-27 半導体試験装置及びその制御方法

Publications (2)

Publication Number Publication Date
TW200508631A true TW200508631A (en) 2005-03-01
TWI317430B TWI317430B (en) 2009-11-21

Family

ID=33543477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093117611A TWI317430B (en) 2003-06-19 2004-06-18 Semiconductor testing apparatus and controlling method thereof

Country Status (9)

Country Link
US (1) US7356435B2 (zh)
EP (1) EP1643509B1 (zh)
JP (1) JP4334285B2 (zh)
KR (1) KR100733234B1 (zh)
CN (1) CN100524536C (zh)
DE (1) DE602004025347D1 (zh)
PT (1) PT1643509E (zh)
TW (1) TWI317430B (zh)
WO (1) WO2004114318A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7543199B2 (en) 2005-09-29 2009-06-02 Hynix Semiconductor, Inc. Test device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7913002B2 (en) * 2004-08-20 2011-03-22 Advantest Corporation Test apparatus, configuration method, and device interface
JP4542852B2 (ja) 2004-08-20 2010-09-15 株式会社アドバンテスト 試験装置及び試験方法
JP2006294104A (ja) * 2005-04-08 2006-10-26 Yokogawa Electric Corp デバイス試験装置およびデバイス試験方法
KR100788913B1 (ko) * 2005-11-18 2007-12-27 주식회사디아이 반도체 장치의 테스트 시스템을 위한 전치 분기 패턴 발생장치
KR100750397B1 (ko) * 2006-01-24 2007-08-17 주식회사디아이 웨이퍼 검사장치의 멀티 테스트 구현시스템
US20070208968A1 (en) * 2006-03-01 2007-09-06 Anand Krishnamurthy At-speed multi-port memory array test method and apparatus
KR100859793B1 (ko) * 2007-06-25 2008-09-23 주식회사 메모리앤테스팅 반도체 테스트 장치 및 이를 이용한 반도체 테스트 방법
US7821284B2 (en) * 2008-10-24 2010-10-26 It&T Semiconductor test head apparatus using field programmable gate array
CN101776731B (zh) * 2009-01-14 2012-06-13 南亚科技股份有限公司 半导体组件测试装置与方法
JP2011007721A (ja) * 2009-06-29 2011-01-13 Yokogawa Electric Corp 半導体試験装置、半導体試験方法および半導体試験プログラム
EP2587489A1 (en) * 2011-10-27 2013-05-01 Maishi Electronic (Shanghai) Ltd. Systems and methods for testing memories
CN103093829A (zh) * 2011-10-27 2013-05-08 迈实电子(上海)有限公司 存储器测试系统及存储器测试方法
US9285828B2 (en) * 2013-07-11 2016-03-15 Apple Inc. Memory system with improved bus timing calibration
US20170045579A1 (en) * 2015-08-14 2017-02-16 Texas Instruments Incorporated Cpu bist testing of integrated circuits using serial wire debug
US10319453B2 (en) * 2017-03-16 2019-06-11 Intel Corporation Board level leakage testing for memory interface
KR20220052780A (ko) * 2020-10-21 2022-04-28 에스케이하이닉스 주식회사 테스트회로를 포함하는 전자장치 및 그의 동작 방법
CN115047307B (zh) * 2022-08-17 2022-11-25 浙江杭可仪器有限公司 一种半导体器件老化测试箱

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0140176B1 (ko) * 1994-11-30 1998-07-15 김광호 반도체 메모리장치의 동작모드 제어장치 및 방법
US6094733A (en) * 1996-01-25 2000-07-25 Kabushiki Kaisha Toshiba Method for testing semiconductor memory devices, and apparatus and system for testing semiconductor memory devices
JPH09288153A (ja) * 1996-04-19 1997-11-04 Advantest Corp 半導体試験装置
US5794175A (en) * 1997-09-09 1998-08-11 Teradyne, Inc. Low cost, highly parallel memory tester
JPH11203893A (ja) * 1998-01-05 1999-07-30 Fujitsu Ltd 半導体装置及び半導体装置の試験方法
US6499121B1 (en) * 1999-03-01 2002-12-24 Formfactor, Inc. Distributed interface for parallel testing of multiple devices using a single tester channel
DE10082824T1 (de) * 1999-08-17 2002-02-28 Advantest Corp Adapter zum Steuern einer Meßvorrichtung, eine Meßvorrichtung, eine Steuervorrichtung für eine Meßvorrichtung, ein Verfahren zum Verarbeiten der Messung und ein Aufzeichnungsmedium
JP3447638B2 (ja) * 1999-12-24 2003-09-16 日本電気株式会社 半導体装置のテスト方法及びシステム並びに記録媒体
JP2002015596A (ja) * 2000-06-27 2002-01-18 Advantest Corp 半導体試験装置
JP2002071766A (ja) * 2000-08-28 2002-03-12 Advantest Corp 半導体試験装置
WO2002103379A1 (fr) * 2001-06-13 2002-12-27 Advantest Corporation Instrument destine a tester des dispositifs semi-conducteurs et procede destine a tester des dispositifs semi-conducteurs
JP4291596B2 (ja) * 2003-02-26 2009-07-08 株式会社ルネサステクノロジ 半導体集積回路の試験装置およびそれを用いた半導体集積回路の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7543199B2 (en) 2005-09-29 2009-06-02 Hynix Semiconductor, Inc. Test device

Also Published As

Publication number Publication date
EP1643509A1 (en) 2006-04-05
EP1643509A4 (en) 2007-04-04
PT1643509E (pt) 2010-03-25
CN100524536C (zh) 2009-08-05
US7356435B2 (en) 2008-04-08
KR100733234B1 (ko) 2007-06-27
EP1643509B1 (en) 2010-01-27
TWI317430B (en) 2009-11-21
KR20060019607A (ko) 2006-03-03
US20060092755A1 (en) 2006-05-04
CN1809896A (zh) 2006-07-26
WO2004114318A1 (ja) 2004-12-29
JP2005063471A (ja) 2005-03-10
JP4334285B2 (ja) 2009-09-30
DE602004025347D1 (de) 2010-03-18

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees