TW200427012A - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
TW200427012A
TW200427012A TW093105058A TW93105058A TW200427012A TW 200427012 A TW200427012 A TW 200427012A TW 093105058 A TW093105058 A TW 093105058A TW 93105058 A TW93105058 A TW 93105058A TW 200427012 A TW200427012 A TW 200427012A
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TW
Taiwan
Prior art keywords
substrate
pins
chip
wafer
package
Prior art date
Application number
TW093105058A
Other languages
English (en)
Other versions
TWI286825B (en
Inventor
Wataru Kikuchi
Toshio Sugano
Satoshi Isa
Original Assignee
Elpida Memory Inc
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Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of TW200427012A publication Critical patent/TW200427012A/zh
Application granted granted Critical
Publication of TWI286825B publication Critical patent/TWI286825B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Description

200427012 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種堆疊式半導體封裝，特別是 於堆疊式DRAM封裝以形成高速資料傳輸。 【先前技術】 請參照第1圖，常見的堆疊式半導體封裝包括數個可 堆疊之半導體封裝，其中個別之可堆疊的半導體封裝包 括··一形成於上表面中央位置之具有一凹處1〇1之基板 102，一由基板102之上表面延伸至下表面之導線圖案 103，一配置於基板1〇2之凹處101中之半導體晶片1〇4，複 數個連接半導體晶片1 0 4以及導線圖案1 〇 3之金屬線1 〇 5， 複數個位於基板102上表面且連接導線圖案1〇3之末端銲墊 106，以及一複數個位於基板丨〇2下表面用以連接並固定導 線圖案103之銲錫球107。 末端銲墊106於圖案上與銲錫球丨〇7排列一致，亦即若 將此類複數個可堆疊之半導體封裝拆開再堆疊時，位於上 層封裝之銲錫球107將--對應至鄰接之下層封裝的末端 銲墊106。所以，藉由堆疊複數個可堆疊之半導體封裝並 完成迴銲（reflowing)步驟後，即可得到一堆疊複數個半 導體晶片且相互連接之堆疊式封装。 請參照第2圖，另一常見的堆疊式半導體封裝包括半 導體晶片111以及個別包覆半導體晶片i j 1之彈性基板 112。 請參照第3圖，每一個堆疊式半導體封裝之半導體晶
2130-6196.PF(N2);Uofung.ptd 第7頁 200427012 五、發明說明（2) 片，如第2圖所示，具有一提供複數個接點121之下表 此/卜，每一個彈性基板112之上表面具有對應於接點 121之弟一傳導銲墊陣列122排列之圖案（可逆圖案）。彈性 ^板11 2之下表層具有第二傳導銲墊陣列，且與第一傳 ill塾相陣^122以垂直方向重疊對齊（即排列之圖案與接點 121相付），第三以及第四傳導銲墊陣列形成於第二傳導 2 =之對側。每個第三以及第四傳導銲墊陣 傳導銲塾陣列之可逆圖案方式排列並透過導。 導# ^^導體晶片1U架設於彈性基板112之上表層時，半 接點m連接於第一傳導銲墊陣列122之第 112之下n，過彈性基板112，其亦位於彈性基板 抽& >表層之弟二傳導銲墊陣列之第二傳導銲墊。據此 __，母個半導體晶片111之接點1 21係連接於相對庫< $ 二以及第四傳導銲墊陣列之銲塾之_。當該彈 =覆該第二半導體晶片ηι ·，該第三以及/四傳導 =陣列便位於半導體晶片之上表層之上，亦即弟該第傳三i 三以：ΐ::ΐ陣列相對。一第五傳導銲墊陣列定義為第 案排列知^鲜塾陣列依相同於第一傳導鮮墊陣列之圖 ΖΑ 4 ，半導體晶片111與相對應之彈性基板1 2便 成為:可堆疊之半導體封裝。 ^ 土板⑴更 藉由堆疊複數個上述結構之可堆疊之半導體封 :第層封裝之第二傳導鲜墊陣列以及鄰近下層封‘ 之第五傳導銲塾陣列便可以銲接方式連接。如此：；： _ 第8頁 2130-6196.PF(N2);Uofung.ptd ι、赞明說明（3) 如第2 圖所示广例體如封\之堆疊封裝便相互堆疊並連接，例 及一半導體曰H 隹豐式半導體封裝係由具有一 亦即藉由堆Ϊ可可堆疊之半導體封裝 封裝。在堆聂^ ^ ^ + V體封裝便可獲得堆疊式 引腳作為連：；近；埯晶因其餘之可堆疊之半導體 堆疊之半導體封壯 &之半導體封裝之用，最底 外部連2 =之弓丨腳(鮮锡球或傳導銲墊)乃用 的引“端二封疊…體 導體封裝之垂直位置，二：：決於母-個可堆 距離而下層封裝且右_ ，、疋上層封裝具有一較長 半導體封裝具；；屬線距離：亦即傳統 ¥體封裝位置不同而有所差異之缺點。 【發明内容】 有鑑於此，本發日月夕Η ΑΑ + 封裝，包括單一其广、 々在於如供一種堆疊式半導f μ 、 土&以及架設於該基底上之兩半導體曰 同。，以使金屬線自外部連接端至兩半導體晶片之線長: 種堆疊式半導體封裝 一種堆疊式半導體封 第二相互對應之表面 本發明之另一目的在於提供一 以形成高速資料傳輸。 為達成上述目的，本發明提供 裝’包括··一基底，具有第一以及 200427012 五、發明說明（4) 以及第一以及第二半導體晶片，每一該晶片具有一架設表 面以=一預定之圖案中提供複數個晶片引腳設置，該第一 以及第二半導體晶片被各自架設於第一以及第二基板表 面’以使該架設表面隔著該基板相互對應。 、於上述之堆疊式半導體封裝中，該基板具有各自對應 ，^，個封裝引腳之該晶片引腳，並形成於不同於一晶片 木彡又區之第一或第二表面，以將第一、第二半導體晶片架 設好。 於 同之一 於 接至與 定引腳 於 屬線， 線部分 引腳， 由該共 大體上 腳。 於 括一介 用金屬 線之長 上述之堆疊式半導體封裝 配置。 疊式半導體封裝 預定圖案 上述之堆 其對應之 與對應於 上述之堆 其中該連 ’其中該 以作為對 用金屬線 相同於該 第一、第二半導 第一、第二半導 疊式半導體封裝 線一端連接至該 連線連接其他共 應該第一、第二 一端至對應之該 共用金屬線一端 上述之堆疊式半導體封裝 層孔’該介層孔形成於該 線之其他端點之間之位置 度彼此相同。 中’該封装引腳以完全相 中’該封裝引腳包括一連 體晶片之晶片引腳，且固 體晶片之弓丨腳連接。 中’該基板具有一共用金 固定引腳以及一分支金屬 用金屬線之端點至兩晶片 半導體晶片之晶片引腳。 晶片引腳之金屬線長度， 至另一對應之該晶片引 中’該分支金屬線部份包 兩晶片引卿以及連接至共 ’而第―、第二分支金屬
於上述之堆疊式半導體封罗 該兩曰H a ^ 衣中’對應於該固定引腳之 通雨日日片引腳透過基板相互面對， 接連接… 該分支金屬線具有一直 牧逆按至兩晶片引腳之介層孔。 於上述之堆疊式半導體封裝中，夕 底，其具有-基層板及/或一能泝：基底係一夕層基 線以及兮八+人β a 匕原供應板，而該共用金屬 琢Μ及該分支金屬線各自 一傳輪線。 9板及/或能源供應板形成 晶圓ΐ =體晶片為—元素晶片（裸晶），例如_，藉由 製作(預製程)以形成，結構，包括一基板以
“兀素晶片架設於基板上並電性連接至該基板。 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 田明參照第4Α、4Β圖，其係顯示根據本發明實施例之一 =豐式半導體封裝10，其包括第一半導體晶片丨丨、第二半 導體晶片1 2，以及一用以架設第一、第二半導體晶片之彈
性基板13。該彈性基板13上下表面為相互對應之第一以及 弟一表面。 該第一半導體晶片11架設於晶片架設區（如第U圖之 51)之彈性基板;13之上表面，以形成對分為兩區域之上表 面的其中之一。該第二半導體晶片12架設於彈性基板13之 下表面，隔著彈性基板1 3對應該第一半導體晶片} i。該第
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例如使 一第二半導體基晶片u、12架設於彈性基板1 用銲錫球。 該弹性基板1 3對摺以包覆該第二半導體曰 摺疊步驟使得剩餘之彈性基板！ 3之上表面區^ (如第=由 之52)成為整個堆疊半導體封裝1〇之底部表面。於; 個封裝引腳(銲錫球)14以作為堆疊式、導體 封裝10之外部連接端。 、卞 > 篮 接著，請參照第5至11圖，將詳細說明每一第一、 二半導體基晶片1 1、1 2以及彈性基板J 3。 第一、第二半導體基晶片U、12之結構彼此相似。 一、第二半導體基晶片J J、1 2皆係一記憶晶片，例如： DRAM。此外，第一、第二半導體基晶片丨j、丨2皆可為由曰 圓製程製作（預製程）製作之元素晶片（或裸晶），或一包= 一基板以及架設於基板上之該元素晶片，由封裝製程（後 製程）形成之封裝結構。 具有封I結構之半導體晶片，例如揭露於曰本專利 第H11-135562號以及第H11 -186449號，於第5、6圖中說 明。請參照第5、6圖，該半導體晶片係藉由架設一元素晶 片20 2、302於基板201、301上形成，利用金屬線（銲 墊）203、303以金屬線銲接方式（或内引腳接合、覆晶連 接’及其他類似方式）電性連接元素晶片2 〇 2、3 0 2與基 板’接著將該晶片2 0 2、3 0 2以及該基板封於樹脂模型中以 保護基板上之導體圖案。 此外’該半導體晶片可為利用一封裝製程（後製程）與
200427012 五、發明說明（7) 晶圓製程（預製程）整合之另一封裝結構，且該封裝製程於 一晶圓層級之下完成。該半導體晶片指的是晶圓級之晶片 大小封裝（chip size package or chip scale package ； CSP)或一晶圓製程封裝。例如，此半導體晶片種類係揭露 於曰本專利第20 02-26 1 1 92號以及第20 03-298 0 0 5號。請參 照第7圖，如上述文件揭露之於晶圓製程之半導體晶片結 構包括.一保護層402、一重裝電線層403(rewiring layer)、一銅柱4〇4以及其他類似物於半導體基板上，並 以樹脂模型4 〇 5加以密封。 請參照第8圖，每一半導體晶片11、1 2具有一附有複 數個引腳（半導體錫球，亦稱為晶片引腳）2 1之表面（架設 表面）’其中該引腳以一預定之圖案配置以適於電性以及 機械連接至彈性基板丨3。 封裝引腳係根據不同之作用（訊號）配置 每 - -…心/…在 1夕·』如， DDR- Π之SDRAM的晶片引腳21以陣列圖案配置並設計出不 同之功能，如第9圖所示。於第9圖中，晶片引腳2 1之配置 係自上層開始。例如，於第9圖中，於第A列第i行之弓丨腳 (A1引腳）係作為VDd。 在此’說明堆疊式半導體1 〇之封裝引腳丨4的配置。該 封裝引腳14以相同於半導體晶片u (或12)之引腳21的預定 圖案配置。例如，形成SDRAMs之堆疊式半導體封裝之封裝 引腳以第1 0圖所示之圖案配置相互堆疊，其中該以粗體字 表示之引腳與第9圖的不同。 請參照第9、10圖，該資料引腳（DQ)以及指令/位址引
200427012 五、發明說明（8) 腳（C / A )個別設置於上半部以及下半部。於第丨〇圖中，3對 6個引腳以粗體字表示包括晶片選擇引腳（cs〇以及CS1)， 計時引腳（CKE0以及CKE1 )，以及晶粒上端引腳（QDT1以及 0DT1)。該些引腳係用以各自獨立操作第一、第二半導體 晶片11、1 2。每一引腳只連接至半導體晶片之一。例如， 若第一晶片11之CS、CKE以及0DT個別連接至封裝晶片引腳 CS0、CKE0以及ODTO，第二晶片12之CS、CKE以及0DT則個 別連接至封裝晶片引腳CSO、CKE0以及〇DT0。 該些用以個別獨立操作第一、第二半導體晶片丨丨、i 2 之封裝引腳被稱為選擇性引腳，而剩餘之封裝引腳被稱為 一般性引腳。 # 如第10圖所示，該堆疊式半導體封裝之封裝引腳配置 包括弟一（或附加）半導體晶片之選擇性引腳，亦包括第9 圖所示之每一半導體晶片所配置之晶片引腳。 此外，該平坦基板1 3係一多層金屬基板，例如一四層 基板包括四層導體層，包括做為兩側表層之較高或較低 (前側或後侧）訊號層以及以VDD、GND板形成之中間兩層。 在此，本發明之彈性基板1 3為四層基板。 θ 如第11圖所示，於彈性基板1 3上表面之晶片架設區5 J 附有複數個晶片連接銲墊（第一連接銲墊陣列），該銲塾以 相同於第一半導體晶片丨丨（或丨2 )之引腳2丨的預定圖案配 置在剩餘之彈性基板13之上表面區域52中，一外部連接 墊陣列包括複數個對應該封裝引腳（封裝引腳陣列）14之外 部連接塾以作為堆疊式半導體封裝1 0之外部連接端，形成 第14頁 200427012 發明說明（9) 一第一半導體晶片11之預定引腳配置之玻璃圖案。於彈性 基板1 3之下表面以及一位於架設晶片區5丨之後侧之上的區 域5 3、’設置有複數個晶片連接銲墊於玻璃圖案中以對應第 二半導體晶片12之引腳21。於彈性基板13之下表面以及對 應=外部連接銲墊陣列之區域54中，形成複數個連接至外 部銲墊之介層孔（如第13圖之506)。彈性基板13更具有複 數個金屬線（訊號線之金屬圖案）以及其他介層孔（第1 4圖 之6 03、604、608、610、612 ;第15 圖之702 ;第 16 圖之 803 )以個別連接相對應之該第一、第二半導體連接銲銲墊 至外部連接墊（封裝引腳）。該金屬線形成於前、後之訊號 層。 睛參照弟12A、12B圖，第一、第二半導體晶片η、i2 個別架設於彈性基板1 3之頂部以及底部。如第丨2A圖所 示’將弟一、第二半導體晶片11、12之位置互換，該第一 半導體晶片11之A1引腳設置於左侧（左方或後方）時，該第 一半導體晶片1 2之A1引腳設置於右側（右方或前方）時。 第一半導體晶片11之每一引腳以及對應之第二半導體 晶片引腳（具有相同功能）的兩關係彼此相反，且透過彈性 基板1 3之金屬線連接至對應之封裝引腳丨4。個別作用於第 一、第二半導體晶片11、1 2之一對引腳中只有一 至相對應之封裝引腳!4之一 腳連接 於第一、第二半導體晶片1 1、i 2個別架設於彈性基板 1 3上之後，該彈性基板1 3對摺以包覆該第二半導體晶^ 1 2，如此便形成如第4 A、4B圖所示之堆疊式半導體封裝
2130-6196-PF(N2);Uofung.ptd 第15頁 200427012 五、發明說明（ίο) 10。此時之該封裝引腳14以相同 腳21之方“及圖案設置。因此 可直接架設第一半導體晶片11於適用j 2體封裝10， 半導體晶片之基板之架設區可架設依』有：二：；設第- 記憶封裝。 又據有兩倍儲存容量之 接著說明有關第一、第一丰導 及外部連接墊。 弟一丰¥體晶片連接墊之連接以 第一、第二半導體晶片U、12之引 裝引腳14之選擇性引腳以及連接至固定：腳封 該連接至固定引腳之曰H a _你朱腳之日日片引腳。 板遠接至固定？丨^ 係透過VDD面板以及GND面 板連接至□ d腳’且該連接係透過 號層。晶片引腳透過訊铐厣H 」1 j汉/次後側之訊 引腳得以每針引：固定引腳，該訊號層之 引，係乂母對引腳互相面對並透過基板上形成之介声 Ϊίίί連接。為使上述之兩晶片間連接，該銲墊：下述 、請參照第13圖，於第一連接銲塾陣列中，每一連接至 ^丫：：^曰片引腳銲糊卜透過金屬線’訊號線） 連接至對應於k擇性引腳之外部連接銲墊5〇3，其中該金 屬線包括彈性基板1 3之前側訊號層。另外，第 陣列中，每一連接至選擇性引腳之晶片引 過金屬線505 (訊號線）連接至彈性基板13下表面區域54之 介層孔506 ’其中該金屬線包括彈性基板13之後侧訊號 層。該介層孔50 6連接至外部連接銲墊5〇7，而該外部連接 第16頁 2130-6196-PF(N2);Uofung.ptd 200427012 五、發明說明（π) —- 銲墊50 7則連接至對應之選擇性引腳。在此，每一金屬線 已括於後側之訊號層其透過連接該區域$ 4之介層孔以連接 至對應的外部連接銲墊。 请參照第1 4圖，於第一連接銲墊陣列該晶片引腳之銲 墊（VDD，VDDQ)6 02(僅顯示其一）透過該VDD基板6〇1之固定 引腳連接，而該VDD基板601透過介層孔6 03連接，而該介 層孔603向基底13之底部表面。該VDI)基板透過介層孔 604連接至對應之外部連接墊Mg。相同的，於第一連接銲 墊陣列中，該晶片引腳之銲墊6〇7(僅顯示一個為代表）透 過該0以0基板6 0 6之固定引腳連接，而該(^])基板6〇6透過介 層孔60 8^連接，而該介層孔6〇8向基底丨3之底部表面。另 外’於第二連接銲墊陣列該晶片引腳之銲墊6 〇 9 (僅顯示其 一）透過該VDD基板601之固定引腳連接，而該VDD基板6〇1 透過介層孔6 10連接，而該介層孔61〇向基底13之底部表 面。相同的’於第二連接銲墊陣列中，該晶片引腳之銲墊 601 (VSS，VSSQ)(僅顯示一個為代表）透過該GND基板6〇6之 固定引腳連接，而該GND基板60 6透過介層孔612連接，而 該介層孔612向基底13之底部表面。 在此’該與電源供應有關之銲墊（VDD，VDDQ)連接至 單一 VDD基板。VDD以及VDDQ可藉由分開同一層中之VDD基 板來個別打線。VDD、VDDQ亦可打線於前側訊號層及/或後 側訊號層之空的間隙中。此外，形成—VD1)、VDDq銲墊之 附加基板。該連接至GND平面之銲墊（VSS，VSSQ)可以相同 方式進行打線。
2130-6196-PF(N2);Uofung.ptd 第17頁 200427012 發明說明（12) 請參照第15圖’於第一連接墊陣列中，每一透過前側 訊號層及/或後側訊號層連接至固定引腳晶片之引腳之鲜 墊701(除該銲墊直接透過介層孔連接至底部表面之鲜塾者 之外）係透過金屬線（分支金屬線）703連接至介；孔7〇2而 形成於對應於第一、第二訊號銲墊之中間點附近，其中該 金屬線7 0 3包括别側訊5虎層。該第二連接塾陣列之對靡焊 塾704透過金屬線（分支金屬線）705連接至相同之介声孔 7 0 2 ’其中該金屬線7 0 5包括後側訊號層。而透過訊號層金 屬線連接至每一固定引腳之一對銲墊701、704係透過^層 孔7 0 2彼此連接’而形成於中間點附近。該連接至該對銲 墊701、704之介層孔702會進一步透過前側及/或後側之訊 號層的金屬線706或707連接至外部連接墊，以使其對應於 固定引腳。該分支金屬線703、705以及介層孔702彼此連 接並整個視為分支金屬線部份。根據上述結構，該分支金 屬線連接至彼此對應之連接墊（晶片引腳）的長度係大體彼 此相同的（在此範圍下不會產生實施上的問題）。 請參照第1 6圖，於第一連接銲墊陣列中，其他留下之 透過前侧及/或後側之訊號層連接至固定引腳之連接銲墊 801各透過介層孔803連接至該第二連接銲墊陣列後侧之連 接墊802。此乃因半導體晶片11、12之部份引腳功能可以 調換而不致產生任何問題。例如，每一半導體晶片11、1 2 之引腳以第9圖所示之功能設置，其中第一、第二半導體 晶片11、12之一的DQ0、DQ1、DQ2以及DQ3引腳對應於另一 晶片的DQ1、DQ0、DQ3以及DQ2。在此，每一半導體晶片之
2130-6196-PF(N2);Uofung.ptd 第18頁 200427012
DQO、DQ1、DQ2以及DQ3引腳可互換其功能，以便使該些相 互對應之引腳連接至相同之固定引腳且不產生問題。第一 2接墊陣列之每一連接墊8〇1可直接透過介層孔8〇3連接至 苐二連接墊陣列之連接墊8〇2，其中該第二連接墊陣列設 置於後侧底層。該一對透過介層孔8〇3彼此連接之連接墊 8〇2之一則透過前侧及/或後侧之訊號層的金屬線8〇4 二ς j連接至對應之固定引腳。於此例巾，當金屬線8 04或 士 同連接至分支金屬線部分時，該介層孔8 0 3形成一分 支金屬線部分。
、該可直接透過介層孔相連接之對應連接墊可因在設言 二ί產t之方便以不同方法相互連接。特別是，兩彼山 之ί接銲墊可透過介層孔連接，1述之方式形成方 獅*，之中間點附近。另外，前侧及/或後侧訊號層之引 =非直接連接，而係透過介層孔利用金屬線形成於不序 ^媒埶t銲墊透過介層孔直接連接時，此介層孔直接形居 銲墊墊 亦可視為該介層孔形成於銲墊附近而直接連福 ^ 著將"兒明第一、第二連接銲墊陣列以及其外部 t連，」特別是有關晶片連接至固定引腳之連接塾
萝> 第J7A圖，其係顯示彈性基板13之部分前侧1 就層（對應於第9圖之车莫轉曰 17A m ^ ^ ^ 口之牛蜍體日日片的金屬線A-D)。對應於 # 土板1 3之部分後側訊號層則顯示於1 7B圖。 弟m、17B圖中所顯示之彈性基板13係—上視圖。 "月多’b第1 7A圖，該第一半導體晶片之A8引腳的連4
200427012 五、發明說明（14) 墊’透過前側金屬線7 1 (分支金屬線）連接至介層孔7 2。另 外，如第1 7B圖所示，該第二半導體晶片之A8引腳的連接 塾’透過後側金屬線7 3 (分支金屬線）連接至介層孔7 2。在 此’該介層孔72形成於兩半導體晶片之A8引腳的連接墊之 中間點附近，以便使金屬線71、7 3之長度彼此相同。形成 長度彼此相同之金屬線71、7 3以作為傳輸線（為使其電阻 相當）。該介層孔7 2更透過後側訊號層之金屬線（共用金屬 線）74連接至形成於該區域54之底部表面的介層孔75並連 接至該A8封裝引腳的銲墊。
與A8引腳的連接塾相同，該第一、第二半導體晶片之 B3引腳的連接墊透過一介層孔76相互連接，其中該介層孔 76形成於兩半導體晶片之連接墊的中間點附近。與人8引腳 的介層孔72不同的是，該介層孔76透過前側訊號層之訊號 線77連接至該B3封裝引腳的銲墊。 與A8引腳的連接墊相同，該對應於第一以及二半導體 晶片之B7引腳之連接墊連接至β7封裝引腳後侧之介層孔 、D3的 部封裝 D3的連 後側之 、請參照第17A圖，該第一半導體晶片之引腳C2 連接銲墊’透過讯唬層前侧之金屬線個別連接至外
引腳C8、D7的連接墊。在此未圖解說明該引腳c2、 $墊，透過介層孔個別直接連接該第二半導 C8、B7引腳。 C2 ' "3 *"Α
2130-6196-PF(N2);Uofung.ptd 第20頁 ZUU427012 五、發明說明（15) = ;=2、、D3的介層孔。在此未圖解說明該引腳 側之C8、R7 /透過介層孔個別連接該第—帛導體晶片後 w m B7引腳。 由介ΐίΓΓ基板之鲜塾（仓⑷1引聊之連接塾）乃直接 之銲&。 至¥1)1)基板，此方式亦應用於連接至GND基板 連接至選擇性引腳之晶Η腳之連接墊係透過前側及 二後側之訊號層的金屬線’以相同於第一、第二半導體 日日片之引腳C2、D3的連接銲墊方式連接。 盔且ί著°兒明於彈性基板上形成金屬線。該彈性基板13 irL 金屬線及/或一能量供應金屬線之複數層基 报藤4 σ卩分（甚或全部）訊號金屬線圖案與基板及/或能量 =板：？構成傳輸線（或金屬線）。請參照第18_21圖， ,、糸顯：藉由每一金屬線圖案形成之不同的傳輸線結構。 18Α、18Β圖所示，該傳輸線可為微帶線，包括： 金屬線圖案81，以及—鄰接於該訊號金屬線圖案81 $基板及/或能量供應板（平面金屬線)82。接著，請參照 ^19Α、19Β圖所示，該傳輸線可為一帶、線，包括：一訊號 金屬線圖案81 ’卩及一對鄰接於該訊號金屬線圖㈣之對 應侧基板及/或能量供應板（平面金屬線）82a&/482b。如 :20A、20B圖所示’該傳輸線可為平行線包括：一訊號金 属線圖案81 ’以及一基板及/或能量供應金屬線（平面金屬 線）83，該基板及/或能量供應金屬線（平面金屬線）83沿著 與訊號金屬線圖案之一側（或對應侧）平行延伸。上述之傳 200427012
五、發明說明（16) 輸線結構適當選擇並結合以形成訊號金屬圖案。 該基板及/或能量供應板（平面金屬線）82'、82a以及 82b形成寬度不小於訊號金屬圖案之微帶線或帶線。 請參照第21A圖，該基板及/或能量供應板（平面金屬 線）91、92形成之傳輸線包括複數個基板部分及/或電源供 應金屬板部分（平板）。 “ 请參照第2 1 B圖，該基板及/或能量供應板（平面金屬 線）82、82a以及82b形成之傳輸線可由介層孔95及/或 金屬線9 6部分分隔。 〆
雖然本發明已以較佳實施例揭露如上，然盆並非用t 限定本發明，任何熟習此項技藝者，在不脫離二發明之来 神和範圍内，當可作更動與潤飾，因此本 ^ 當視後附之中請專利範圍所界定者為準。 例如’上述之說明中該封裝引腳與第_ 腳以垂直方向對準。請參照第22圖，該封裝引腳可;:备 =少共用金屬線之長度。請參照第23 “及23β圖，= ς引腳之排列亦可與第一半導體晶片引腳之排列相當不
200427012 圖式簡單說明 第1圖係繪示出傳統堆疊半導 y圖係緣示出另—傳統堆；=，圖； 第3圖係繪示出用於第2圖之堆聂_、曾#衣剖面圖，· 晶片以及一彈性基板分解圖； $ V體封裝之半導體 第4 A、4B圖係各自繪示出根掳 導體封裝之透視圖以及上視圖。 X明貫施例之堆疊半 第5圖係繪示出具有一傳統封姓 面圖； ϋ構之半導體晶片剖 剖面圖； 苐6圖係緣示出具有另一傳統封姓 si ： 对裝…構之半導體晶片 片剖Γ:係緣示*具有再另一傳統封裝結搆之半導 半導第4A、4B*中用於…導想封裝 體晶 之 ^ η圖Λ繪^第8圖中之半導體晶片之引腳配置圖； 置圖=10圖係繪示出第4Α、4Β圖中之半導體晶片之引腳配 ，係繪示出第4Α、4Β圖中用於堆 弹性基板透視圖； 山第12Α、12Β圖係各自繪示出第4Α、“圖半導體晶片鑲 肷於彈性基板前之透視圖以及垂直剖面圖； 、第1 3圖係繪示出有關第1 1圖之彈性基板上的選擇引腳 連接剖面圖； 第14圖係繪示出有關第U圖之彈性基板中之VDD平面 2130-6196-PF(N2);Uofung.ptd 圖式簡單說明 連接剖面圖； 圖之彈性基板上固定引腳連 第15圖係繪示出有闕第U 接剖面圖； 第Ϊ6圖係繪示出銲墊間藉 層孔直接相互連接剖面圖； 弟1圖之彈性基板中之介 弟1 7 A 1 B圖係綠示出彈性美 :晶片連接銲墊陣列與外部二：連接部❾’各為第 第二晶片連接銲墊陣列以及連接至外:間）連接，以及 層孔間之連接。 卜σ卩連接銲塾陣列之介 線之傳輸線的透 做為微帶線之傳輸線的 微帶線之傳輸線 、i F1第二A 18β圖係各自繪示出做為微帶 視圖以及縱向圖； f 第19A、19B係各自繪示出另 透視圖以及縱向圖； 的读、2°β圖係各自繪示出再-做為 的透視圖以及縱向圖； 第21Α圖係繪示出包括複數個 分之能量供應板透視圖； 敬及/或此里供應板部 第21B圖係繪示出另一句括遂 板部分之能量供應板透視二括複數個基板及/或能量供應 剖面^ 2 2圖係繪不出根據本發明之改良式堆疊半導體封裝 丰藤231!圖係各自繪示出根據本發明之改良式堆疊 半v體封裝之剖面圖以及透視圖。 200427012 圖式簡單說明 【符號說明】 1 0〜堆疊式半導體封裝； 1 1〜第一半導體晶片 12〜第二半導體晶片； 1 3〜彈性基板； 14〜封裝引腳； 21〜晶片引腳； 5 1〜晶片架設區； 52〜上表面區域； 53〜下表面區域； 54〜下表面區域； 7 1〜前側金屬線； 7 2〜介層孔； 73〜後側金屬線； 74〜共用金屬線； 7 5〜介層孔； 7 6〜介層孔； 7 7〜訊號線； 7 8〜介層孔； 8 1〜訊號金屬線圖案； 9 5〜介層孔； 9 6〜金屬線； 1 0 1〜凹處； 1 0 2〜基板； 1 0 3〜導線圖案； 104〜半導體晶片； 1 〇 5〜金屬線； 106〜末端銲塾； 1 0 7〜鲜錫球； 111〜半導體晶片； 11 2〜彈性基板； 1 2 2〜第一傳導銲墊陣列； 1 2 1〜接點； 2 0 1〜基板； 2〇2〜元素晶片； 203〜銲墊； 301〜基板； 3 0 2〜元素晶； 3 0 3〜銲塾； 4 0 2〜保護層； 403〜重裝電線層； 404〜銅柱； 4 0 5〜樹脂模型； 5 0 2〜金屬線； 5 0 3〜外部連接銲墊； 5 0 5〜金屬線； 5 0 6〜介層孔；
2130-6196-PF(N2);Uofung.ptd 第25頁
200427012 圖式簡單說明 507〜外部連接銲墊； 601 60 2〜銲墊； 603 604〜介層孔； 605 6 0 6 〜GND 基板； 607 608〜介層孔； 609 6 1 0〜介層孔； 611 6 1 2〜介層孔； 701 702〜介層孔； 703 704〜銲墊； 705 801〜連接墊； 802 803〜介層孔； 804 82〜基板及/或能量供應板；805 91〜基板及/或能量供應板 92〜基板及/或能量供應板 7 0 6〜前側訊號層之金屬線 7 0 7〜後側訊號層之金屬線 82a〜基板及/或能量供應板； 82b〜基板及/或能量供應板； 8 3〜基板及/或能量供應金屬線； 5 0 1〜選擇性引腳之晶片引腳銲墊 504〜選擇性引腳之晶片引腳銲墊 VDD基板； 介層孔； 外部連接墊 鲜墊 銲墊 銲墊 銲墊 分支金屬線 分支金屬線 連接墊； 金屬線， 金屬線；
2130-6196-PF(N2);Uofung.ptd 第26頁

Claims (1)

  1. 200427012 六、申請專利範圍 一 »1· 一種堆疊式半導體封裝，包括一基底，具有第一以 及第一相互對應之表面，以及第一以及第二半導體晶片， 每一該晶片具有一架設表面以於一預定之圖案中提供複數 個，片引腳設置，該第一以及第二半導體晶片被各自架設 於第一以及第二之基板表面，以使該架設表面隔著插入其 間之該基板相互對應。 2 ·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中該基板具有各自對應於複數個封裝引腳之該晶片引 腳’並形成於不同於一晶片架設區之第一或第二表面，以 將第一、第二半導體晶片架設好。 3 ·如申請專利範圍第2項所述之堆疊式半導體封裝， 其中該封裝引腳以完全相同於一預定之圖案配置。 4 ·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中該封裝引腳包括一連接至與其對應之第一、第二半導 體晶片之晶片引腳，且固定引腳與對應於第一、第二半導 體晶片之引腳連接。 5·如申請專利範圍第4項所述之堆疊式半導體封裝， 其中： 該基板具有一共用之金屬線，其中該連線一端連接至 該固定引腳以及一分支之金屬線部分，其中該連線連接其 他共用金屬線之端點至兩晶片引腳’以作為對應該第一、 第二半導體晶片之晶片引腳； 由該共用金屬一端至對應之該晶片引腳之金屬線長 度，大體上相同於該共用金屬一端至另一對應之該晶片引
    2130-6196-PF(N2) ;Uofung.ptd 第27頁 200427012
    項所述之堆豐式半導體封裝 6·如申請專利範圍第5 其中： 該刀支金屬線部份句技 人® 7丨 VX- > 不曰μ ?丨π、” 匕括一；丨層孔’該介層孔形成於苛 窨日日—Ρ以連接至共用金屬線之其他端點之間之位〜 置’而弟一：第二分支金屬線之長度彼此相同。 7.如申明專利範圍第1項所述之堆疊 其中對應於該固定引g之兮；曰^ ^ =疋刟角之該兩晶片引角透過基板相互面 對，該为支金屬線具有一直接連接至兩晶片引角之介芦 孔。， 9 8·如申請專利範圍第丨項所述之堆疊式半導體封裝， 其中該基底係一多層基底，其具有一基層板及/或一能源 供應板，而該共用金屬線以及該分支金屬線部份各自與基 層板及/或爿b源供應板形成一傳輸線。 9·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中該傳輸線包括任一微帶線（micr〇strip line)、帶線 (strip 1 ine)以及一平行埠。 、 1 0 ·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中該基層板及/或電源供應板包括由複數個基層板及/或 電源供應板形成之部分或由一介層孔或另一金屬線部分隔 離之部分。 11 ·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中該半導體晶片係一元素晶片（裸晶），該晶片具有一架 設元素晶片於一基板上之封裝結構，電性連接元素晶片以
    2130-6196-PF(N2);Uofung.ptd 第28頁 200427012 六、申請專利範圍 及基板上之金屬線（銲墊），其中該連接方式包括，銲線、 内引腳接合（inner lead bounding)、覆晶連接 (flip - chip connection)及其他類似方式，接著將該晶片 以及該基板封於樹脂模型中以保護基板上之導體圖案 晶圓級CSP或晶圓製程封裝。
    2130-6196-PF(N2);Uofung.ptd 第29頁
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US20040227222A1 (en) 2004-11-18
CN1531087A (zh) 2004-09-22
JP4072505B2 (ja) 2008-04-09
US20070001299A1 (en) 2007-01-04
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US7642635B2 (en) 2010-01-05

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