WO2022160415A1 - 一种半导体封装结构及其制造方法、半导体器件 - Google Patents

一种半导体封装结构及其制造方法、半导体器件 Download PDF

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Publication number
WO2022160415A1
WO2022160415A1 PCT/CN2021/079315 CN2021079315W WO2022160415A1 WO 2022160415 A1 WO2022160415 A1 WO 2022160415A1 CN 2021079315 W CN2021079315 W CN 2021079315W WO 2022160415 A1 WO2022160415 A1 WO 2022160415A1
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Prior art keywords
chip
layer
bottom edge
metal layer
board
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PCT/CN2021/079315
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English (en)
French (fr)
Inventor
曹立强
胡文华
Original Assignee
华进半导体封装先导技术研发中心有限公司
上海先方半导体有限公司
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Publication of WO2022160415A1 publication Critical patent/WO2022160415A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging structure, a manufacturing method thereof, and a semiconductor device.
  • the present application provides a semiconductor package structure, a manufacturing method thereof, and a semiconductor device to solve the problem of interconnection between different chips on the same layer of the system-level semiconductor package structure, and the problem that the wiring area of the plane interconnection line affects the miniaturization of the package structure.
  • the application provides a semiconductor packaging structure, comprising: a plastic sealing layer; a first interconnecting structure layer, the first interconnecting structure layer is located on one side surface of the plastic sealing layer, the first interconnecting structure layer includes a first metal layer; an adapter plate, an adapter plate Located in the plastic sealing layer, the extended plane of the board body is perpendicular to the first interconnecting structure layer, the transfer board has a metal layer of the transfer board, and the metal layer of the transfer board is connected to the first metal layer; the first chip, the first chip is located in the first The surface of the interconnect structure layer facing the side of the plastic encapsulation layer, the first chip is connected to the first metal layer, and the plastic encapsulation layer covers the first chip; the second chip, the second chip is located on the surface of the first interconnect structure layer facing the side of the plastic encapsulation layer, the first chip The two chips are connected to the first metal layer, and the plastic encapsulation layer covers the second chip; the first chip and the second chip are different types of chips,
  • the adapter board includes a board body, the board body has opposite first surfaces and second surfaces, the first surface and the second surface are respectively the two surfaces with the largest area among the surfaces of the board body, and the first surface is perpendicular to the surface.
  • a bottom edge pin is connected to the first metal layer; a plurality of first bottom edge pins are also connected to the metal layer of the adapter board; the second surface has a second bottom edge, and the second surface is provided with a plurality of The second bottom edge pins, a plurality of second bottom edge pins are connected to the first metal layer; the plurality of second bottom edge pins are also connected to the metal layer of the transition board.
  • a plurality of first bottom edge pins are arranged parallel to the first bottom edge, and a plurality of second bottom edge pins are arranged parallel to the second bottom edge.
  • the number of the first chips is multiple; and/or the number of the second chips is multiple.
  • the first surface is further provided with multiple contacts
  • the second surface is further provided with multiple contacts
  • the metal layer of the adapter plate connects the multiple contacts on the first surface and the multiple contacts on the second surface
  • the first surface is provided with There is a third element, the third element is connected to the metal layer of the adapter board through the contacts on the first surface; and/or, the second surface is provided with a third element, and the third element is connected to the metal layer of the adapter board through the contacts on the second surface;
  • the third element is a passive device or chip.
  • the present application also provides a method for manufacturing a semiconductor packaging structure, comprising the following steps: forming a plastic sealing layer; forming a first interconnecting structure layer, the first interconnecting structure layer is located on one side surface of the plastic sealing layer, and the first interconnecting structure layer includes a first metal layer ; Set up an adapter plate, the adapter plate is located in the plastic sealing layer, the plane of the board body extension is perpendicular to the first interconnect structure layer, the adapter plate has a metal layer of the adapter plate, and the metal layer of the adapter plate is connected to the first metal layer; A first chip is installed, the first chip is located on the surface of the first interconnect structure layer facing the plastic packaging layer, the first chip is connected to the first metal layer, and the plastic packaging layer covers the first chip; the second chip is mounted, and the second chip is located on the first chip A surface of the interconnect structure layer facing the side of the plastic encapsulation layer, the second chip is connected to the first metal layer, and the plastic encapsulation layer covers the second chip
  • the adapter board includes a board body, the board body has opposite first surfaces and second surfaces, the first surface and the second surface are respectively the two surfaces with the largest area among the surfaces of the board body, and the first surface is perpendicular to the surface.
  • a first interconnection structure layer the second surface is perpendicular to the first interconnection structure layer; the first surface has a first bottom edge
  • the manufacturing method of the semiconductor package structure includes the following steps: forming on the side of the first bottom edge of the first surface a plurality of first bottom edge pins, the plurality of first bottom edge pins are connected to the first metal layer; the plurality of first bottom edge pins are also connected to the metal layer of the adapter board; the second surface has a second bottom edge, and the semiconductor package
  • the manufacturing method of the structure includes the following steps: forming a plurality of second bottom edge pins on one side of the second bottom edge of the second surface, and the plurality of second bottom edge pins are connected to the first metal layer; a plurality of second bottom edge pins The edge pin
  • the manufacturing method of the semiconductor package structure includes the following steps in sequence: providing a substrate, forming a plurality of metal bumps on the substrate; connecting a plurality of first bottom edge pins and a plurality of second bottom edges of the interposer.
  • the feet are welded to the first substrate through a plurality of metal bumps; the first chip and the second chip are respectively mounted on the substrate; a plastic packaging layer is formed, and the plastic packaging layer covers the first chip, the second chip and the transfer board; and the substrate is removed;
  • a first interconnect structure layer is formed, and the first interconnect structure layer covers the surface facing the substrate side before the first chip, the surface facing the substrate side before the second chip, the surface facing the substrate side before the interposer, and the plastic sealing layer.
  • a surface on one side of the substrate; solder balls are formed on the side of the first interconnect structure layer facing away from the plastic encapsulation layer, and the solder balls are connected to the first metal layer.
  • the manufacturing method of the semiconductor package structure further includes the following steps: forming a plurality of contacts on the first surface, forming a plurality of contacts on the second surface, and connecting the plurality of contacts on the first surface and the second surface with the metal layer of the interposer board multiple contacts; attach the third component to the first surface, the third component is connected to the metal layer of the interposer through the contacts on the first surface; and/or, attach the third component to the second surface, the third component The interposer metal layer is connected through the contacts on the second surface.
  • the present application also provides a semiconductor device including the above semiconductor package structure.
  • the semiconductor packaging structure of the present application through the setting of the adapter plate perpendicular to the first interconnect structure layer, makes the adapter plate stand in the plastic sealing layer on the first interconnect structure layer, and the first chip on both sides of the adapter plate And the second chip is interconnected through the first metal layer and the transition board.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.
  • the semiconductor package structure of the present application is connected to the first metal layer through a first bottom edge pin and a second bottom edge pin, and a plurality of first bottom edge pins and a plurality of second bottom edge pins are respectively connected
  • the arrangement of the adapter plate realizes the vertical position of the adapter plate, and on the other hand, the first chip and the second chip on both sides of the adapter plate are interconnected through the first metal layer and the adapter plate.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the semiconductor package structure in the horizontal direction.
  • a plurality of first bottom edge pins are arranged parallel to the first bottom edge, and a plurality of second bottom edge pins are arranged parallel to the second bottom edge.
  • the pins arranged in parallel are easy to realize the balance of welding, which can avoid the disconnection of individual pins due to uneven welding.
  • a plurality of contacts for connecting the metal layer of the adapter plate are arranged on the first surface and the second surface, and a third element can also be arranged on the first surface and/or the second surface of the adapter plate, The third element is connected to the metal layer of the adapter board through the contact point, which can realize interconnection with other elements in the package structure and fan-out on the same side, which is beneficial to improve the integration degree of the device.
  • the semiconductor package structure manufactured by the manufacturing method of the semiconductor package structure provided by the present application through the setting of the adapter plate perpendicular to the first interconnect structure layer, so that the adapter plate is vertically placed in the plastic sealing layer on the first interconnect structure layer,
  • the first chip and the second chip on both sides of the transfer board are interconnected through the first metal layer and the transfer board.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.
  • the semiconductor package structure manufactured by the manufacturing method of the semiconductor package structure provided by the present application is formed by forming a plurality of first bottom edge pins and a plurality of second bottom edge pins, and the first bottom edge pins and the second bottom edge are connected to each other.
  • the pins are connected to the first metal layer, and the metal layer of the adapter plate is connected to the plurality of first bottom edge pins and the plurality of second bottom edge pins, on the one hand, the vertical position of the adapter plate is realized, and on the other hand, the transfer board is installed.
  • the first chip and the second chip on both sides of the connecting board are interconnected through the first metal layer and the connecting board.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the semiconductor package structure in the horizontal direction.
  • a third element can also be arranged on the first surface and/or the second surface of the adapter board, The third element is connected to the metal layer of the adapter board through the contact point, which can realize interconnection with other elements in the package structure and fan-out on the same side, which is beneficial to improve the integration degree of the device.
  • the semiconductor device provided by this application includes the above-mentioned semiconductor packaging structure, through the setting of the adapter plate perpendicular to the first interconnect structure layer, so that the adapter plate is vertically placed in the plastic sealing layer on the first interconnect structure layer, and the adapter plate is connected.
  • the first chip and the second chip on both sides of the board are interconnected through the first metal layer and the transition board.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.
  • FIGS. 1-7 are schematic diagrams of various states in a manufacturing process of a semiconductor package structure in an embodiment of the present application.
  • 3 is a side view of one side of the first surface of the adapter plate
  • FIG. 7 is a schematic structural diagram of a semiconductor package structure in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a semiconductor package structure in another embodiment of the present application.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect.
  • this embodiment provides a semiconductor packaging structure, including:
  • Plastic encapsulation layer 400 is plastic encapsulation layer 400 .
  • the first interconnection structure layer 500 is located on one side surface of the plastic encapsulation layer 400 , and the first interconnection structure layer 500 includes a first metal layer 501 and a first insulating medium layer 502 .
  • the adapter plate 300, the adapter plate 300 is located in the plastic sealing layer 400, the plane of the adapter plate 300 itself is perpendicular to the first interconnection structure layer 500, and the adapter plate 300 has an adapter plate metal layer (not shown in the figure) , the transition board metal layer is connected to the first metal layer 501 .
  • the first chip 100 is located on the surface of the first interconnect structure layer 500 facing the plastic encapsulation layer 400 , the first chip 100 is connected to the first metal layer 501 , and the plastic encapsulation layer 400 covers the first chip 100 .
  • the second chip 200 is located on the surface of the first interconnect structure layer 500 facing the plastic encapsulation layer 400 , the second chip 200 is connected to the first metal layer 501 , and the plastic encapsulation layer 400 covers the second chip 200 .
  • the first chip 100 and the second chip 200 are different types of chips, and the first chip 100 and the second chip 200 are located on two sides of the interposer board 300 respectively.
  • the first chip 100 and the second chip 200 may be a field programmable gate array (FPGA) chip and a double rate synchronous dynamic random access memory (DDR) chip, respectively.
  • FPGA field programmable gate array
  • DDR double rate synchronous dynamic random access memory
  • the interposer board 300 is arranged perpendicular to the first interconnect structure layer 500 , so that the interposer board 300 is vertically placed in the plastic sealing layer 400 on the first interconnect structure layer 500 .
  • the first chip 100 and the second chip 200 on the side are interconnected through the first metal layer 501 and the interposer 300 .
  • the wiring process of the adapter board 300 can achieve higher precision and smaller line width and line spacing than the dense wiring process of the plane interconnection line, it can achieve higher precision than the plane interconnection line. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.
  • the adapter board 300 includes a board body 301 , the board body 301 has opposite first and second surfaces, and the first surface and the second surface are respectively a board body Of the two surfaces with the largest areas, the first surface is perpendicular to the first interconnect structure layer 500 ; the second surface is perpendicular to the first interconnect structure layer 500 .
  • the first surface has a first bottom edge, a plurality of first bottom edge pins 3021 are disposed on one side of the first bottom edge, and the plurality of first bottom edge pins 3021 are connected to the first metal layer 501; A bottom edge pin 3021 is also connected to the metal layer of the adapter board.
  • the second surface has a second bottom edge, a plurality of second bottom edge pins 3022 are disposed on one side of the second bottom edge, and the plurality of second bottom edge pins 3022 are connected to the first metal layer 501; The two bottom pins 3022 are also connected to the metal layer of the transition board.
  • the first bottom edge pins 3021 and the second bottom edge pins 3022 are connected to the first metal layer 501 , and the plurality of first bottom edge pins 3021 and the plurality of second bottom edge pins 3022 are respectively connected to the riser board 300
  • the adapter board 300 is set upright, and on the other hand, the first chip 100 and the second chip 200 on both sides of the adapter board 300 are interconnected through the first metal layer 501 and the adapter board 300 .
  • the wiring process of the adapter board 300 can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can realize more accurate wiring than plane interconnection lines. High density and occupy a smaller area.
  • the adapter board 300 since the adapter board 300 is erected, the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the semiconductor package structure in the horizontal direction. .
  • first bottom edge pins 3021 are arranged parallel to the first bottom edge
  • second bottom edge pins 3022 are arranged parallel to the second bottom edge.
  • the pins arranged in parallel are easy to realize the balance of welding, which can avoid the disconnection of individual pins due to uneven welding.
  • the number of the first chips 100 may be multiple; and/or the number of the second chips 200 may be multiple.
  • the first surface is further provided with a plurality of contacts 303
  • the second surface is further provided with a plurality of contacts 303
  • the metal layer of the adapter plate connects the contacts 303 on the first surface and the second surface A plurality of contacts 303 on the surface.
  • the first surface is provided with a third element 700, and the third element 700 is connected to the metal layer of the interposer through the contacts 303 on the first surface; and/or, the second surface is provided with a third element 700, and the third element 700 passes through the second surface
  • the contact 303 is connected to the metal layer of the adapter board.
  • the third element 700 may be a passive device or a chip.
  • a plurality of contacts for connecting the metal layers of the interposer are provided on the first surface and the second surface, and a third element 700 can also be provided on the first surface and/or the second surface of the interposer, and the third element 700 is connected by the contacts 303
  • the metal layer of the transition board can realize interconnection with other components in the package structure and fan-out on the same side, which is beneficial to improve the integration of the device.
  • the present embodiment provides a method for manufacturing a semiconductor package structure, including the following steps:
  • a plastic encapsulation layer 400 is formed.
  • a first interconnection structure layer 500 is formed, the first interconnection structure layer 500 is located on one side surface of the plastic sealing layer 400 , and the first interconnection structure layer 500 includes a first metal layer 501 and a first insulating medium layer 502 .
  • An adapter plate 300 is provided, the adapter plate 300 is located in the plastic sealing layer 400 , the plane of the adapter plate 300 extending itself is perpendicular to the first interconnect structure layer 500 , the adapter plate 300 has an adapter plate metal layer, and the adapter plate metal layer The first metal layer 501 is connected.
  • the first chip 100 is mounted.
  • the first chip 100 is located on the surface of the first interconnect structure layer 500 facing the plastic packaging layer 400 , the first chip 100 is connected to the first metal layer 501 , and the plastic packaging layer 400 covers the first chip 100 .
  • the second chip 200 is mounted.
  • the second chip 200 is located on the surface of the first interconnect structure layer 500 facing the plastic packaging layer 400 , the second chip 200 is connected to the first metal layer 501 , and the plastic packaging layer 400 covers the second chip 200 .
  • the first chip 100 and the second chip 200 are different types of chips, and the first chip 100 and the second chip 200 are located on two sides of the adapter board 300 respectively.
  • the first chip 100 and the second chip 200 may be a field programmable gate array (FPGA) chip and a double rate synchronous dynamic random access memory (DDR) chip, respectively.
  • FPGA field programmable gate array
  • DDR double rate synchronous dynamic random access memory
  • the adapter board 300 includes a board body 301 , and the board body 301 has a first surface and a second surface opposite to each other.
  • the first surface and the second surface are respectively the two surfaces with the largest area among the surfaces of the board body 301 .
  • the first surface is perpendicular to the first interconnect structure layer 500
  • the second surface is perpendicular to the first interconnect structure layer 500 .
  • the interposer 300 is arranged perpendicular to the first interconnect structure layer 500, so that the interposer 300 is vertically placed in the plastic sealing layer 400 on the first interconnect structure layer 500,
  • the first chip 100 and the second chip 200 on both sides of the connecting board 300 are interconnected through the first metal layer 501 and the connecting board 300 .
  • the wiring process of the adapter board 300 can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can realize more accurate wiring than plane interconnection lines. High density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.
  • the first surface has a first bottom edge
  • the manufacturing method of the semiconductor package structure further includes the following steps: forming a plurality of first bottom edge pins 3021 on one side of the first bottom edge of the first surface;
  • the first bottom edge pins 3021 are connected to the first metal layer 501;
  • the plurality of first bottom edge pins 3021 are also connected to the metal layer of the adapter board,
  • the second surface has a second bottom edge
  • the manufacturing method of the semiconductor package structure further includes the following steps: forming a plurality of second bottom edge pins 3022 on one side of the second bottom edge of the second surface, and the plurality of second bottom edge contacts
  • the pins 3022 are connected to the first metal layer 501 .
  • the plurality of second bottom pins 3022 are also connected to the metal layer of the riser board.
  • first bottom edge pins 3021 and the second bottom edge pins 3022 are connected to the first metal layer 501, and the board metal
  • the interconnection with the second chip 200 is achieved through the first metal layer 501 and the interposer board 300 .
  • the wiring process of the adapter board 300 can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can realize more accurate wiring than plane interconnection lines. High density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the semiconductor package structure in the horizontal direction.
  • the manufacturing method of the semiconductor package structure includes the following steps in sequence:
  • a substrate 0001 is provided on which a plurality of metal bumps 0002 are formed.
  • a plurality of first bottom-side pins 3021 and a plurality of second bottom-side pins 3022 of the interposer board 300 are soldered to the first substrate 0001 through a plurality of metal bumps 0002 .
  • the first chip 100 and the second chip 200 are respectively mounted on the substrate 0001 .
  • a plastic sealing layer 400 is formed, and the plastic sealing layer 400 covers the first chip 100 , the second chip 200 and the interposer 300 .
  • the substrate 0001 is removed.
  • a first interconnect structure layer 500 is formed.
  • the first interconnect structure layer 500 covers the surface of the first chip 100 facing the substrate 0001 side, the surface of the interposer 300 facing the substrate 0001 side, and the plastic sealing layer 400 facing the surface. The surface of the substrate 0001 side.
  • solder balls 600 are formed on the side of the first interconnect structure layer 500 facing away from the molding layer 400 , and the solder balls 600 are connected to the first metal layer.
  • the manufacturing method of the semiconductor package structure further includes the following steps:
  • a plurality of contacts 303 are formed on the first surface, a plurality of contacts 303 are formed on the second surface, and the interposer metal layer connects the plurality of contacts 303 on the first surface and the plurality of contacts 303 on the second surface.
  • the third component 700 is connected to the metal layer of the interposer board through the contacts 303 on the first surface; and/or,
  • the third component 700 is mounted on the second surface, and the third component 700 is connected to the interposer metal layer through the contact 303 on the second surface.
  • a third element 700 can also be provided on the first surface and/or the second surface of the adapter board 300, and the third element 700 is connected to the metal layer of the adapter board through the contacts 303, The interconnection with other components in the package structure and the fan-out on the same side can be realized, which is beneficial to improve the integration degree of the device.
  • This embodiment provides a semiconductor device, including the semiconductor package structure in the above-mentioned Embodiment 1.
  • the adapter plate perpendicular to the first interconnect structure layer, the adapter plate is vertically placed in the plastic encapsulation layer on the first interconnect structure layer, and the first chip and the second chip on both sides of the adapter plate pass through the first metal layer. It is interconnected with the adapter board.
  • the interconnection board wiring process can achieve higher precision and smaller line width and line spacing than the dense wiring process of plane interconnection lines, it can achieve higher precision than plane interconnection lines. density and occupy a smaller area.
  • the wiring in the horizontal direction of the plane is changed to the vertical direction, which can reduce the area occupied by the wiring area, which is beneficial to the miniaturization of the package structure in the horizontal direction.

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Abstract

一种封装结构和半导体器件，半导体封装结构包括：塑封层（400）；第一互联结构层（500），第一互联结构层（500）位于塑封层（400）一侧表面，第一互联结构层（500）包括第一金属层（501）；转接板（300），转接板（300）位于塑封层（400）中，板体延展的平面垂直于第一互联结构层（500），转接板（300）内具有转接板金属层，转接板金属层连接第一金属层（501）；第一芯片（100），第一芯片（100）位于第一互联结构层（500）朝向塑封层（400）一侧的表面，第一芯片（100）连接第一金属层（501），塑封层（400）包覆第一芯片（100）；第二芯片（200），第二芯片（200）位于第一互联结构层（500）朝向塑封层（400）一侧的表面，第二芯片（200）连接第一金属层（501），塑封层（400）包覆第二芯片（200）；第一芯片（100）和第二芯片（200）为不同种类的芯片，第一芯片（100）和第二芯片（200）分别位于转接板（300）的两侧。

Description

一种半导体封装结构及其制造方法、半导体器件 技术领域
本申请涉及半导体封装技术领域，具体涉及一种半导体封装结构及其制造方法、半导体器件。
背景技术
系统级封装的半导体封装结构中，同层的不同芯片通常需要高密度互联。通常的做法是通过多条平面互联线密集布线实现互联。但是这样的做法需要多层布线，由于工艺的限制线宽线距较大，使得布线区域在封装结构的水平面上占据较大的面积，不利于封装结构水平方向上的小型化。
发明内容
因此，本申请提供一种半导体封装结构及其制造方法、半导体器件，以解决系统级半导体封装结构同层的不同芯片之间互联，平面互联线的布线区影响封装结构的小型化的问题。
本申请提供一种半导体封装结构，包括：塑封层；第一互联结构层，第一互联结构层位于塑封层一侧表面，第一互联结构层包括第一金属层；转接板，转接板位于塑封层中，板体延展的平面垂直于第一互联结构层，转接板内具有转接板金属层，转接板金属层连接第一金属层；第一芯片，第一芯片位于第一互联结构层朝向塑封层一侧的表面，第一芯片连接第一 金属层，塑封层包覆第一芯片；第二芯片，第二芯片位于第一互联结构层朝向塑封层一侧的表面，第二芯片连接第一金属层，塑封层包覆第二芯片；第一芯片和第二芯片为不同种类的芯片，第一芯片和第二芯片分别位于转接板的两侧。
可选的，转接板包括板体，板体具有相对的第一表面和第二表面，第一表面和第二表面分别为板体各个表面中面积最大的两个表面，第一表面垂直于第一互联结构层；第二表面垂直于第一互联结构层；第一表面具有第一底边，第一表面在第一底边一侧设置有多个第一底边接脚，多个第一底边接脚连接第一金属层；多个第一底边接脚还连接转接板金属层；第二表面具有第二底边，第二表面在第二底边一侧设置有多个第二底边接脚，多个第二底边接脚连接第一金属层；多个第二底边接脚还连接转接板金属层。
可选的，多个第一底边接脚平行于第一底边排列，多个第二底边接脚平行于第二底边排列。
可选的，第一芯片的数量为多个；和/或，第二芯片的数量为多个。
可选的，第一表面还设置有多个接点，第二表面还设置有多个接点，转接板金属层连接第一表面的多个接点和第二表面的多个接点；第一表面设置有第三元件，第三元件通过第一表面的接点连接转接板金属层；和/或，第二表面设置有第三元件，第三元件通过第二表面的接点连接转接板金属层；
可选的，第三元件为无源器件或芯片。
本申请还提供一种半导体封装结构的制造方法，包括以下步骤：形成 塑封层；形成第一互联结构层，第一互联结构层位于塑封层一侧表面，第一互联结构层包括第一金属层；设置转接板，转接板位于塑封层中，板体延展的平面垂直于第一互联结构层，转接板内具有转接板金属层，转接板金属层连接第一金属层；贴装第一芯片，第一芯片位于第一互联结构层朝向塑封层一侧的表面，第一芯片连接第一金属层，塑封层包覆第一芯片；贴装第二芯片，第二芯片位于第一互联结构层朝向塑封层一侧的表面，第二芯片连接第一金属层，塑封层包覆第二芯片；其中第一芯片和第二芯片为不同种类的芯片，第一芯片和第二芯片分别位于转接板的两侧。
可选的，转接板包括板体，板体具有相对的第一表面和第二表面，第一表面和第二表面分别为板体各个表面中面积最大的两个表面，第一表面垂直于第一互联结构层；第二表面垂直于第一互联结构层；第一表面具有第一底边，半导体封装结构的制造方法包括还包括以下步骤：在第一表面的第一底边一侧形成多个第一底边接脚，多个第一底边接脚连接第一金属层；多个第一底边接脚还连接转接板金属层；第二表面具有第二底边，半导体封装结构的制造方法包括还包括以下步骤：在第二表面的第二底边一侧形成多个第二底边接脚，多个第二底边接脚连接第一金属层；多个第二底边接脚还连接转接板金属层。
可选的，半导体封装结构的制造方法依序包括以下步骤：提供基板，在基板上形成多个金属凸点；将转接板的多个第一底边接脚和多个第二底边接脚通过多个金属凸点焊接至第一基板；将第一芯片和第二芯片分别贴装至基板；形成塑封层，塑封层包覆第一芯片、第二芯片和转接板；去除基板；形成第一互联结构层，第一互联结构层覆盖第一芯片之前朝向基板 一侧的表面、第二芯片之前朝向基板一侧的表面、转接板之前朝向基板一侧的表面和塑封层之前朝向基板一侧的表面；在第一互联结构层背向塑封层一侧形成焊球，焊球连接第一金属层。
可选的，半导体封装结构的制造方法还包括以下步骤：在第一表面形成多个接点，在第二表面形成多个接点，转接板金属层连接第一表面的多个接点和第二表面的多个接点；将第三元件贴装至第一表面，第三元件通过第一表面的接点连接转接板金属层；和/或，将第三元件贴装至第二表面，第三元件通过第二表面的接点连接转接板金属层。
本申请还提供一种半导体器件，包括如上的半导体封装结构。
本申请技术方案，具有如下优点：
1.本申请的半导体封装结构，通过转接板垂直于第一互联结构层的设置，使得转接板立置于第一互联结构层上的塑封层中，转接板两侧的第一芯片和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
2.本申请的半导体封装结构，通过第一底边接脚和第二底边接脚连接至第一金属层，并且多个第一底边接脚和多个第二底边接脚分别连接转接板的设置，一方面实现了转接板的立置，另一方面转接板两侧的第一芯片 和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于半导体封装结构在水平方向上的小型化。
3.本申请的半导体封装结构，多个第一底边接脚呈平行于第一底边排列，多个第二底边接脚呈平行于第二底边排列。平行排列的接脚易于实现焊接的均衡性，可避免因焊接不均衡发生个别接脚的断开的情况。
4.本申请的半导体封装结构，通过第一表面和第二表面设置多个连接转接板金属层的接点，还可在转接板的第一表面和/或第二表面设置第三元件，第三元件通过接点连接转接板金属层，可实现与封装结构中其他元件的互联和同侧扇出，有利于提高器件的集成度。
5.本申请提供的半导体封装结构的制造方法制造的半导体封装结构，通过转接板垂直于第一互联结构层的设置，使得转接板立置于第一互联结构层上的塑封层中，转接板两侧的第一芯片和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
6.本申请提供的半导体封装结构的制造方法制造的半导体封装结构，通过形成多个第一底边接脚和多个第二底边接脚，第一底边接脚和第二底边接脚连接至第一金属层，并且转接板金属层连接多个第一底边接脚和多个第二底边接脚的设置，一方面实现了转接板的立置，另一方面转接板两侧的第一芯片和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于半导体封装结构在水平方向上的小型化。
7.本申请提供的半导体封装结构的制造方法制造的半导体封装结构，通过在转接板上形成多个接点，还可在转接板的第一表面和/或第二表面设置第三元件，第三元件通过接点连接转接板金属层，可实现与封装结构中其他元件的互联和同侧扇出，有利于提高器件的集成度。
8.本申请提供的半导体器件，包含如上的半导体封装结构，通过转接板垂直于第一互联结构层的设置，使得转接板立置于第一互联结构层上的塑封层中，转接板两侧的第一芯片和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图7为本申请的一实施例中的半导体封装结构的制造过程中各个状态的示意图；
图3为转接板第一表面一侧的侧视图；
图7为本申请的一实施例中的半导体封装结构的结构示意图；
图8为本申请的另一实施例中的半导体封装结构的结构示意图。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和 操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
参考图1-图8，本实施例提供一种半导体封装结构，包括：
塑封层400。
第一互联结构层500，第一互联结构层500位于塑封层400一侧表面，第一互联结构层500包括第一金属层501和第一绝缘介质层502。
转接板300，转接板300位于塑封层400中，转接板300自身延展的平面垂直于第一互联结构层500，转接板300内具有转接板金属层(图中未示出)，转接板金属层连接第一金属层501。
第一芯片100，第一芯片100位于第一互联结构层500朝向塑封层400一侧的表面，第一芯片100连接第一金属层501，塑封层400包覆第一芯片100。
第二芯片200，第二芯片200位于第一互联结构层500朝向塑封层400一 侧的表面，第二芯片200连接第一金属层501，塑封层400包覆第二芯片200。
第一芯片100和第二芯片200为不同种类的芯片，第一芯片100和第二芯片200分别位于转接板300的两侧。
例如第一芯片100和第二芯片200可以分别为现场可编程门阵列(FPGA)芯片和双倍速率同步动态随机存储器(DDR)芯片。
本实施例的半导体封装结构，通过转接板300垂直于第一互联结构层500的设置，使得转接板300立置于第一互联结构层500上的塑封层400中，转接板300两侧的第一芯片100和第二芯片200通过第一金属层501和转接板300实现了互联。相比平面互联线的互联方式，由于转接板300布线的工艺可以实现比平面互联线的密集布线加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板300立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
参考图2、图3以及图7，在本实施例中，转接板300包括板体301，板体301具有相对的第一表面和第二表面，第一表面和第二表面分别为板体各个表面中面积最大的两个表面，第一表面垂直于第一互联结构层500；第二表面垂直于第一互联结构层500。
第一表面具有第一底边，第一表面在第一底边一侧设置有多个第一底边接脚3021，多个第一底边接脚3021连接第一金属层501；多个第一底边接脚3021还连接转接板金属层.
第二表面具有第二底边，第二表面在第二底边一侧设置有多个第二底 边接脚3022，多个第二底边接脚3022连接第一金属层501；多个第二底边接脚3022还连接转接板金属层。
通过第一底边接脚3021和第二底边接脚3022连接至第一金属层501，并且多个第一底边接脚3021和多个第二底边接脚3022分别连接转接板300的设置，一方面实现了转接板300的立置，另一方面转接板300两侧的第一芯片100和第二芯片200通过第一金属层501和转接板300实现了互联。相比平面互联线的互联方式，由于转接板300布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板300立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于半导体封装结构在水平方向上的小型化。
在本实施例中，多个第一底边接脚3021平行于第一底边排列，多个第二底边接脚3022平行于第二底边排列。平行排列的接脚易于实现焊接的均衡性，可避免因焊接不均衡发生个别接脚的断开的情况。
在本实施例中，第一芯片100的数量可以为多个；和/或，第二芯片200的数量可以为多个。
参考图8，在其他一些实施例中，第一表面还设置有多个接点303，第二表面还设置有多个接点303，转接板金属层连接第一表面的多个接点303和第二表面的多个接点303。第一表面设置有第三元件700，第三元件700通过第一表面的接点303连接转接板金属层；和/或，第二表面设置有第三元件700，第三元件700通过第二表面的接点303连接转接板金属层。
具体的，第三元件700可以为无源器件或芯片。
通过第一表面和第二表面设置多个连接转接板金属层的接点，还可在转接板的第一表面和/或第二表面设置第三元件700，第三元件700通过接点303连接转接板金属层，可实现与封装结构中其他元件的互联和同侧扇出，有利于提高器件的集成度。
实施例2
参考图1-图7，本实施例提供一种半导体封装结构的制造方法，包括以下步骤：
形成塑封层400。
形成第一互联结构层500，第一互联结构层500位于塑封层400一侧表面，第一互联结构层500包括第一金属层501和第一绝缘介质层502。
设置转接板300，转接板300位于塑封层400中，转接板300自身延展的平面垂直于第一互联结构层500，转接板300内具有转接板金属层，转接板金属层连接第一金属层501。
贴装第一芯片100，第一芯片100位于第一互联结构层500朝向塑封层400一侧的表面，第一芯片100连接第一金属层501，塑封层400包覆第一芯片100。
贴装第二芯片200，第二芯片200位于第一互联结构层500朝向塑封层400一侧的表面，第二芯片200连接第一金属层501，塑封层400包覆第二芯片200。
其中第一芯片100和第二芯片200为不同种类的芯片，第一芯片100和第二芯片200分别位于转接板300的两侧。
例如第一芯片100和第二芯片200可以分别为现场可编程门阵列(FPGA)芯片和双倍速率同步动态随机存储器(DDR)芯片。
在本实施例中，转接板300包括板体301，板体301具有相对的第一表面和第二表面，第一表面和第二表面分别为板体301各个表面中面积最大的两个表面，第一表面垂直于第一互联结构层500，第二表面垂直于第一互联结构层500。
本实施例提供的半导体封装结构的制造方法，通过转接板300垂直于第一互联结构层500的设置，使得转接板300立置于第一互联结构层500上的塑封层400中，转接板300两侧的第一芯片100和第二芯片200通过第一金属层501和转接板300实现了互联。相比平面互联线的互联方式，由于转接板300布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板300立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
在本实施例中，第一表面具有第一底边，半导体封装结构的制造方法包括还包括以下步骤：在第一表面的第一底边一侧形成多个第一底边接脚3021，多个第一底边接脚3021连接第一金属层501；多个第一底边接脚3021还连接转接板金属层、
第二表面具有第二底边，半导体封装结构的制造方法包括还包括以下步骤：在第二表面的第二底边一侧形成多个第二底边接脚3022，多个第二底边接脚3022连接第一金属层501。多个第二底边接脚3022还连接转接板 金属层。
通过形成多个第一底边接脚3021和多个第二底边接脚3022，第一底边接脚3021和第二底边接脚3022连接至第一金属层501，并且转接板金属层连接多个第一底边接脚3021和多个第二底边接脚3022的设置，一方面实现了转接板300的立置，另一方面转接板300两侧的第一芯片100和第二芯片200通过第一金属层501和转接板300实现了互联。相比平面互联线的互联方式，由于转接板300布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。此外，由于转接板300立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于半导体封装结构在水平方向上的小型化
在本实施例中，半导体封装结构的制造方法依序包括以下步骤：
参考图1，提供基板0001，在基板0001上形成多个金属凸点0002。
参考图2，将转接板300的多个第一底边接脚3021和多个第二底边接脚3022通过多个金属凸点0002焊接至第一基板0001。
参考图4，将第一芯片100和第二芯片200分别贴装至基板0001。
参考图5，形成塑封层400，塑封层400包覆第一芯片100、第二芯片200和转接板300。
参考图6，去除基板0001。
参考图7，形成第一互联结构层500，第一互联结构层500覆盖第一芯片100之前朝向基板0001一侧的表面、转接板300之前朝向基板0001一侧的表面和塑封层400之前朝向基板0001一侧的表面。
继续参考图7，在第一互联结构层500背向塑封层400一侧形成焊球600，焊球600连接第一金属层。
参考图8，在其他一些实施例中，半导体封装结构的制造方法还包括以下步骤：
在第一表面形成多个接,303，在第二表面形成多个接点303，转接板金属层连接第一表面的多个接点303和第二表面的多个接点303。
将第三元件700贴装至第一表面，第三元件700通过第一表面的接点303连接转接板金属层；和/或，
将第三元件700贴装至第二表面，第三元件700通过第二表面的接点303连接转接板金属层。
通过在转接板300上形成多个接点303，还可在转接板300的第一表面和/或第二表面设置第三元件700，第三元件700通过接点303连接转接板金属层，可实现与封装结构中其他元件的互联和同侧扇出，有利于提高器件的集成度。
实施例3
本实施例提供一种半导体器件，包括上述实施例1中的半导体封装结构。通过转接板垂直于第一互联结构层的设置，使得转接板立置于第一互联结构层上的塑封层中，转接板两侧的第一芯片和第二芯片通过第一金属层和转接板实现了互联。相比平面互联线的互联方式，由于转接板布线的工艺可以实现比平面互联线的密集布线的加工工艺更高的精度和更小的线宽线距，因此可以实现比平面互联线更高的密集程度和占据更小的面积。 此外，由于转接板立置，使得平面互联线中部分在平面水平方向上的走线改变为垂直方向，可缩小布线区所占的面积，有利于封装结构在水平方向上的小型化。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (10)

  1. 一种半导体封装结构，其特征在于，包括：
    塑封层；
    第一互联结构层，所述第一互联结构层位于所述塑封层一侧表面，所述第一互联结构层包括第一金属层；
    转接板，所述转接板位于所述塑封层中，所述转接板延展的平面垂直于所述第一互联结构层，所述转接板内具有转接板金属层，所述转接板金属层连接所述第一金属层；
    第一芯片，所述第一芯片位于所述第一互联结构层朝向所述塑封层一侧的表面，所述第一芯片连接所述第一金属层，所述塑封层包覆所述第一芯片；
    第二芯片，所述第二芯片位于所述第一互联结构层朝向所述塑封层一侧的表面，所述第二芯片连接所述第一金属层，所述塑封层包覆所述第二芯片；
    所述第一芯片和所述第二芯片为不同种类的芯片，所述第一芯片和所述第二芯片分别位于所述转接板的两侧。
  2. 根据权利要求1所述的半导体封装结构，其特征在于，
    所述转接板包括板体，所述板体具有相对的第一表面和第二表面，所述第一表面和所述第二表面分别为所述板体各个表面中面积最大的两个表面，所述第一表面垂直于所述第一互联结构层；所述第二表面垂直于所述第一互联结构层；
    所述第一表面具有第一底边，所述第一表面在所述第一底边一侧设置 有多个第一底边接脚，所述多个第一底边接脚连接所述第一金属层；所述多个第一底边接脚还连接所述转接板金属层；
    所述第二表面具有第二底边，所述第二表面在所述第二底边一侧设置有多个第二底边接脚，所述多个第二底边接脚连接所述第一金属层；所述多个第二底边接脚还连接所述转接板金属层。
  3. 根据权利要求2所述的半导体封装结构，其特征在于，
    所述多个第一底边接脚平行于所述第一底边排列，所述多个第二底边接脚平行于所述第二底边排列。
  4. 根据权利要求1所述的半导体封装结构，其特征在于，还包括：
    所述第一芯片的数量为多个；和/或，所述第二芯片的数量为多个。
  5. 根据权利要求2或3所述的半导体封装结构，其特征在于，
    所述第一表面还设置有多个接点，所述第二表面还设置有多个接点，所述转接板金属层连接所述第一表面的多个接点和所述第二表面的多个接点；
    所述第一表面设置有第三元件，所述第三元件通过所述第一表面的接点连接所述转接板金属层；和/或，
    所述第二表面设置有第三元件，所述第三元件通过所述第二表面的接点连接所述转接板金属层；
    优选的，所述第三元件为无源器件或芯片。
  6. 一种半导体封装结构的制造方法，其特征在于，包括以下步骤：
    形成塑封层；
    形成第一互联结构层，所述第一互联结构层位于所述塑封层一侧表面， 所述第一互联结构层包括第一金属层；
    设置转接板，所述转接板位于所述塑封层中，所述转接板延展的平面垂直于所述第一互联结构层，所述转接板内具有转接板金属层，所述转接板金属层连接所述第一金属层；
    贴装第一芯片，所述第一芯片位于所述第一互联结构层朝向所述塑封层一侧的表面，所述第一芯片连接所述第一金属层，所述塑封层包覆所述第一芯片；
    贴装第二芯片，所述第二芯片位于所述第一互联结构层朝向所述塑封层一侧的表面，所述第二芯片连接所述第一金属层，所述塑封层包覆所述第二芯片；
    其中所述第一芯片和所述第二芯片为不同种类的芯片，所述第一芯片和所述第二芯片分别位于所述转接板的两侧。
  7. 根据权利要求6所述的半导体封装结构的制造方法，其特征在于，
    所述转接板包括板体，所述板体具有相对的第一表面和第二表面，所述第一表面和所述第二表面分别为所述板体各个表面中面积最大的两个表面，所述第一表面垂直于所述第一互联结构层；所述第二表面垂直于所述第一互联结构层；
    所述第一表面具有第一底边，所述半导体封装结构的制造方法包括还包括以下步骤：在所述第一表面的所述第一底边一侧形成多个第一底边接脚，所述多个第一底边接脚连接所述第一金属层；所述多个第一底边接脚还连接所述转接板金属层；
    所述第二表面具有第二底边，所述半导体封装结构的制造方法包括还 包括以下步骤：在所述第二表面的所述第二底边一侧形成多个第二底边接脚，所述多个第二底边接脚连接所述第一金属层；所述多个第二底边接脚还连接所述转接板金属层。
  8. 根据权利要求7所述的半导体封装结构的制造方法，其特征在于，
    所述半导体封装结构的制造方法依序包括以下步骤：
    提供基板，在所述基板上形成多个金属凸点；
    将所述转接板的多个第一底边接脚和多个第二底边接脚通过所述多个金属凸点焊接至所述基板；
    将所述第一芯片和所述第二芯片分别贴装至所述基板；
    形成所述塑封层，所述塑封层包覆所述第一芯片、所述第二芯片和所述转接板；
    去除所述基板；
    形成所述第一互联结构层，所述第一互联结构层覆盖所述第一芯片之前朝向基板一侧的表面、所述第二芯片之前朝向基板一侧的表面、所述转接板之前朝向基板一侧的表面和所述塑封层之前朝向基板一侧的表面；
    在所述第一互联结构层背向所述塑封层一侧形成焊球，所述焊球连接所述第一金属层。
  9. 根据权利要求7或8所述的半导体封装结构的制造方法，其特征在于，还包括以下步骤：
    在所述第一表面形成多个接点，在所述第二表面形成多个接点，所述转接板金属层连接所述第一表面的多个接点和所述第二表面的多个接点；
    将第三元件贴装至所述第一表面，所述第三元件通过所述第一表面的 接点连接所述转接板金属层；和/或，
    将第三元件贴装至所述第二表面，所述第三元件通过所述第二表面的接点连接所述转接板金属层。
  10. 一种半导体器件，其特征在于，包括：
    如权利要求1-5中任一项所述的半导体封装结构。
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