WO2024082536A1 - 一种封装结构 - Google Patents

一种封装结构 Download PDF

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Publication number
WO2024082536A1
WO2024082536A1 PCT/CN2023/082474 CN2023082474W WO2024082536A1 WO 2024082536 A1 WO2024082536 A1 WO 2024082536A1 CN 2023082474 W CN2023082474 W CN 2023082474W WO 2024082536 A1 WO2024082536 A1 WO 2024082536A1
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WO
WIPO (PCT)
Prior art keywords
layer
electrical connection
packaging structure
base layer
pad
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Application number
PCT/CN2023/082474
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English (en)
French (fr)
Inventor
潘英
Original Assignee
长鑫存储技术有限公司
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Publication of WO2024082536A1 publication Critical patent/WO2024082536A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to, but is not limited to, a packaging structure.
  • the present disclosure provides a packaging structure, comprising:
  • a plurality of crystal grains are stacked on the base layer, the projections of two adjacent crystal grains on the base layer partially overlap, and the projections of two crystal grains arranged at intervals on the base layer at least partially overlap;
  • the two spaced-apart grains are electrically connected via an electrical signal path, wherein the electrical signal path comprises a first electrical connection layer, the first electrical connection layer is located between the two spaced-apart grains, and the first electrical connection layer is electrically connected to the two spaced-apart grains respectively.
  • the electrical signal path further comprises a conductive plug, and the first electrical connection layer is electrically connected to the conductive plug;
  • the conductive plug is disposed on a grain close to the base layer among the two grains disposed at intervals, and the conductive plug penetrates the grain.
  • a support layer is disposed between two adjacent grains.
  • the heights of the support layers between any two adjacent grains are equal, and the height of the first electrical connection layer is greater than twice the height of the support layer.
  • a grain adjacent to the base layer among the plurality of grains is a first grain, and the support layer is disposed between the first grain and the base layer.
  • a grain adjacent to the first grain among the plurality of grains is a second grain, and the first electrical connection layer is disposed between the second grain and the base layer.
  • a second electrical connection layer is disposed between the first crystal grain and the base layer, and the first crystal grain is electrically connected to the base layer through the second electrical connection layer;
  • the second electrical connection layer and the support layer have the same height.
  • the first electrical connection layer includes a first pad and a second pad, and a first solder bump located between the first pad and the second pad;
  • the first pad and the second pad are respectively connected to two of the dies that are spaced apart from each other, or,
  • One of the first pad and the second pad is connected to the die, and the other of the first pad and the second pad is connected to the base layer.
  • the second electrical connection layer and the support layer each include two independently arranged third pads, and a second welding bump located between the two third pads;
  • One of the two third pads is connected to the first conductive plug of the first die, and the two third pads are connected to the first conductive plug of the first die. Another one of the three pads is connected to the base layer.
  • a height of the first welding bump is greater than a height of the second welding bump.
  • front sides of the two dies disposed at intervals are disposed opposite to each other.
  • a welding pad is disposed on the front side of the die, and the first electrical connection layer is electrically connected to two of the welding pads disposed opposite to each other.
  • front sides of the two dies disposed at intervals face the base layer.
  • a bonding pad is disposed on the front side of the die, and the bonding pad of the upper die among the two interval-arranged die is electrically connected to the first electrical connection layer.
  • the conductive plug of the lower die among the two dies arranged at an interval is electrically connected to the first electrical connection layer.
  • the base layer includes a packaging substrate or a control chip.
  • the packaging structure further includes a packaging layer, wherein the packaging layer covers the die and fills the area between adjacent die;
  • the encapsulation layer fills the area between the die and the base layer.
  • the present invention increases the distance between the grains by staggering multiple grains, which facilitates filling and improves the heat dissipation performance; after the multiple grains are staggered, an electrical signal path is set between two spaced grains to form an electrical connection, thereby increasing the distance between the multiple electrical signal paths formed between the spaced grains, avoiding interference caused by the close distance between different electrical signal paths, and improving the signal transmission reliability of the packaging structure.
  • FIG. 1 is a schematic diagram of a packaging structure in a comparative embodiment.
  • Fig. 2 is a schematic diagram showing a packaging structure according to an exemplary embodiment.
  • Fig. 3 is a schematic diagram of an exploded view of a packaging structure according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram showing a packaging structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram showing an exploded view of a packaging structure according to an exemplary embodiment.
  • multiple semiconductor dies in a stacked arrangement are usually connected by through silicon vias, which easily cause signal interference between close through silicon vias.
  • multiple semiconductor dies in a stacked arrangement are usually connected by adhesive, which has a weak heat dissipation capacity and affects the performance of the memory.
  • a packaging structure in a comparative embodiment is provided, and the packaging structure can be applied, for example, to the process of producing high bandwidth memory (HBM).
  • the packaging structure includes a base layer 100' and a plurality of crystal grains 200', wherein the plurality of crystal grains 200' are stacked on the base layer 100', and the projections of the plurality of crystal grains 200' on the base layer 100' overlap. Between the crystal grains 200' and the base layer 100', and between the crystal grains 200' and the crystal grains 200', adhesive 600' is usually used for bonding connection, and the distance between adjacent crystal grains 200' is relatively close.
  • a conductive path 300' is provided between the plurality of crystal grains 200', and the conductive path 300' is used to form an electrical connection channel between the crystal grain 200' and the base layer 100' or between the crystal grain 200' and the crystal grain 200'. As shown in FIG. 1 , the physical positions of the plurality of conductive paths 300' are relatively close, which may easily cause signal interference during signal transmission, thereby affecting the signal transmission quality.
  • the present disclosure provides a packaging structure, which includes a base layer and a plurality of grains, wherein the plurality of grains are stacked on the base layer, the projections of two adjacent grains on the base layer partially overlap, the projections of two grains arranged at intervals on the base layer at least partially overlap, and the two grains arranged at intervals are electrically connected through an electrical signal path, the electrical signal path includes a first electrical connection layer, the first electrical connection layer is located between the two grains arranged at intervals, and the first electrical connection layer is electrically connected to the two grains arranged at intervals, respectively.
  • the present disclosure increases the distance between the grains by staggering the plurality of grains, which facilitates filling and improves the heat dissipation performance; after staggering the plurality of grains, an electrical signal path is arranged between the two grains arranged at intervals to form an electrical connection, thereby increasing the distance between the plurality of electrical signal paths formed between the grains arranged at intervals, avoiding interference caused by the close distance between different electrical signal paths, and improving the signal transmission reliability of the packaging structure.
  • an embodiment of the present disclosure provides a packaging structure, which can be applied to the process of packaging semiconductor devices such as memory, for example, in the packaging process of memory devices such as DRAM (Dynamic Random Access Memory) and LPDDR (Low Power Double Data Rate).
  • DRAM Dynamic Random Access Memory
  • LPDDR Low Power Double Data Rate
  • the packaging structure includes a base layer 100 and a plurality of crystal grains 200 .
  • the base layer 100 serves as a supporting structure of the packaging structure.
  • the base layer 100 may be a packaging substrate 110 (refer to FIG. 2 ).
  • An interconnection through hole (not shown in the drawing) may be provided in the packaging substrate 110 .
  • the interconnection through hole penetrates the packaging substrate 110 in the thickness direction of the packaging substrate 110 (the z direction shown in FIG. 2 ), so that the plurality of crystal grains 200 in the packaging structure can be electrically connected to external components (not shown in the drawing) through the interconnection through hole, such as capacitors, power supply devices, etc.
  • the base layer 100 may also be a control chip 120 (refer to FIG. 4 ).
  • the control chip 120 can be electrically connected to the crystal grain 200 and control it. Among them, an integrated circuit is provided in the crystal grain 200 .
  • the integrated circuit has a specific function.
  • the combination of a plurality of crystal grains 200 can make the packaging structure have a corresponding function.
  • the crystal grains 200 are stacked on the base layer 100 (in the z direction shown in FIG. 2), and the projections of two adjacent crystal grains 200 on the base layer 100 partially overlap.
  • the projections of the two crystal grains 200 disposed at intervals on the base layer 100 at least partially overlap, that is, the projections of the two crystal grains 200 disposed at intervals on the base layer 100 may completely overlap, or may only overlap. Partially overlap to form a conductive path between the overlapping parts to achieve electrical signal transmission.
  • this embodiment exemplarily shows a situation where four crystal grains are arranged on the base layer 100, and the plurality of crystal grains 200 are the first crystal grain 210, the second crystal grain 220, the third crystal grain 230 and the fourth crystal grain 240 from bottom to top (z direction shown in FIG. 2).
  • the number of crystal grains for example, six crystal grains can also be set.
  • the projections of adjacent grains 200 on the base layer 100 overlap, so that the grain 200 located at the lower layer of two adjacent grains 200 can provide support for the grain 200 located at the upper layer.
  • the first grain 210 can provide support for the second grain 220
  • the second grain 220 can provide support for the third grain 230
  • the third grain 230 can provide support for the fourth grain 240.
  • FIG. 2 shows an example in which the projections of the two spaced-apart dies 200 on the base layer 100 (see FIG. 3) completely overlap, for example, the projections of the first die 210 and the third die 230 on the base layer 100 completely overlap, and the projections of the second die 220 and the fourth die 240 on the base layer 100 overlap.
  • the two interval-set grains 200 may only partially overlap.
  • the fourth grain 240 may be moved a certain distance to the left (opposite to the x-direction shown in FIG. 2 ) based on the orientation shown in FIG. 2 , but it is necessary to ensure that the fourth grain 240 has overlapping portions with both the third grain 230 and the second grain 22.
  • the electrical signal path 300 includes a first electrical connection layer 310.
  • the first electrical connection layer 310 is located between two spaced-apart grains 200, and the first electrical connection layer 310 is electrically connected to the two spaced-apart grains 200, respectively.
  • the first electrical connection layer 310 is arranged between the second grain 220 and the fourth grain 240, and the first electrical connection layer 310 is arranged between the first grain 210 and the third grain 230. Referring to FIG. 2 , the right side (x direction shown in FIG.
  • the left side (opposite to the x direction shown in FIG. 2 ) area of the fourth die 240 is directly opposite to the left side area of the third die 230, so that the first electrical connection layer 310 can be set between the left side area of the fourth die 240 and the left side area of the second die 220, and the second die 220 and the fourth die 240 are electrically connected through the first electrical connection layer 310.
  • the electrical signal path 300 formed between the first die 210 and the third die 230 and the electrical signal path 300 formed between the second die 220 and the fourth die 240 are two independent conductive paths. Based on the orientation shown in FIG. 2 , the two electrical signal paths 300 are respectively set on the left and right sides of the packaging structure, and the distance between the two is relatively far, so the signal interference is small.
  • the distance between different electrical signal paths 300 increases, thereby preventing the electrical signal paths 300 from being too close to each other and causing signal interference, thereby improving the performance of the packaging structure.
  • stacking in the above-mentioned manner can also reduce the overlapping area between the dies 200, increase the heat dissipation area of each dies 200 and the distance between the dies 200, and improve the heat dissipation performance of the packaging structure.
  • the exposed surface area of the grains and the distance between the grains are increased, which facilitates packaging and filling between the grains while also improving the heat dissipation performance; and, after staggering the plurality of grains, an electrical signal path can be set between two spaced-apart grains to form an electrical connection, thereby increasing the distance between the electrical signal paths of the plurality of grains, effectively avoiding interference caused by the proximity of different electrical signal paths, and improving the signal transmission reliability of the packaging structure.
  • this embodiment provides a packaging structure, which includes a base layer 100 and a plurality of dies 200, wherein the plurality of dies 200 are stacked on the base layer 100, wherein the projections of two adjacent dies 200 on the base layer 100 partially overlap, and the projections of two dies 200 disposed at intervals at least partially overlap on the base layer 100, and the two dies 200 disposed at intervals are electrically connected through an electrical signal path 300, wherein the electrical signal path 300 includes a first The electrical connection layer 310 , the first electrical connection layer 310 is located between two spaced-apart crystal grains 200 , and the first electrical connection layer 310 is electrically connected to the two spaced-apart crystal grains 200 , respectively.
  • the electrical signal path 300 further includes a conductive plug 320, which is disposed in the grain 200.
  • the conductive plug 320 penetrates the grain 200 in the thickness direction of the grain 200 (the z direction shown in FIG2 ), and the conductive plug 320 is formed by through silicon via (TSV) technology.
  • TSV through silicon via
  • the conductive plug 320 is disposed in the grain 200 close to the base layer 100 among the two grains 200 disposed at intervals.
  • the conductive plug 320 is disposed in the first grain 210 closer to the base layer 100; among the second grain 220 and the fourth grain 240 disposed at intervals, the conductive plug 320 is disposed in the second grain 220 closer to the base layer 100.
  • the conductive plug 320 disposed in the first die 210 is defined as a first conductive plug 321
  • the conductive plug 320 disposed in the second die 220 is defined as a second conductive plug 322 .
  • the package structure further includes a fifth die (not shown in the drawings) and a sixth die (not shown in the drawings) stacked in sequence, wherein the fifth die is connected to the third die 230, and the sixth die is connected to the fourth die 240.
  • conductive plugs need to be disposed in the third die 230 and the fourth die 240.
  • a support layer 400 is provided between two adjacent grains 200.
  • the support layer 400 is provided between two adjacent grains 200 in the embodiment of the present disclosure. Since the support layer 400 has a certain height (z direction shown in FIG2 ), the height difference between adjacent grains 200 is increased. In the two adjacent grains 200, the bottom surface of the upper grain 200 (z direction shown in FIG2 ) and the top surface of the lower grain 200 can be exposed, which is convenient for filling the packaging material between the two adjacent grains 200. At the same time, the heat dissipation area of the grains 200 can also be increased, and the heat dissipation performance is improved.
  • the support layer 400 can be made of metal material and connected by welding. Compared with the adhesive 600 ', the support layer 400 can increase the connection strength between adjacent grains 200, and improve the overall strength and reliability of the packaging structure.
  • the height of the support layer 400 between any two adjacent grains 200 is equal. It can be determined that since the heights of the support layers 400 arranged between the multiple grains 200 are all equal, the multiple support layers 400 can be processed using the same process technology, which is simple in process and convenient in layout, and is conducive to improving the yield rate.
  • the heights of the plurality of first electrical connection layers 310 may also be set to be equal, so that the plurality of grains 200 can be connected and assembled according to a unified standard.
  • the height of the first electrical connection layer 310 is set to be equal to the sum of the thickness of one grain 200 and the height of the two support layers 400, so that the support heights on the left and right sides of the plurality of grains 200 are the same, so that the plurality of grains 200 are parallel to each other, which facilitates the stacking and assembly of the plurality of grains.
  • the height of the first electrical connection layer 310 may also be slightly greater than the sum of the thickness of one grain 200 and the height of the two support layers 400, and while not affecting the packaging performance, some tilting of the individual grains 200 may be allowed, as long as the height of the first electrical connection layer 310 is greater than twice the height of the support layer 400.
  • a support layer 400 is also provided between the first crystal grain 210 and the base layer 100.
  • the first crystal grain 210 is located at the bottom among the multiple crystal grains 200, so that the first crystal grain 210 is directly adjacent to the base layer 100.
  • the first crystal grain 210 and the base layer 100 are no longer closely attached, so that the first crystal grain 210 can dissipate heat through its lower surface, thereby enhancing the heat dissipation capacity of the first crystal grain 210.
  • connecting the first crystal grain 210 and the base layer 100 with the support layer 400 can also improve the structural strength between the first crystal grain 210 and the base layer 100.
  • a second electrical connection layer 500 can be provided between the first crystal grain 210 and the base layer 100.
  • the second electrical connection layer 500 is used to transmit the electrical signal of the base layer 100 to the first crystal grain 210, and then to the third crystal grain 230 through the electrical signal path 300.
  • the height of the support layer 400 and the second electrical connection layer 500 can be set to be the same, so that the first crystal grain 210 can be kept level with the base layer 100, and the stacking reliability of multiple crystal grains 200 is improved.
  • the second electrical connection layer 500 includes two independent third pads 410, and the material of the third pads 410 may be copper, for example.
  • One of the two third pads 410 is electrically connected to the first conductive plug 321 of the first crystal grain 210, and the other of the two third pads 410 is connected to the base layer 100, so as to form an electrical signal transmission between the base layer 100 and the first crystal grain 210.
  • FIG3 a schematic diagram of a plurality of crystal grains 200 and a base layer 100 that are not connected is shown, and the support layer 400 also includes two independent third pads 410, one of the two third pads 410 is welded to the first crystal grain 210, and the other of the two third pads 410 is welded to the base layer 100, but the support layer 400 does not form an electrical signal path between the base layer 100 and the first crystal grain 210.
  • the second electrical connection layer 500 includes two third pads 410 and a second welding bump 420 located between the two third pads 410.
  • the support layer 400 also includes two third pads 410 and a second welding bump 420 located between the two third pads 410.
  • the second welding bump 420 is used to weld and connect the two third pads 410.
  • FIG3 a schematic diagram of a plurality of grains 200 and a base layer 100 that are not connected is shown.
  • the second welding bump 420 can be set on the third pad 410 on the first grain 210, or on the third pad 410 on the base layer 100, but no further details are given.
  • the material of the second welding bump 420 can be, for example, tin, which has a low melting point and can be melted by a little heating to quickly connect the two third pads 410 and improve the packaging efficiency.
  • the shape of the second welding bump 420 can be columnar or spherical, which can be selected according to the packaging needs.
  • a first electrical connection layer 310 is disposed between the second crystal grain 220 and the base layer 100 .
  • the first electrical connection layer 310 disposed between the second crystal grain 220 and the base layer 100 is used to form electrical signal transmission between the second crystal grain 220 and the base layer 100 .
  • a first electrical connection layer 310 is also provided between the second and fourth grains 220 and 240, which are arranged at intervals.
  • the first electrical connection layer 310 provided between the second and fourth grains 220 and 240 is used to form electrical signal transmission between the second and fourth grains 220 and 240.
  • the first electrical connection layer 310 between the second and fourth grains 220 and 240 is connected to the second pad 221 (refer to FIG. 3 ) of the second grain 220, so that an electrical signal path 300 is formed between the second and fourth grains 220 and 240.
  • the second pad 221 of the second grain 220 is connected to the second conductive plug 322 in the second grain 220 to form an electrical connection, the two electrical signal paths 300 between the second and fourth grains 220 and between the second and fourth grains 240 and between the second grain 220 and the base layer 100 are connected, so that the signal in the fourth grain 240 can be transmitted to the base layer 100.
  • the first and third grains 210 and 230 are similar, and will not be described in detail.
  • the first electrical connection layer 310 located between the second die 220 and the base layer 100 and the first electrical connection layer 310 located between the interval-arranged die 200 may be manufactured using the same process technology.
  • the first electrical connection layer 310 includes a first pad 311 and a second pad 312, and the materials of the first pad 311 and the second pad 312 may be copper.
  • the first electrical connection layer 310 also includes a first welding bump 313, and the first welding bump 313 is used to weld the first pad 311 and the second pad 312 together, and the first welding bump 313 may be spherical or cylindrical.
  • the first welding bump 313 may be set to be cylindrical.
  • the material of the first welding bump 313 may be tin, for example, and the first welding bump 313 may be formed on the first pad 311 or on the second pad 312 using a growth process.
  • the heights of the first pad 311 and the second pad 312 may be the same or different. Usually, the heights of the first pad 311 and the second pad 312 are not equal, and the height of the first pad 311 is greater than the height of the second pad 312.
  • the first pad 311 and the second pad 312 are usually formed by an epitaxial growth process. If two pads with higher heights need to be formed on the same grain at the same time, the process will be complicated.
  • the second grain 220 and the fourth grain 240 are arranged at intervals.
  • a higher first pad 311 may be formed on the fourth die 240, and a lower second pad 312 may be formed on the second die 220, to avoid the need to grow higher pads on both the upper and lower sides of the second die 220, thereby reducing process difficulty.
  • the first solder pad 311 on the fourth chip 240 can be aligned with the second solder pad 312 on the second chip 220 so that the first solder bump 313 is located between the first solder pad 311 and the second solder pad 312.
  • the first solder bump 313 is melted by heating the first solder bump 313, and the first solder pad 311 and the second solder pad 312 can be fastened together after the first solder bump 313 is cooled.
  • the height of the first electrical connection layer 310 is greater than twice the height of the support layer 400, wherein the manner in which the height of the first electrical connection layer 310 can be greater than the height of the support layer 400 includes increasing the height of any one or more of the first pad 311, the second pad 312, or the first welding bump 313, so that the height of the first electrical connection layer 310 is greater than twice the height of the support layer 400.
  • the height of the first welding bump 313 in the first electrical connection layer 310 can be set to be greater than the height of the second welding bump 420 in the support layer 400, so that the height of the first electrical connection layer 310 is greater than twice the height of the support layer 400, so as to supplement the height of the grain 200.
  • the present embodiment provides a packaging structure
  • the packaging structure includes a base layer 100 and a plurality of dies 200, the plurality of dies 200 are stacked on the base layer 100, the projections of two adjacent dies 200 on the base layer 100 partially overlap, the projections of two dies 200 disposed at intervals on the base layer 100 at least partially overlap, the two dies 200 disposed at intervals are electrically connected through an electrical signal path 300, the electrical signal path includes a first electrical connection layer 310, the first electrical connection layer 310 is located between the two dies 200 disposed at intervals, and the first electrical connection layer 310 is electrically connected to the two dies 200 disposed at intervals, respectively.
  • the packaging structure provided in the present embodiment may include the structures provided in the above-mentioned embodiments.
  • the front sides of two spaced-apart crystal grains 200 are arranged opposite to each other.
  • the front side of the crystal grain 200 for example, the side of the crystal grain 200 is provided with a pad 250 (pad), and the pad 250 of the crystal grain 200 is connected to an integrated circuit (not shown in the drawings) inside the crystal grain 200, and a signal transmission path can be formed through the pad 250 for signal transmission.
  • the pad 250 on the first crystal grain 210 is defined as a first pad 211
  • the pad 250 on the second crystal grain 220 is defined as a second pad 221
  • the pad 250 on the third crystal grain 230 is defined as a third pad 231
  • the pad 250 on the fourth crystal grain 240 is defined as a fourth pad 241.
  • the first pad 211 on the first grain 210 is electrically connected to the first conductive plug 321 , so that the third grain 230 can be electrically connected to the first conductive plug 321 through the first pad 211 , thus saving additional wiring.
  • the second grain 220 and the fourth grain 240 are similar, and will not be described in detail.
  • the fourth die 240 is in a flipped state, so that the fourth pad 241 located on the front of the fourth die 240 can face the second die 220, and the first electrical connection layer 310 is arranged on the front of the fourth die 240, so that the fourth die 240 can be electrically connected to the second conductive plug 322 in the second die 220 through the fourth pad 241, the first electrical connection layer 310, and the second pad 221 in sequence.
  • the front sides of the two spaced-apart dies 200 both face the base layer 100 , that is, all the dies 200 are packaged in a flip-chip manner.
  • the pad 250 of the upper die 200 is electrically connected to the first electrical connection layer 310
  • the conductive plug 320 of the lower die 200 is electrically connected to the first electrical connection layer 310 .
  • the first electrical connection layer 310 is located on the front side of the fourth die 240 (the side where the fourth pad 241 is provided), and the first electrical connection layer 310 is located on the back side of the second die 220 , and the fourth die 240 can form an electrical connection with the second conductive plug 322 in the second die 220 through the fourth pad 241 and the first electrical connection layer 310 .
  • the packaging structure further includes a packaging layer 700 , which covers the die 200 and fills the area between adjacent die 200 , and the packaging layer 700 also fills the area between the die 200 and the base layer 100 .
  • a packaging structure provided with a support layer 400. Since the support layer 400 increases the interval between adjacent crystal grains 200 and increases the interval between the crystal grains 200 and the base layer 100, it is more conducive to filling the packaging layer 700.
  • the material of the packaging layer 700 is, for example, epoxy molding compound (EMC), which has excellent properties such as high heat resistance, high moisture resistance, high filling rate, low expansion, low stress, low impurities, and low friction coefficient.
  • EMC epoxy molding compound
  • first, second, etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.
  • the distance between the grains is increased by staggering the plurality of grains, which facilitates filling and improves the heat dissipation performance; after the plurality of grains are staggered, an electrical signal path is set between two spaced grains to form an electrical connection, thereby increasing the distance between the plurality of electrical signal paths formed between the spaced grains, avoiding interference caused by the close distance between different electrical signal paths, and improving the signal transmission reliability of the packaging structure.

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  • Physics & Mathematics (AREA)
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Abstract

公开了一种封装结构，封装结构包括基层和多个晶粒，多个晶粒层叠设置于基层，相邻的两个晶粒在基层上的投影部分重合，间隔设置的两个晶粒在基层上的投影至少部分重合，间隔设置的两个晶粒通过电信号通路形成电连接，电信号通路的第一电连接层位于间隔设置的两个晶粒之间，且第一电连接层分别与间隔设置的两个晶粒电连接。

Description

一种封装结构
本公开基于申请号为202211290801.7、申请日为2022年10月21日、申请名称为“一种封装结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种封装结构。
背景技术
在半导体技术领域，半导体芯片正朝着3D堆叠的方向发展，通过对半导体芯片厚度空间的利用，能够增加存储器的存储密度，以具有更强的存储性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种封装结构，包括：
基层；
多个晶粒，层叠设置于所述基层，相邻的两个所述晶粒在所述基层上的投影部分重合，间隔设置的两个所述晶粒在所述基层上的投影至少部分重合；
间隔设置的两个所述晶粒通过电信号通路电连接，所述电信号通路包括第一电连接层，所述第一电连接层位于间隔设置的两个所述晶粒之间，且所述第一电连接层分别与间隔设置的两个所述晶粒电连接。
在一些实施例中，所述电信号通路还包括导电插塞，所述第一电连接层与所述导电插塞电连接；
所述导电插塞设置于间隔设置的两个所述晶粒中靠近所述基层的晶粒，所述导电插塞贯穿所述晶粒。
在一些实施例中，相邻的两个所述晶粒之间设置支撑层。
在一些实施例中，沿多个所述晶粒的层叠方向，任意相邻的两个所述晶粒之间的所述支撑层的高度相等，所述第一电连接层的高度大于所述支撑层的高度的两倍。
在一些实施例中，多个所述晶粒中与所述基层相邻的晶粒为第一晶粒，所述第一晶粒与所述基层之间设置所述支撑层。
在一些实施例中，多个所述晶粒中与所述第一晶粒相邻的晶粒为第二晶粒，所述第二晶粒与所述基层之间设置所述第一电连接层。
在一些实施例中，所述第一晶粒与所述基层之间设置第二电连接层，所述第一晶粒通过所述第二电连接层与所述基层电连接；
沿多个所述晶粒的层叠方向，所述第二电连接层与所述支撑层的高度相等。
在一些实施例中，所述第一电连接层包括第一焊盘和第二焊盘，以及位于所述第一焊盘和所述第二焊盘之间的第一焊接凸点；
所述第一焊盘和所述第二焊盘分别与间隔设置的两个所述晶粒连接，或者，
所述第一焊盘和所述第二焊盘两者之一与所述晶粒连接，两者另一与所述基层连接。
在一些实施例中，所述第二电连接层和所述支撑层均包括独立设置的两个第三焊盘，以及位于两个所述第三焊盘之间的第二焊接凸点；
两个所述第三焊盘中的一个与所述第一晶粒的第一导电插塞连接，两个所述第 三焊盘中的另一个与所述基层连接。
在一些实施例中，沿多个所述晶粒的层叠方向，所述第一焊接凸点的高度大于所述第二焊接凸点的高度。
在一些实施例中，间隔设置的两个所述晶粒的正面相对设置。
在一些实施例中，所述晶粒的正面设置焊垫，所述第一电连接层分别与相对设置的两个所述焊垫电连接。
在一些实施例中，间隔设置的两个所述晶粒的正面均朝向所述基层。
在一些实施例中，所述晶粒的正面设置焊垫，间隔设置的两个所述晶粒中位于上方的晶粒的所述焊垫与所述第一电连接层电连接。
在一些实施例中，间隔设置的两个所述晶粒中位于下方的晶粒的所述导电插塞与所述第一电连接层电连接。
在一些实施例中，所述基层包括封装基板或控制芯片。
在一些实施例中，所述封装结构还包括封装层，所述封装层包覆所述晶粒并填充相邻的所述晶粒之间的区域；
所述封装层填充所述晶粒与所述基层之间的区域。
本公开提供的封装结构中，本公开通过将多个晶粒交错设置，增大了晶粒间的距离，方便进行填充的同时还提升了散热性能；将多个晶粒错开设置后，在间隔设置的两个晶粒之间设置电信号通路形成电连接，从而能够将间隔设置的晶粒之间形成的多条电信号通路间的距离增大，避免了不同电信号通路之间距离较近而产生干扰，提高了封装结构的信号传输可靠性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是对比实施例中封装结构的示意图。
图2是根据一示例性实施例示出的封装结构的示意图。
图3是根据一示例性实施例示出的封装结构的拆分示意图。
图4是根据一示例性实施例示出的封装结构的示意图。
图5是根据一示例性实施例示出的封装结构的拆分示意图。
附图标记：
100’、基层；200’、晶粒；300’、导电通路；600’、粘贴胶；
100、基层；110、封装基板；120、控制芯片；
200、晶粒；210、第一晶粒；211、第一焊垫；220、第二晶粒；221、第二焊
垫；230、第三晶粒；231、第三焊垫；240、第四晶粒；241、第四焊垫；250、焊垫；
300、电信号通路；310、第一电连接层；311、第一焊盘；312、第二焊盘；
313、第一焊接凸点；320、导电插塞；321、第一导电插塞；320、第二导电插塞；
400、支撑层；410、第三焊盘；420、第二焊接凸点；
500、第二电连接层；
700、封装层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地 描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在半导体技术领域，半导体芯片正朝着3D堆叠的方向发展，通过对半导体芯片竖直空间的利用，能够增加存储器的存储密度，以具有更强的存储性能。
目前，堆叠设置的多个半导体晶粒之间通常全部使用硅通孔形成信号连接，靠近的硅通孔之间易产生信号干扰。并且，堆叠设置的多个半导体晶粒之间通常使用粘贴胶进行粘连连接，胶体散热能力弱，影响存储器的性能。
如图1所示，提供了一个对比实施例中的封装结构，该封装结构比如可以应用于生产高带宽内存(High Bandwidth Memory，HBM)的过程中。封装结构包括基层100’和多个晶粒200’，多个晶粒200’层叠设置于基层100’，多个晶粒200’在基层100’上的投影重合。在晶粒200’与基层100’之间，以及晶粒200’与晶粒200’之间，通常采用粘贴胶600’进行粘接连接，相邻的晶粒200’之间的距离较近。上述堆叠方式以及连接方式导致晶粒200’的散热面积小，并且粘贴胶600’的导热性能差，当封装结构处于高负载运行时容易因散热性能不佳导致性能下降，影响用户体验。并且，在多个晶粒200’之间设置有导电通路300’，导电通路300’用于在晶粒200’与基层100’之间或者晶粒200’与晶粒200’之间形成电连接通道。由图1中示出的内容可知，多个导电通路300’之间的物理位置较近，在信号传输过程中容易产生信号干扰，影响信号传输质量。
为了改善对比实施例中存在的晶粒散热性能不佳，以及信号通路过于靠近的问题，本公开提供了一种封装结构，封装结构包括基层和多个晶粒，多个晶粒层叠设置于基层，相邻的两个晶粒在基层上的投影部分重合，间隔设置的两个晶粒在基层上的投影至少部分重合，间隔设置的两个晶粒通过电信号通路形成电连接，电信号通路包括第一电连接层，第一电连接层位于间隔设置的两个晶粒之间，且第一电连接层分别与间隔设置的两个晶粒电连接。本公开通过将多个晶粒交错设置，增大了晶粒间的距离，方便进行填充的同时还提升了散热性能；将多个晶粒错开设置后，在间隔设置的两个晶粒之间设置电信号通路形成电连接，从而能够将间隔设置的晶粒之间形成的多条电信号通路间的距离增大，避免了不同电信号通路之间距离较近而产生干扰，提高了封装结构的信号传输可靠性。
本公开示例性的实施例中，如图2至图5所示，本公开实施例提供了一种封装结构，封装结构可以应用于对存储器等半导体设备进行封装的过程，例如应用在DRAM(动态随机存取存储器，Dynamic Random Access Memory)、LPDDR(低功耗双倍数据速率内存，Low Power Double Data Rate)等存储器件的封装过程中。
本实施例中，如图2至图5所示，封装结构包括基层100和多个晶粒200，基层100作为封装结构的支撑结构，基层100可以为封装基板110(参照图2)，封装基板110中可以设置互联通孔(附图未示出)，互联通孔在封装基板110的厚度方向(图2中所示z方向)上贯穿封装基板110，使得封装结构内的多个晶粒200能够通过互联通孔与外部元器件(附图未示出)形成电连接，外部元器件比如电容、供电器件等。基层100也可以为控制芯片120(参照图4)，控制芯片120能够与晶粒200形成电连接并对其进行控制。其中，晶粒200中设置有集成电路，集成电路具有特定的功能，多个晶粒200组合可以使得封装结构具有相应的功能。
参照图2和图3，晶粒200层叠设置于基层100上(图2中所示z方向)，相邻的两个晶粒200在基层100上的投影部分重合。间隔设置的两个晶粒200在基层100上的投影至少部分重合，即间隔设置的两个晶粒200在基层100上的投影可以完全重合，也可以只有 部分重合，以在重合的部分之间形成导电通路，实现电信号传输。为便于对本公开的技术方案进行解释，本实施例中示例性地示出了基层100上设置有4个晶粒的情况，多个晶粒200由下向上(图2中所示z方向)依次为第一晶粒210、第二晶粒220、第三晶粒230和第四晶粒240。当然，在实施过程中，对于晶粒的数量没有限定，比如还可以设置六个。
参照图2和图3，相邻的晶粒200在基层100上的投影部分重合，从而相邻的两个晶粒200中，位于下层的晶粒200能够对位于上层的晶粒200提供支撑。比如，第一晶粒210能够对第二晶粒220提供支撑，第二晶粒220能够对第三晶粒230提供支撑，第三晶粒230能够对第四晶粒240提供支撑。
继续参照图2和图3，间隔设置的两个晶粒200在基层100上的投影至少部分重合，使得间隔设置的两个晶粒200之间能够设置电信号通路300以形成电连接，电信号通路300沿多个晶粒200的堆叠方向(图2中所示z方向)延伸。图2中示出了间隔设置的两个晶粒200在基层100(参照图3)上的投影完全重合的示例，比如，第一晶粒210和第三晶粒230在基层100上的投影完全重合，第二晶粒220和第四晶粒240在基层100上的投影重合。在一些其他可能的实施方式(图中未示出)中，间隔设置的两个晶粒200也可以只有部分重合，为了方便说明，可以参照图2，并以间隔设置的第二晶粒220和第四晶粒240为例，第四晶粒240可以图2中示出的方位为准向左(图2中所示x方向的反向)移动一段距离，但要保证第四晶粒240与第三晶粒230和第二晶粒22同时都具有重叠部分即可。
下面对电信号通路300的设置方式进行说明，电信号通路300包括第一电连接层310，第一电连接层310位于间隔设置的两个晶粒200之间，且第一电连接层310分别与间隔设置的两个晶粒200电连接。比如，第二晶粒220和第四晶粒240之间设置有第一电连接层310，第一晶粒210和第三晶粒230之间设置有第一电连接层310。参照图2，第一晶粒210的右侧(图2中所示x方向)区域和第三晶粒230的右侧区域直接相对，从而可以在第一晶粒210的右侧区域和第三晶粒230的右侧区域之间设置第一电连接层310，第一晶粒210和第三晶粒230通过第一电连接层310形成电连接。又比如，第四晶粒240的左侧(图2中所示x方向的反向)区域和第三晶粒230的左侧区域直接相对，从而可以在第四晶粒240的左侧区域和第二晶粒220的左侧区域之间设置第一电连接层310，第二晶粒220和第四晶粒240通过第一电连接层310形成电连接。第一晶粒210与第三晶粒230之间形成的电信号通路300与第二晶粒220与第四晶粒240之间形成的电信号通路300为相互独立两条导电通路，以图2中示出的方位为准，两个电信号通路300分别设置于封装结构内的左侧和右侧，两者之间的距离较远，信号干扰小。
参照图2，可以确定的是，将多个晶粒200采用上述交错堆叠方式形成导电互联时，不同的电信号通路300之间的距离(图2中所示x方向)增大，从而能够避免电信号通路300过于靠近出现信号干扰，提升封装结构的性能。并且，采用上述方式进行堆叠，还能够减小晶粒200之间的重叠面积，增大了每个晶粒200的散热面积和晶粒200之间的距离，提升封装结构的散热性能。
本公开实施例中，通过将多个晶粒交错设置，增大了晶粒暴露出的表面积和晶粒之间的距离，方便在晶粒之间进行封装填充的同时还提升了散热性能；并且，将多个晶粒错开设置后，能够在间隔设置的两个晶粒之间设置电信号通路形成电连接，从而能够将多个晶粒的电信号通路之间的距离增大，有效避免了不同电信号通路靠近产生干扰，提高了封装结构的信号传输可靠性。
在一个示例性实施例中，如图2至图5所示，本实施例提供了一种封装结构，封装结构包括基层100和多个晶粒200，多个晶粒200层叠设置于基层100，相邻的两个晶粒200在基层100上的投影部分重合，间隔设置的两个晶粒200在基层100上的投影至少部分重合，间隔设置的两个晶粒200通过电信号通路300形成电连接，电信号通路300包括第一 电连接层310，第一电连接层310位于间隔设置的两个晶粒200之间，且第一电连接层310分别与间隔设置的两个晶粒200电连接。
本实施例中，如图2所示，电信号通路300还包括导电插塞320，导电插塞320设置于晶粒200中，导电插塞320在晶粒200的厚度方向(图2中所示z方向)上贯穿晶粒200，导电插塞320通过硅通孔(Through Silicon Via，TSV)技术形成。
参照图2和图3，导电插塞320设置于间隔设置的两个晶粒200中靠近基层100的晶粒200。例如，在间隔设置的第一晶粒210和第三晶粒230中，导电插塞320设置于更靠近基层100的第一晶粒210中；在间隔设置的第二晶粒220和第四晶粒240中，导电插塞320设置于更靠近基层100的第二晶粒220中。通过将导电插塞320设置于间隔设置的两个晶粒200中靠近基层100的晶粒200中，使得位于上方的晶粒200能够通过导电插塞320与基层100之间进行电信号传输。
为便于对本公开的技术方案进行解释，将设置于第一晶粒210中的导电插塞320定义为第一导电插塞321，将设置于第二晶粒220中的导电插塞320定义为第二导电插塞322。
可以理解的是，参照图2和图3，当第四晶粒240上还设置有其他晶粒(附图未示出)时，第三晶粒230和第四晶粒240中也可以设置导电插塞，以使得设置在第四晶粒240上的其他晶粒能够与基层100之间形成电连接。比如，封装结构还包括依次堆叠的第五晶粒(附图未示出)和第六晶粒(附图未示出)，其中，第五晶粒与第三晶粒230连接，第六晶粒与第四晶粒240连接，为了使第五晶粒和第六晶粒与基层100之间能够进行电信号传输，需要在第三晶粒230和第四晶粒240中设置导电插塞。
在一个实施例中，如图2所示，相邻的两个晶粒200之间设置支撑层400。与对比实施例中的采用粘贴胶600’(参照图1)粘接的方式相比，本公开实施例中通过在相邻的两个晶粒200之间设置支撑层400，由于支撑层400具有一定的高度(图2中所示z方向)，使得相邻的晶粒200之间高度差增大，在相邻的两个晶粒200中，上方(图2中所示z方向)晶粒200的底面以及下方晶粒200的顶面能够暴露出来，方便在相邻的两个晶粒200之间填充封装材料。同时，还可以增大晶粒200的散热面积，提升了散热性能。另外，支撑层400可以由金属材料制成并采用焊接方式连接，支撑层400与粘贴胶600’相比，可以增大相邻晶粒200之间的连接强度，提升了封装结构的整体强度和可靠性。
在一个实施例中，如图2所示，沿多个晶粒200的层叠方向(图2中所示z方向)，任意相邻的两个晶粒200之间支撑层400的高度相等，可以确定的是，由于设置于多个晶粒200之间的支撑层400的高度均相等，从而多个支撑层400可以采用相同的制程工艺加工，工艺简单且布局方便，有利于提升良品率。
在一个可能的实施方式中，参照图2，将多个支撑层400的高度(图2中所示z方向)设置成相同时，还可以将多个第一电连接层310的高度设置成相等，使得多个晶粒200能够按照统一标准进行连接组装。比如，参照图2至图5，将第一电连接层310的高度设置为等于一个晶粒200的厚度与两个支撑层400的高度之和，使得多个晶粒200的左右两侧的支撑高度相同，从而多个晶粒200相互平行，便于多个晶粒的堆叠组装。当然，可以理解的是，在其他可能的实施例中，第一电连接层310的高度也可以稍大于一个晶粒200的厚度与两个支撑层400的高度之和，在不影响封装性能的同时，可以允许个别晶粒200存在一些倾斜，只要保证第一电连接层310的高度大于支撑层400的高度的两倍即可。
在一个实施例中，如图2所示，第一晶粒210与基层100之间也设置有支撑层400，第一晶粒210在多个晶粒200中位于最下方，从而第一晶粒210直接与基层100相邻，通过在第一晶粒210和基层100之间设置支撑层400，使得第一晶粒210与基层100不再紧密贴合，从而第一晶粒210可以通过其下表面进行散热，增强第一晶粒210的散热能力。并且，将第一晶粒210和基层100采用支撑层400进行连接，还能够提高第一晶粒210与基层100之间的结构强度。
可以理解的是，当第一晶粒210与基层100之间设置支撑层400时，第一晶粒210与基层100之间产生高度差，为了确保基层100与第一晶粒210之间能够实现良好的电信号导通，可以在第一晶粒210与基层100之间设置第二电连接层500，第二电连接层500用于将基层100的电信号传输至第一晶粒210，进而通过电信号通路300传输至第三晶粒230。其中，可以将支撑层400与第二电连接层500的高度设置成相同，使得第一晶粒210能够与基层100保持水平，提升多个晶粒200的堆叠可靠性。
其中，如图2所示，第二电连接层500包括独立的两个第三焊盘410，第三焊盘410的材料比如可以为铜。两个第三焊盘410中的一个与第一晶粒210的第一导电插塞321形成电连接，两个第三焊盘410中的另一个与基层100连接，以在基层100与第一晶粒210之间形成电信号传输。参照图3，示出了未进行连接的多个晶粒200与基层100的示意图，支撑层400也包括独立的两个第三焊盘410，两个第三焊盘410中的一个与第一晶粒210焊接连接，两个第三焊盘410中的另一个与基层100焊接连接，但支撑层400并不会在基层100与第一晶粒210之间形成电信号通路。
如图2所示，第二电连接层500包括两个第三焊盘410，以及位于两个第三焊盘410之间的第二焊接凸点420，同时，支撑层400也两个第三焊盘410，以及位于两个第三焊盘410之间的第二焊接凸点420，第二焊接凸点420用于将两个第三焊盘410焊接连接。参照图3，示出了未进行连接的多个晶粒200与基层100的示意图，第二焊接凸点420可以设置于第一晶粒210上的第三焊盘410，也可以设置于基层100上的第三焊盘410，不过多赘述。其中，第二焊接凸点420的材料比如可以是锡，熔点较低，只需要稍微加热就可以融化，以快速连接两个第三焊盘410，提升封装效率。其中，第二焊接凸点420的形状可以为柱状或者球状，可以根据封装需要进行选择。
在一个实施例中，如图2所示，第二晶粒220与基层100之间设置第一电连接层310，设置于第二晶粒220和基层100之间的第一电连接层310用于在第二晶粒220与基层100之间形成电信号传输。
参照图2，间隔设置的第二晶粒220和第四晶粒240之间也设置有第一电连接层310，设置于第二晶粒220和第四晶粒240之间的第一电连接层310用于在第二晶粒220和第四晶粒240之间形成电信号传输。参照图2，第二晶粒220与第四晶粒240之间的第一电连接层310与第二晶粒220的第二焊垫221(参考图3)相连，使得第二晶粒220和第四晶粒240之间形成一条电信号通路300，由于第二晶粒220的第二焊垫221与第二晶粒220中的第二导电插塞322相连形成电连接，从而第二晶粒220和第四晶粒240以及第二晶粒220与基层100之间的两条电信号通路300连通，使得第四晶粒240中的信号能够传输至基层100中。第一晶粒210和第三晶粒230同理，不再赘述。
位于第二晶粒220与基层100之间的第一电连接层310，与位于间隔设置的晶粒200之间的第一电连接层310可以采用相同的制程工艺。
在一个实施例中，参照图2，第一电连接层310包括第一焊盘311和第二焊盘312，第一焊盘311和第二焊盘312的材料可以为铜。第一电连接层310还包括第一焊接凸点313，第一焊接凸点313用于将第一焊盘311和第二焊盘312焊接连接，第一焊接凸点313可以为球形也可以为柱形，当第一焊盘311与第二焊盘312之间的距离较大时，可以将第一焊接凸点313设置为柱形。其中，第一焊接凸点313的材料比如可以为锡，可以使用生长工艺将第一焊接凸点313形成于第一焊盘311上，也可以形成于第二焊盘312上。
需要说明的是，参照图2至图5，第一焊盘311和第二焊盘312的高度可以相同，也可以不同，通常情况下，第一焊盘311和第二焊盘312的高度不相等，且第一焊盘311的高度大于第二焊盘312的高度。比如，参照图2和图3，第一焊盘311和第二焊盘312通常采用外延生长的工艺形成。如果需要同一个晶粒上同时形成两个高度较高的焊盘，会导致工艺复杂，在本公开提供的技术方案中，以间隔设置的第二晶粒220和第四晶粒240为 例，可以将高度较高的第一焊盘311形成于第四晶粒240上，并将高度较低的第二焊盘312形成于第二晶粒220上，以避免第二晶粒220的上下两侧均需要生长较高的焊盘，降低了工艺难度。
参照图3，在晶粒封装过程中，可以将第四晶粒240上的第一焊盘311与第二晶粒220上的第二焊盘312对齐，使得第一焊接凸点313位于第一焊盘311和第二焊盘312之间，通过对第一焊接凸点313进行加热使得第一焊接凸点313融化，待第一焊接凸点313冷却后即可将第一焊盘311和第二焊盘312紧固连接。
本公开前述实施例中提到第一电连接层310的高度大于支撑层400高度的两倍，其中，能够实现第一电连接层310的高度大于支撑层400的高度的方式包括增大第一焊盘311、第二焊盘312或第一焊接凸点313中任意一个或多个的高度，以使得第一电连接层310的高度大于支撑层400高度的两倍。在一个示例中，可以将第一电连接层310中第一焊接凸点313的高度设置成大于支撑层400中第二焊接凸点420的高度，使得第一电连接层310的高度大于支撑层400高度的两倍，以补充晶粒200的高度。
在一个示例性实施例中，如图2至图5所示，本实施例提供了一种封装结构，封装结构包括基层100和多个晶粒200，多个晶粒200层叠设置于基层100，相邻的两个晶粒200在基层100上的投影部分重合，间隔设置的两个晶粒200在基层100上的投影至少部分重合，间隔设置的两个晶粒200通过电信号通路300形成电连接，电信号通路包括第一电连接层310，第一电连接层310位于间隔设置的两个晶粒200之间，且第一电连接层310分别与间隔设置的两个晶粒200电连接。本实施例提供的封装结构可以包括上述各个实施例中提供的结构。
在一些可能的实施方式中，如图2和图3所示，间隔设置的两个晶粒200的正面相对设置。晶粒200的正面比如晶粒200设置有焊垫250(pad)的一面，晶粒200的焊垫250与晶粒200内部的集成电路(附图未示出)连接，可以通过焊垫250形成信号传输通路以进行信号传输。为便于对本公开的技术方案进行解释，将第一晶粒210上的焊垫250定义为第一焊垫211，第二晶粒220上的焊垫250定义为第二焊垫221，第三晶粒230上的焊垫250定义为第三焊垫231，第四晶粒240上的焊垫250定义为第四焊垫241。
首先，需要说明的是，参照图2，对于设置有导电插塞320的晶粒(例如第一晶粒210和第二晶粒220)，第一晶粒210上的第一焊垫211与第一导电插塞321电连接，使得第三晶粒230通过第一焊垫211即可与第一导电插塞321形成电连接，节省额外布线。第二晶粒220和第四晶粒240同理，不再赘述。
参照图2和图3，以间隔设置的第二晶粒220和第四晶粒240为例，在封装状态下，第四晶粒240处于倒装状态，使得位于第四晶粒240正面的第四焊垫241能够朝向第二晶粒220，第一电连接层310设置于第四晶粒240的正面，进而第四晶粒240能够依次通过第四焊垫241、第一电连接层310、第二焊垫221与第二晶粒220中的第二导电插塞322电连接。
在另一些可能的实施方式中，如图4和图5所示，间隔设置的两个晶粒200的正面均朝向基层100，也即，所有晶粒200均以倒装的形式进行封装。
其中，参照图4，间隔设置的两个晶粒200中，位于上方的晶粒200的焊垫250与第一电连接层310电连接，位于下方的晶粒200的导电插塞320与第一电连接层310电连接。
参照图4和图5，以间隔设置的第二晶粒220和第四晶粒240为例，在封装状态下，第一电连接层310位于第四晶粒240的正面(设置有第四焊垫241的一面)，且第一电连接层310位于第二晶粒220的背面，第四晶粒240能够通过第四焊垫241、第一电连接层310与第二晶粒220中的第二导电插塞322形成电连接。
在一个实施例中，参照图4，封装结构还包括封装层700，封装层700包覆晶粒200并填充相邻的晶粒200之间的区域，封装层700还填充晶粒200与基层100之间的区域， 以对晶粒200进行有效保护。可以理解的是，本公开上述实施例中提供了设置有支撑层400的封装结构，由于支撑层400使得相邻的晶粒200之间的间隔变大，以及使得晶粒200与基层100之间的间隔变大，从而更利于填充封装层700。封装层700的材料比如环氧树脂模塑料(Epoxy Molding Compound，简称EMC)，环氧树脂模塑料具有高耐热、高耐湿、高填充率、低膨胀、低应力、低杂质、低摩擦系数等优越性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的封装结构中，通过将多个晶粒交错设置，增大了晶粒间的距离，方便进行填充的同时还提升了散热性能；将多个晶粒错开设置后，在间隔设置的两个晶粒之间设置电信号通路形成电连接，从而能够将间隔设置的晶粒之间形成的多条电信号通路间的距离增大，避免了不同电信号通路之间距离较近而产生干扰，提高了封装结构的信号传输可靠性。

Claims (17)

  1. 一种封装结构，包括：
    基层(100)；
    多个晶粒(200)，层叠设置于所述基层(100)，相邻的两个所述晶粒(100)在所述基层(100)上的投影部分重合，间隔设置的两个所述晶粒(200)在所述基层(100)上的投影至少部分重合；
    间隔设置的两个所述晶粒(200)通过电信号通路(300)电连接，所述电信号通路(300)包括第一电连接层(310)，所述第一电连接层(310)位于间隔设置的两个所述晶粒(200)之间，且所述第一电连接层(310)分别与间隔设置的两个所述晶粒(200)电连接。
  2. 根据权利要求1所述的封装结构，其中，所述电信号通路(300)还包括导电插塞(320)，所述第一电连接层(310)与所述导电插塞(320)电连接；
    所述导电插塞(320)设置于间隔设置的两个所述晶粒(200)中靠近所述基层(100)的晶粒(200)，所述导电插塞(320)贯穿所述晶粒(200)。
  3. 根据权利要求1所述的封装结构，其中，相邻的两个所述晶粒(200)之间设置支撑层(400)。
  4. 根据权利要求3所述的封装结构，其中，沿多个所述晶粒(200)的层叠方向，任意相邻的两个所述晶粒(200)之间的所述支撑层(400)的高度相等，所述第一电连接层(310)的高度大于所述支撑层(400)的高度的两倍。
  5. 根据权利要求3或4所述的封装结构，其中，多个所述晶粒(200)中与所述基层(100)相邻的晶粒(200)为第一晶粒(210)，所述第一晶粒(210)与所述基层(100)之间设置所述支撑层(400)。
  6. 根据权利要求5所述的封装结构，其中，多个所述晶粒(200)中与所述第一晶粒(210)相邻的晶粒(200)为第二晶粒(220)，所述第二晶粒(220)与所述基层(100)之间设置所述第一电连接层(310)。
  7. 根据权利要求5或6所述的封装结构，其中，所述第一晶粒(210)与所述基层(100)之间设置第二电连接层(500)，所述第一晶粒(210)通过所述第二电连接层(500)与所述基层(100)电连接；
    沿多个所述晶粒(200)的层叠方向，所述第二电连接层(500)与所述支撑层(400)的高度相等。
  8. 根据权利要求7所述的封装结构，其中，所述第一电连接层(310)包括第一焊盘(311)和第二焊盘(312)，以及位于所述第一焊盘(311)和所述第二焊盘(312)之间的第一焊接凸点(313)；
    所述第一焊盘(311)和所述第二焊盘(312)分别与间隔设置的两个所述晶粒(200)连接，或者，
    所述第一焊盘(311)和所述第二焊盘(312)两者之一与所述晶粒(200)连接，两者另一与所述基层(100)连接。
  9. 根据权利要求8所述的封装结构，其中，所述第二电连接层(500)和所述支撑层(400)均包括独立设置的两个第三焊盘(410)，以及位于两个所述第三焊盘(410)之间的第二焊接凸点(420)；
    两个所述第三焊盘(410)中的一个与所述第一晶粒(210)的第一导电插塞(321)连接，两个所述第三焊盘(410)中的另一个与所述基层(100)连接。
  10. 根据权利要求9所述的封装结构，其中，沿多个所述晶粒(200)的层叠方向，所述第一焊接凸点(313)的高度大于所述第二焊接凸点(420)的高度。
  11. 根据权利要求1所述的封装结构，其中，间隔设置的两个所述晶粒(200)的正面相对设置。
  12. 根据权利要求1至11任一项所述的封装结构，其中，所述晶粒(200)的正面设置焊垫(250)，所述第一电连接层(310)分别与相对设置的两个所述焊垫(250)电连接。
  13. 根据权利要求2所述的封装结构，其中，间隔设置的两个所述晶粒(200)的正面均朝向所述基层(100)。
  14. 根据权利要求13所述的封装结构，其中，所述晶粒(200)的正面设置焊垫(250)，间隔设置的两个所述晶粒(200)中位于上方的晶粒(200)的所述焊垫(250)与所述第一电连接层(310)电连接。
  15. 根据权利要求13或14所述的封装结构，其中，间隔设置的两个所述晶粒(200)中位于下方的晶粒(200)的所述导电插塞(320)与所述第一电连接层(310)电连接。
  16. 根据权利要求1至15任一项所述的封装结构，其中，所述基层(100)包括封装基板(110)或控制芯片(120)。
  17. 根据权利要求1至16任一项所述的封装结构，其中，所述封装结构还包括封装层(700)，所述封装层(700)包覆所述晶粒(200)并填充相邻的所述晶粒(200)之间的区域；
    所述封装层(700)填充所述晶粒(200)与所述基层(100)之间的区域。
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CN102779802A (zh) * 2012-07-13 2012-11-14 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN109755182A (zh) * 2017-11-07 2019-05-14 中芯国际集成电路制造(上海)有限公司 芯片堆叠封装结构及其形成方法
CN210668369U (zh) * 2019-12-17 2020-06-02 江苏爱矽半导体科技有限公司 一种堆叠式封装结构
WO2021097730A1 (zh) * 2019-11-20 2021-05-27 华为技术有限公司 一种多芯片堆叠封装及制作方法

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CN102779802A (zh) * 2012-07-13 2012-11-14 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN109755182A (zh) * 2017-11-07 2019-05-14 中芯国际集成电路制造(上海)有限公司 芯片堆叠封装结构及其形成方法
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