WO2024031767A1 - 半导体结构和半导体结构的制造方法 - Google Patents

半导体结构和半导体结构的制造方法 Download PDF

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Publication number
WO2024031767A1
WO2024031767A1 PCT/CN2022/117375 CN2022117375W WO2024031767A1 WO 2024031767 A1 WO2024031767 A1 WO 2024031767A1 CN 2022117375 W CN2022117375 W CN 2022117375W WO 2024031767 A1 WO2024031767 A1 WO 2024031767A1
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Prior art keywords
power supply
wiring layer
frame
memory
substrate
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PCT/CN2022/117375
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English (en)
French (fr)
Inventor
庄凌艺
吕开敏
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长鑫存储技术有限公司
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Priority to US18/449,062 priority Critical patent/US20240055333A1/en
Publication of WO2024031767A1 publication Critical patent/WO2024031767A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

Definitions

  • the present disclosure belongs to the field of semiconductors, and specifically relates to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • HBM High Bandwidth Memory
  • Memory chip stacking technology represented by HBM extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thus greatly increasing the density of memory chips and achieving large capacity and high performance. bandwidth.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a power supply port; a memory module located on the substrate; the memory module includes a Memory chips stacked in one direction, the first direction is parallel to the upper surface of the substrate; each memory chip has a power supply signal line, and at least one of the plurality of memory chips has a power supply wiring layer, so The power supply signal line is electrically connected to the power supply wiring layer; the power supply wiring layer includes a connected first wiring layer and a second wiring layer, and the plane where the first wiring layer is located is perpendicular to the upper surface of the substrate; The second wiring layer is located on the surface of the memory chip away from the substrate; a lead is connected to the second wiring layer; a lead frame is connected to the lead and the power supply port.
  • the embodiments of the present disclosure also provide a manufacturing method of a semiconductor structure.
  • the manufacturing method includes: providing a substrate, the substrate having a power supply port; providing a memory module; the memory module includes a first Directionally stacked memory chips; each memory chip has a power supply signal line, at least one of the plurality of memory chips has a power supply wiring layer, and the power supply signal line is electrically connected to the power supply wiring layer;
  • the power supply wiring layer includes a connected first wiring layer and a second wiring layer.
  • the plane of the first wiring layer is perpendicular to the upper surface of the substrate; the second wiring layer is located on the side of the memory chip away from the substrate. surface; fix the memory module on the substrate, and the first direction is parallel to the upper surface of the substrate; provide leads and a lead frame, connect the leads to the second wiring layer; connect the The lead frame is connected to the lead wire and the power supply port.
  • the technical solution provided by the embodiments of the present disclosure has at least the following advantages: the stacking direction of multiple memory chips is parallel to the substrate. Therefore, the communication distance of multiple memory chips is the same, which facilitates unified communication delay and improves the operation rate.
  • the power supply wiring layer in the memory chip can lead the power supply signal line out of the memory chip to achieve wired power supply. Wired power supply has high stability and reliability.
  • the leads are combined with the lead frame, thereby increasing the flexibility of connection methods and the strength of the structure.
  • Figure 1 shows a schematic diagram of a semiconductor structure
  • Figures 2 and 5 respectively show different cross-sectional views of a semiconductor structure provided by an embodiment of the present disclosure
  • Figures 3, 4, and 6 respectively show schematic diagrams of different active surfaces of a memory chip provided by an embodiment of the present disclosure
  • FIG. 7 shows a top view of a lead frame, leads and power supply wiring layers provided by an embodiment of the present disclosure.
  • FIGS. 8-9 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • HBM adopts a parallel stacking method, that is, the front surfaces of multiple memory chips 200 are parallel to the upper surface of the substrate 300 .
  • the arrangement direction of the multiple memory chips 200 is perpendicular to the upper surface of the substrate 300 .
  • the communication distance between the uppermost memory chip 200 and the lowermost memory chip 200 and the logic chip 400 is greatly different, resulting in a large communication delay difference between different memory chips 200 and the logic chip 400.
  • how the semiconductor structure is powered can also affect its performance.
  • Embodiments of the present disclosure provide a semiconductor structure, in which multiple memory chips are stacked in a direction parallel to the upper surface of the substrate, that is, the arrangement direction of the multiple memory chips is parallel to the upper surface of the substrate. Therefore, the multiple memory chips are stacked in a direction parallel to the upper surface of the substrate.
  • the communication distance is the same, which facilitates unified communication delay and improves the operating speed.
  • the power supply wiring layer in the memory chip can change the layout of the power supply signal lines and lead the power supply signal lines out of the memory chip. That is, wired power supply can improve the reliability of the power supply.
  • the lead wire makes the connection between the lead frame and the memory module more flexible, and the lead frame can standardize the layout of the power supply path to ensure the stability of the power supply.
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a substrate 9 having a power supply port 92; a memory module 100 located on the substrate 9; the memory module 100 includes a first A plurality of memory chips 1 are stacked in the direction X, the first direction
  • the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 includes a connected first wiring layer 21 and a second wiring layer 22.
  • the plane where the first wiring layer 21 is located is perpendicular to the upper surface of the substrate 9; the second wiring The layer 22 is located on the surface of the memory chip 1 away from the substrate 9; the leads 74 are connected to the second wiring layer 22; the lead frame 7 is connected to the leads 74 and the power supply port 92.
  • the power supply wiring layer 2 can lead out the power supply signal line 12 to facilitate wired power supply to the memory chip 1, thereby improving power supply stability.
  • the surface of the memory chip 1 includes an opposite front and a back, and a side connected between them. The area of the front and the back is larger than the area of the side.
  • the plane of the first wiring layer 21 is perpendicular to the upper surface of the substrate 9 .
  • the first wiring layer 21 can be located on the front or back of the memory chip 1 for connecting the power supply signal line 12 .
  • the second wiring layer 22 leads the first wiring layer 21 to the side of the memory chip 1. That is, the second wiring layer 22 can be used as a pad connecting the first wiring layer 21 and the leads 74 to increase the welding area and reduce the difficulty of welding. And the contact resistance between the power supply wiring layer 2 and the lead 74 is reduced.
  • the leads 74 and the lead frame 7 can form a wired power supply path between the substrate 9 and the memory chip 1 .
  • the lead frame 7 has high strength and is not easily deformed, thereby regulating the direction of the wired power supply path; the lead wire 74 is easy to bend, which can improve the flexibility of connecting the lead frame 7 and the power supply wiring layer 2 .
  • the plurality of memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the plurality of memory chips 1 is parallel to the substrate 9 . Therefore, the side surface of the memory chip 1 faces the substrate 9. Since the area of the side surface of the memory chip 1 is smaller, it occupies a smaller area on the upper surface of the substrate 9, which is beneficial to increasing the number of stacked memory chips 1.
  • the semiconductor structure has a first direction X, a second direction Y, and a third direction Z.
  • the first direction X is the stacking direction of the memory chip 1 ; the second direction Y is perpendicular to the first direction
  • the surface of the memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together through molecular force or other forces.
  • the surface of the memory chip 1 may also have bonding portions 42, and under elevated temperature conditions, adjacent bonding portions 42 are bonded and connected together. That is to say, the dielectric layer 43 is made of insulating material and can play an isolation role; the bonding portion 42 is made of conductive material and can play an electrical connection role.
  • the dielectric layer 43 also exposes the end surface of the first wiring layer 21 facing away from the logic chip 3 and covers the surface of the first wiring layer 21 except the end surface.
  • the memory chip 1 may be a chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory).
  • adjacent memory chips 1 can be stacked front to back, which facilitates the unification of the bonding steps of the memory chips 1 and makes the production process simpler.
  • the stacking manner of adjacent memory chips 1 may also include front-to-front, or back-to-back.
  • the front side of the memory chip 1 can be understood as the active surface 13
  • the back side can be understood as the non-active surface opposite to the active surface.
  • the first wiring layer 21 may be located on the front side of the memory chip 1 , that is, extending along the active surface 13 of the memory chip 1 . Therefore, after the components in the memory chip 1 are manufactured, the original back-end process can be used to manufacture the first wiring layer 21 , making the process simpler. In addition, the first wiring layer 21 can only extend at the edge position close to the active surface 13 of the memory chip 1 without covering the entire active surface 13 of the memory chip 1 . Therefore, the first wiring layer 21 and the memory chip 1 The contact area is small, which reduces the impact of the heat generated by the first wiring layer 21 on the memory chip 1 .
  • the ratio of the width of the second wiring layer 22 in the first direction X to the width of the memory chip 1 in the first direction X is 0.8 ⁇ 2.
  • the width of the two wiring layers 22 is equal to the width of the memory chip 1 . In this way, sufficient welding area between the leads 74 and the power supply wiring layer 2 can be ensured, materials can be saved, and production costs can be reduced.
  • each memory chip 1 has a plurality of power supply signal lines 12 .
  • One end of the power supply signal lines 12 is led out from the active surface 13 for connecting to the power supply wiring layer 2 .
  • Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to components in the memory chip 1 .
  • the power supply signal line 12 may be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.
  • each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals.
  • One power supply wiring 20 is electrically connected to a power supply signal line 12.
  • Different power supply signal lines 12 have different voltage signals.
  • different power supply wirings 20 have different voltage signals.
  • the power supply wiring layer 2 includes a ground wiring 20G and a power wiring 20P.
  • the ground wiring 20G is electrically connected to the ground signal line 12G
  • the power wiring 20P is electrically connected to the power signal line 12P.
  • a memory chip 1 has its own power supply wiring layer 2, at least part of the power supply signal lines 12 of the memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have a power supply wiring layer 2, the power supply signal line 12 of the memory chip 1 can be led out through the power supply wiring layer 2 of other memory chips 1. In other words, the memory chip 1 can pass through the conductive via 41 and the key.
  • the junction 42 establishes an electrical connection relationship with other memory chips 1 , thereby electrically connecting its own power supply signal line 12 with the power supply signal line 12 of other memory chips 1 , and further electrically connecting with the power supply wiring layer 2 of other memory chips 1 .
  • At least one of the memory chips 1 on the outermost sides of the memory module 100 has a power supply wiring layer 2; the memory chip 1 has a conductive via 41, and the conductive via 41 is electrically connected to the power supply signal line 12 There is a bonding portion 42 between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive through hole 41; the power supply signal lines 12 of multiple memory chips 1 are electrically connected to the bonding portion 42 through the conductive through hole 41.
  • the power supply wiring layer 2 is located on the outermost memory chip 1 of the memory module 100, which is beneficial to reducing the distance between the power supply wiring layer 2 and the lead frame 7. Therefore, the length of the lead 74 is shortened to reduce power consumption, and the height of the entire package in the third direction Z is reduced.
  • the memory chips 1 on the outermost two sides of the memory module 100 have power supply wiring layers 2 .
  • the lead frames 7 are divided into two groups, and the two groups of lead frames 7 are respectively close to the memory chips 1 on the outermost front and rear sides, and are respectively connected to the two power supply wiring layers 2 .
  • the power supply signal lines 12 can be led out from the outermost two sides of the memory module 100 . Compared with drawing the power supply signal line 12 from one side of the memory module 100, drawing the power supply signal line 12 from both sides can provide more drawing positions, which is beneficial to reducing process difficulty and improving power supply reliability. In other embodiments, the power supply signal line 12 can also be led out from one side of the memory module 100 .
  • FIGS. 3 and 4 are respectively schematic diagrams of the active surfaces 13 of the memory chip 1 on the outermost sides shown in FIG. 2 .
  • Each memory chip 1 has a first power supply signal line group 121 and a second power supply signal line group 122.
  • the first power supply signal line group 121 and the second power supply signal line group 122 each include a plurality of power supply signal lines 12; all first power supply signal lines 12
  • the signal line group 121 is electrically connected to one power supply wiring layer 2; all the second power supply signal line group 122 is electrically connected to another power supply wiring layer 2.
  • the memory chips 1 on the outermost sides are the first memory chip 1a and the second memory chip 1b respectively.
  • the first power supply signal line group 121 of the first memory chip 1a is directly connected to the first memory chip 1a.
  • the power supply wiring layer 2 on the surface of the memory chip 1a is connected.
  • the first power supply signal line group 121 of the memory chip 1 other than the first memory chip 1a is connected to the first power supply signal of the first memory chip 1a through the bonding portion 42 and the conductive via 41.
  • the groups 121 are electrically connected, so that all the first power supply signal line groups 121 can be led out from the power supply wiring layer 2 on the surface of the first memory chip 1a.
  • the second power supply signal line group 122 of the second memory chip 1b is directly connected to the power supply wiring layer 2 on the surface of the second memory chip 1b.
  • the second power supply signal line group 122 is electrically connected to the second power supply signal group 122 of the second memory chip 1b through the bonding portion 42 and the conductive through hole 41, so that all the second power supply signal line group 122 can receive the signal from the second memory chip 1b.
  • the power supply wiring layer 2 on the surface of 1b is led out.
  • the first signal line group 121 and the second signal line group 122 are respectively led out from both sides of the memory module 100. This is beneficial to providing more sufficient connection positions for the leads 74 to increase the distance between adjacent leads 74. distance to avoid incorrect electrical connections.
  • Figure 6 is a schematic diagram of the active surfaces 13 of the memory chips 1 on the outermost sides shown in Figure 5.
  • the memory module 100 includes two chipsets 10 arranged in the first direction X.
  • the chips Each group 10 includes multiple memory chips 1; the power supply signal line 12 of the same chipset 10 is electrically connected to its nearest power supply wiring layer 2.
  • the memory module 100 includes a first chipset 10a and a second chipset 10b. All power supply signal lines 12 of the first memory chip 1a can be directly electrically connected to the power supply wiring layer 2 on the surface of the first memory chip 1a.
  • the first chip The power supply signal lines 12 of other memory chips 1 in the group 10a are electrically connected to the power supply signal lines 12 of the first memory chip 1a through the bonding portion 42 and the conductive via 41, so that all the power supply signal lines of the first chipset 10a can 12 is drawn out from the power supply wiring layer 2 on the surface of the first memory chip 1a.
  • all the power supply signal lines 12 of the second memory chip 1b can be directly electrically connected to the power supply wiring layer 2 on the surface of the second memory chip 1b, and the power supply signal lines 12 of other memory chips 1 in the second chipset 10b are bonded.
  • the portion 42 and the conductive via 41 are electrically connected to the power supply signal lines 12 of the second memory chip 1b, so that all the power supply signal lines 12 of the second chipset 10b can be led out from the power supply wiring layer 2 on the surface of the second memory chip 1b. Since the power supply signal lines 12 of the two chipsets 10 are drawn out separately, it is beneficial to improve the stability and reliability of the power supply.
  • the lead frame 7 will be described in detail below.
  • the lead frame 7 and the memory module 100 are arranged in the first direction X. That is to say, the lead frame 7 is arranged opposite to the outermost memory chip 1 of the memory module 100 . In this way, it is beneficial to reduce the distance between the lead frame 7 and the power supply wiring layer 2 to shorten the length of the lead 74 .
  • FIG. 7 is a top view of the lead frame 7 , the leads 74 and the power supply wiring layer 2 .
  • the power supply wiring layer 2 includes a plurality of power supply wirings 20 spaced apart in the second direction Y
  • the lead frame 7 includes a plurality of frame bars 70 spaced apart in the second direction Y
  • the connected frame bars 70 and power supply wiring 20 have the same voltage signal.
  • the power supply wiring 20 may be disposed facing the frame bars 70 one by one, thereby facilitating the arrangement of the leads 74 .
  • the frame bar 70 is a power frame bar 70P or a ground frame bar 70G.
  • the power frame bar 70P is electrically connected to the power wiring 20P
  • the ground frame bar 70G is electrically connected to the ground wiring 20G.
  • the power frame bars 70P and the ground frame bars 70G are alternately arranged in the second direction Y. That is, the end surfaces of the power supply wiring 20 away from the substrate 9 may also be alternately arranged in the second direction Y. Since there is a large difference between the power signal and the ground signal, alternating the two signals is beneficial to reducing the electromagnetic interference of the adjacent frame bars 70 .
  • the lead frame 7 includes a connected support frame 71 and a main frame 72; the support frame 71 is welded to the upper surface of the substrate 9; the main frame 72 extends in a direction perpendicular to the upper surface of the substrate 9, that is, the main frame 72 extends in the third direction Z; the width of the support frame 71 in the first direction X is greater than the width of the main frame 72 in the first direction X.
  • the support frame 71 extends in a direction parallel to the upper surface of the substrate 9, which is beneficial to increasing the welding area between the lead frame 7 and the substrate 9, thereby enhancing the firmness of the welding.
  • Example ground There are also solder bumps 51 and solder layers 52 between the support frame 71 and the substrate 9 .
  • the end of the support frame 71 is connected to the end of the main frame 72, that is, a strip of conductive material is bent into two sections to serve as the support frame 71 and the main frame 72 respectively.
  • the production process is simpler.
  • the orthographic projection of the main frame 72 on the upper surface of the base plate 9 is located at the center position of the supporting frame 71 within the orthographic projection of the upper surface of the base plate 9 . That is to say, the main frame 72 and the supporting frame 71 can form an inverted T shape, and the lead frame 7 has better stability.
  • the lead frame 7 also includes a welding frame 73.
  • the width of the welding frame 73 in the first direction X is greater than the width of the main body frame 72 in the first direction X; the welding frame 73 is welded to the lead 74; the main body The end of the frame 72 away from the support frame 71 is connected to the welding frame 73 . That is, the welding frame 73 extends in a direction parallel to the upper surface of the substrate 9, which is beneficial to increasing the welding area of the lead 74 and the lead frame 7 to facilitate welding.
  • the lead frame 7 may also include only the main frame 72 without including the welding frame 73 and the supporting frame 71 , that is, the opposite ends of the main frame 72 are welded to the upper surface of the substrate 9 and the leads 74 respectively.
  • each frame bar 70 may include a main frame 72 , a welding frame 73 and a support frame 71 .
  • the semiconductor structure further includes: a first sealing layer 81 surrounding the memory module 100 and exposing the surface of the memory module 100 away from the substrate 9 .
  • the first sealing layer 81 can protect the memory module 100 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed.
  • the first sealing layer 81 is in contact with the welding frame 73 .
  • the first sealing layer 81 can support the welding frame 73, thereby improving the stability of the structure; in addition, it is also helpful to reduce the distance between the welding frame 73 and the memory module 100, thereby reducing the length of the lead 74.
  • the bottom surface of the welding frame 73 may be located on the top surface of the first sealing layer 81 .
  • the side of the first sealing layer 81 away from the substrate 9 has a groove 75 , and the welding frame 73 is engaged in the groove 75 .
  • the welding frames 73 arranged on opposite sides in the second direction Y may contact the side walls of the groove 75 , and the bottom surface of the welding frame 73 may contact the bottom surface of the groove 75 . That is, the first sealing layer 81 can function to fix the welding frame 73 to improve the stability of the lead frame 7 .
  • the semiconductor structure further includes: a second sealing layer 82 covering the memory module 100 , the leads 74 , the lead frame 7 , the second wiring layer 22 and the first sealing layer 81 .
  • the second sealing layer 82 can improve the protection and isolation effect to ensure the performance of the semiconductor structure.
  • first sealing layer 81 and the second sealing layer 82 may be made of the same material.
  • first sealing layer 81 and the second sealing layer 82 may be epoxy resin.
  • the materials of the first sealing layer 81 and the second sealing layer 82 may be different.
  • the second sealing layer 82 has a higher thermal conductivity than the first sealing layer 81 .
  • the semiconductor structure also includes: a logic chip 3, located between the upper surface of the substrate 9 and the memory module 100; the logic chip 3 has a first wireless communication part 31; the memory chip 1 has a second wireless communication part. part 11; the second wireless communication part 11 performs wireless communication with the first wireless communication part 31.
  • the second wireless communication part 11 is located on a side of the memory chip 1 facing the logic chip 3 . As a result, the distance between the first wireless communication unit 31 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.
  • the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delays of the memory chips 1 and the logic chip 3 of different layers will be greatly different; in addition, as the number of layers increases, the The number of through-silicon vias (TSV, Through-Silicon Vias) used for communication will increase proportionally, thus sacrificing wafer area.
  • TSV through-silicon vias
  • the stacking direction and communication method of the memory chip 1 are changed, which is beneficial to improving communication quality and saving wafer area.
  • the side of the memory chip 1 is placed toward the logic chip 3, and the area of the side is smaller; and using wireless communication, there is no need to set up a wired communication unit between the memory chip 1 and the logic chip 3, so that Reducing the process difficulty can also provide sufficient space for the connection structure between the memory chip 1 and the logic chip 3 to improve the structural strength of the two.
  • the lower side of the storage module 100 is used for wireless communication, and the upper side of the storage module 100 is used to lay out the wired power supply path, thereby reducing the electromagnetic interference caused by the current in the wired power supply path to the coil in the wireless communication unit and avoiding signals. loss.
  • the adhesive layer 6 there is an adhesive layer 6 between the memory module 100 and the logic chip 3 . That is, the memory module 100 and the logic chip 3 are connected together through adhesive means to form a memory core.
  • the adhesive layer 6 may be a die attach film (DAF).
  • DAF die attach film
  • the adhesive layer 6 can also be doped with metal ions to improve the heat dissipation effect of the memory module 100 and the logic chip 3 .
  • drawing the power supply signal line 12 from the top of the memory module 100 can leave sufficient space below the memory module 100 to connect the logic chip 3, thereby improving the structural strength.
  • soldering bumps 51 and solder layers 52 between the logic chip 3 and the substrate 9 that is, the logic chip 3 is soldered to the substrate 9 through flip-chip soldering.
  • the substrate 9 can provide power supply and signal exchange to the logic chip 3 through a wired method, and the wired method has higher reliability.
  • connection method of the lead 74 is used at the upper end of the lead frame 7, so that the connection method between the lead frame 7 and the memory module 100 is more flexible; at the same time, the lower end of the lead frame 7 uses welding bumps 51
  • the connection method makes the connection between the lead frame 7 and the substrate 9 more stable; the two connection methods cooperate to make the wired power supply path have both flexibility and stability.
  • FIGS. 8-9 and 2 another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • This manufacturing method can manufacture the semiconductor structure provided in the previous embodiment.
  • this semiconductor structure please refer to the foregoing embodiments.
  • a memory module 100 is provided; the memory module 100 includes a plurality of memory chips 1 stacked along a first direction X; each memory chip 1 has a power supply signal line 12 inside, and at least one of the plurality of memory chips 1
  • the power supply wiring layer 2 has a power supply wiring layer 2, the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 includes a connected first wiring layer 21 and a second wiring layer 22, and the plane where the first wiring layer 21 is located is perpendicular to the substrate 9
  • the second wiring layer 22 is located on the surface of the memory chip 1 away from the substrate 9 .
  • a plurality of memory chips 1 are provided; a first wiring layer 21 is formed on at least one of the plurality of memory chips 1.
  • the plurality of memory chips 1 are stacked and bonded.
  • the power supply signal lines 12 of each layer of memory chips 1 are led out to the top and bottom memory chips 1 through the conductive vias 41 and the bonding portions 42, and then are led out through the power supply wiring layer 2 processed on the top and bottom memory chips 1. to the edge of memory chip 1. It should be noted that during the bonding process, the memory chip 1 is placed horizontally.
  • a first molding process is performed on the memory module 100 to form a first sealing layer 81 surrounding the memory module 100.
  • the first sealing layer 81 also exposes the surface of the memory chip 1 and the first wiring layer 21 away from the substrate 9; After the first molding process, a second wiring layer 22 is formed on the surface of the memory chip 1 away from the substrate 9 .
  • the memory module 100 is rotated 90° so that each memory chip 1 is perpendicular to the logic chip 3, and the memory chip 1 and the logic chip 3 are fixed through the DAF film; the multiple memory modules 100 are reconstructed through the first molding process. , forming a reconstructed wafer; depositing a second wiring layer 22 on the top surface of the reconstructed wafer as a bonding pad through a rewiring process.
  • a base plate 9 is provided, and the base plate 9 has a power supply port 92 ; the memory module 100 is fixed on the base plate 9 , and the first direction X is parallel to the upper surface of the base plate 9 .
  • a lead 74 and a lead frame 7 are provided, and the lead 74 is connected to the second wiring layer 22; the lead frame 7 is connected to the lead 74 and the power supply port 92.
  • the reconstructed wafer is diced to form memory cores, each of which includes a memory module 100 and a logic chip 3 .
  • the memory chip is soldered to the substrate 9 on which the lead frame 7 has been pre-soldered by flip-chip welding, and the power supply wiring 20 is connected to the corresponding frame bar 70 through the lead 74 to realize the connection between the memory chip 1 and the substrate 9 Connection of power supply signal.
  • a second sealing layer 82 covering the memory module 100, the leads 74, the lead frame 7 and other structures is formed through a second molding process.
  • the reason why two molding processes are used in succession is that the first molding process can connect multiple memory modules 100 together. Therefore, the second wiring layer can be formed on multiple memory modules 100 at the same time subsequently. 22, thus helping to reduce process steps.
  • the volume of a single storage module 100 is small. When multiple storage modules 100 are connected together, the total volume becomes larger, the stability is higher, and it is less likely to tip over.
  • the first sealing layer 81 formed by the first molding process can protect and fix the memory module 100 in the subsequent steps of forming the second wiring layer 22 and flip-chip welding to prevent the memory module 100 from collapsing or being damaged. damage, thereby ensuring the performance of the memory module 100.
  • two molding processes in succession can improve the sealing effect.
  • the bottom surface of the substrate 9 may have solder balls 91 to solder the substrate 9 to the peripheral circuit board.
  • the multi-layer memory chip 1 and the logic chip 3 are vertically stacked to form a memory core, and then the power supply wiring layer 2 is led out to the substrate 9 through the lead frame 7 for packaging.
  • the signal communication between the memory chip 1 and the logic chip 3 is implemented wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the memory chip 1 in parallel stacking.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开实施例涉及半导体领域，提供一种半导体结构和半导体结构的制造方法，半导体结构包括：基板，所述基板具有供电端口；存储模块，位于所述基板上；所述存储模块包括沿第一方向堆叠的存储芯片，所述第一方向平行于所述基板的上表面；每个所述存储芯片内具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层包括相连的第一布线层和第二布线层，所述第一布线层所在的平面垂直于所述基板的上表面；所述第二布线层位于所述存储芯片远离所述基板的表面；引线，与所述第二布线层相连；引线框架，与所述引线和所述供电端口相连。本公开实施例至少可以提高半导体结构的性能。

Description

半导体结构和半导体结构的制造方法
交叉引用
本申请引用于2022年8月10日递交的名称为“半导体结构和半导体结构的制造方法”的第202210957711.2号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开属于半导体领域，具体涉及一种半导体结构的制造方法和半导体结构。
背景技术
为提高半导体结构的集成度，可以在同一封装结构内放置一个以上的存储芯片。HBM(High Bandwidth Memory，高带宽内存)是一款新型的内存。以HBM为代表的存储芯片堆叠技术，将原本一维的存储器布局扩展到三维，即将很多个存储芯片堆叠在一起并进行封装，从而大幅度提高了存储芯片的密度，并实现了大容量和高带宽。
然而，随着堆叠层数的增加，HBM的性能有待提升。
发明内容
本公开实施例提供一种半导体结构和半导体结构的制造方法，至少有利于提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，其中，半导体结构包括：基板，所述基板具有供电端口；存储模块，位于所述基板上；所述存储模块包括沿第一方向堆叠的存储芯片，所述第一方向平行于所述基板的上表面；每个所述存储芯片内具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层包括相连的第一布线层和第二布线层，所述第一布线层所在的平面垂直于所述基板的上表面；所述第二布线层位于所述存储芯片远离所述基板的表面；引线，与所述第二布线层相连；引线框架，与所述引 线和所述供电端口相连。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，制造方法包括：提供基板，所述基板具有供电端口；提供存储模块；所述存储模块包括沿第一方向堆叠的存储芯片；每个所述存储芯片内具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层包括相连的第一布线层和第二布线层，所述第一布线层所在的平面垂直于所述基板的上表面；所述第二布线层位于所述存储芯片远离所述基板的表面；将所述存储模块固定在所述基板上，且所述第一方向平行于所述基板的上表面；提供引线和引线框架，将所述引线与所述第二布线层相连；将所述引线框架与所述引线和所述供电端口相连。
本公开实施例提供的技术方案至少具有以下优点：多个存储芯片的堆叠方向平行于基板，因此，多个存储芯片的通信距离相同，从而利于统一通信延时，且提高运行速率。此外，存储芯片内的供电布线层可以将供电信号线引出至存储芯片外，从而实现有线供电。有线供电的稳定性、可靠性较高。此外，引线与引线框架相结合，从而提高连接方式的灵活性以及结构的强度。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种半导体结构的示意图；
图2、图5分别示出了本公开一实施例提供的半导体结构的不同剖面图；
图3、图4、图6分别示出了本公开一实施例提供的存储芯片的不同有源面的示意图；
图7示出了本公开一实施例提供的引线框架、引线和供电布线层的俯视图。
图8-图9示出了本公开另一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
参考图1，HBM采用平行堆叠方式，即，多个存储芯片200的正面平行于基板300的上表面，换言之，多个存储芯片200的排列方向垂直于基板300的上表面。当堆叠层数较多时，最上层的存储芯片200和最下层的存储芯片200与逻辑芯片400的通信距离相差较大，导致不同的存储芯片200与逻辑芯片400的通信延时相差较大，从而影响产品的运行速率。此外，半导体结构的供电方式也会影响其性能。
本公开实施例提供一种半导体结构，其中，多个存储芯片在平行于基板的上表面的方向上堆叠，即多个存储芯片的排列方向平行于基板的上表面，因此，多个存储芯片的通信距离相同，从而利于统一通信延时，且提高运行速率。此外，存储芯片内的供电布线层可以改变供电信号线的布局，并将供电信号线引出至存储芯片外，即，通过有线供电的方式能够提高供电的可靠性。此外，引线使得引线框架与存储模块的连接方式更为灵活，而引线框架能够规范供电路径的布局，从而保证供电的稳定性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图2-图7所示，本公开一实施例提供一种半导体结构，半导体结构包括：基板9，基板9具有供电端口92；存储模块100，位于基板9上；存储模块100包括沿第一方向X堆叠的多个存储芯片1，第一方向X平行于基板9的上表面；每个存储芯片1内具有供电信号线12，多个存储芯片1中的至少一者具有供电布线层2，供电信号线12与供电布线层2电连接；供电布线层2包括相连的第一布线层21和第二布线层22，第一布线层21所在的平面垂直于基板9的上表面；第二布线层22位于存储芯片1远离基板9的表面；引线74，与第二布线层22相连；引线框架7，与引线74和供电端口92相连。
这样的设计至少包括以下几个方面的效果：
第一，供电布线层2可以引出供电信号线12，以便于为存储芯片1 进行有线供电，从而提高供电稳定性。具体地，存储芯片1的表面包括相对的正面和背面，以及连接在二者之间的侧面，正面和背面的面积大于侧面的面积。第一布线层21所在的平面垂直于基板9的上表面，换言之，第一布线层21可以位于存储芯片1的正面或背面，以用于连接供电信号线12。第二布线层22将第一布线层21引出至存储芯片1的侧面，即第二布线层22可以作为连接第一布线层21与引线74的焊盘，以增大焊接面积，降低焊接难度，并降低供电布线层2与引线74的接触电阻。
第二，引线74、引线框架7可在基板9与存储芯片1之间构成有线供电路径。引线框架7的强度较高，不易发生变形，从而能够规范有线供电路径的走向；引线74易弯折，能够提高连接引线框架7和供电布线层2的灵活性。
第三，多个存储芯片1的沿第一方向X堆叠，即多个存储芯片1的排列方向平行于基板9。由此，存储芯片1的侧面朝向基板9，由于存储芯片1的侧面的面积较小，所占据的基板9上表面的面积较小，从而有利于提高存储芯片1的堆叠数量。
以下将结合附图对半导体结构进行详细说明。
首先，需要说明的是，半导体结构内具有第一方向X、第二方向Y和第三方向Z。其中，第一方向X为存储芯片1的堆叠方向；第二方向Y垂直于第一方向X，且平行于逻辑芯片3的上表面，第三方向Z垂直于逻辑芯片3的上表面。
参考图2和图5，多个存储芯片1可以采用混合键合的方式进行堆叠。举例而言，存储芯片1的表面还具有介质层43，相邻存储芯片1的介质层43可以通过分子力等作用力连接在一起。此外，存储芯片1的表面还可以具有键合部42，在升温条件下，相邻键合部42键合连接在一起。也就是说，介质层43为绝缘材料，能够起到隔离作用；键合部42为导电材料，能够起到电气连接的作用。此外，介质层43还露出第一布线层21背向逻辑芯片3的端面，并覆盖第一布线层21除端面之外的表面。
存储芯片1可以为DRAM(Dynamic Random Access Memory，动态随机存储器)或SRAM(Static Random-Access Memory，静态随机存储器)等芯片。在一些实施例中，相邻存储芯片1的堆叠方式可以均为正面对背面，从而有 利于统一存储芯片1的键合步骤，生产工艺更加简单。在一些实施例中，相邻存储芯片1的堆叠方式还可以包括正面对正面，或背面与背面。在一个实施例中，存储芯片1的正面可以理解为有源面13，背面可以理解为与有源面相对的非有源面。
参考图2-图6，第一布线层21可以位于存储芯片1正面，即沿着存储芯片1的有源面13延伸。因此，在存储芯片1内的元件制造完成后，可以利用原有的后段工艺制造第一布线层21，工艺更加简单。另外，第一布线层21可以只在靠近存储芯片1的有源面13一侧的边缘位置延伸，而无需覆盖整个存储芯片1的有源面13，因此，第一布线层21与存储芯片1的接触面积小，降低第一布线层21的发热量对存储芯片1的影响。
参考图2和图5，第二布线层22在第一方向X上的宽度与存储芯片1在第一方向X上的宽度之比为0.8～2，示例地，在第一方向X上，第二布线层22的宽度等于存储芯片1的宽度。如此，既能够保证引线74与供电布线层2具有充足焊接面积，也能够节约材料，降低生产成本。
参考图3-图4和图6，每个存储芯片1内均具有多个供电信号线12，供电信号线12的一端在有源面13上引出，以用于连接供电布线层2。不同供电信号线12可以为存储芯片1内的元件提供不同的电压信号，比如，数字信号或模拟信号。供电信号线12可以为接地信号线12G或电源信号线12P。不同的接地信号线12G具有不同的电压信号，不同的电源信号线12P具有不同的电压信号。
继续参考图3-图4和图6，每个供电布线层2包括多条间隔设置的供电布线20，一供电布线20与一供电信号线12电连接，不同供电信号线12具有不同的电压信号，相应的，不同供电布线20具有不同的电压信号。供电布线层2包括接地布线20G和电源布线20P，接地布线20G与接地信号线12G对应电连接，电源布线20P与电源信号线12P对应电连接。
若一个存储芯片1自身具有供电布线层2，则此存储芯片1的至少部分供电信号线12可以直接与自身的供电布线层2连接，即，通过自身的供电布线层2引出。若一个存储芯片1自身不具有供电布线层2，则此存储芯片1的供电信号线12可以通过其他存储芯片1的供电布线层2引出，换言之，此存储芯片1可以通过导电通孔41以及键合部42与其他的存储芯片1 建立电连接关系，从而将自身的供电信号线12与其他存储芯片1的供电信号线12电连接，进而与其他存储芯片1的供电布线层2电连接。
以下将对存储芯片1与供电布线层2的位置及数量关系进行详细说明。
参考图2和图5，存储模块100最外两侧的存储芯片1中的至少一者具有供电布线层2；存储芯片1内具有导电通孔41，导电通孔41与供电信号线12电连接；相邻存储芯片1之间具有键合部42，键合部42与导电通孔41相连；多个存储芯片1的供电信号线12通过导电通孔41和键合部42电连接。
相比于供电布线层2位于存储模块100内中间位置的存储芯片1上，供电布线层2位于存储模块100最外侧的存储芯片1上有利于减小供电布线层2与引线框架7的距离，从而缩短引线74长度，以降低功耗，并降低整个封装体的在第三方向Z上的高度。
在一些实施例中，存储模块100最外两侧的存储芯片1具有供电布线层2。引线框架7为两组，且两组引线框架7分别靠近最外首尾两侧的存储芯片1，并分别与两个供电布线层2相连。
也就是说，可以从存储模块100的最外两侧引出供电信号线12。相比于从存储模块100的一侧引出供电信号线12，从两侧引出供电信号线12能够提供更多的引出位置，有利于降低工艺难度，并提升供电的可靠性。在另一些实施例中，也可以从存储模块100的一侧引出供电信号线12。
具体地，参考图2-图4，图3和图4分别为图2所示的最外两侧的存储芯片1的有源面13的示意图。每个存储芯片1具有第一供电信号线组121和第二供电信号线组122，第一供电信号线组121和第二供电信号线组122均包括多个供电信号线12；所有第一供电信号线组121与一供电布线层2电连接；所有第二供电信号线组122与另一供电布线层2电连接。
示例地，最外两侧的存储芯片1分别为第一存储芯片1a和第二存储芯片1b，结合参考图2和图3，第一存储芯片1a的第一供电信号线组121直接与第一存储芯片1a表面的供电布线层2相连，第一存储芯片1a以外的存储芯片1的第一供电信号线组121通过键合部42和导电通孔41与第一存储芯片1a的第一供电信号组121电连接，从而使得所有第一供电信号线组121都能从第一存储芯片1a表面的供电布线层2引出。同理，结合参考图2 和图4，第二存储芯片1b的第二供电信号线组122直接与第二存储芯片1b表面的供电布线层2相连，第二存储芯片1b以外的存储芯片1的第二供电信号线组122通过键合部42和导电通孔41与第二存储芯片1b的第二供电信号组122电连接，从而使得所有第二供电信号线组122都能从第二存储芯片1b表面的供电布线层2引出。
也就是说，从存储模块100的两侧分别引出第一信号线组121和第二信号线组122，如此，有利于为引线74提供更充足的连接位置，以增大相邻引线74之间距离，避免发生错误的电连接。
参考图5-图6，图6为图5所示的最外两侧的存储芯片1的有源面13的示意图，存储模块100包括在第一方向X排布的两个芯片组10，芯片组10均包括多个存储芯片1；同一芯片组10的供电信号线12与其距离最近的供电布线层2电连接。
示例地，存储模块100包括第一芯片组10a和第二芯片组10b，第一存储芯片1a的所有供电信号线12可以直接与第一存储芯片1a表面的供电布线层2电连接，第一芯片组10a内的其他存储芯片1的供电信号线12通过键合部42和导电通孔41与第一存储芯片1a的供电信号线12电连接，从而可以使得第一芯片组10a的所有供电信号线12从第一存储芯片1a表面的供电布线层2引出。同理，第二存储芯片1b的所有供电信号线12可以直接与第二存储芯片1b表面的供电布线层2电连接，第二芯片组10b内的其他存储芯片1的供电信号线12通过键合部42和导电通孔41与第二存储芯片1b的供电信号线12电连接，从而可以使得第二芯片组10b的所有供电信号线12从第二存储芯片1b表面的供电布线层2引出。由于两个芯片组10的供电信号线12是单独引出的，从而有利于提高供电的稳定性和可靠性。
以下将对引线框架7进行详细说明。
参考图2和图5，引线框架7与存储模块100在第一方向X上排列。也就是说，引线框架7与存储模块100最外侧的存储芯片1相对设置。如此，有利于减小引线框架7与供电布线层2的距离，以缩短引线74长度。
参考图7，图7为引线框架7、引线74和供电布线层2的俯视图。由于供电布线层2包括多个在第二方向Y间隔设置的供电布线20，相应地，引线框架7包括多个在第二方向Y间隔设置的框架条70，相连的框架条70 和供电布线20具有相同的电压信号。示例地，在第一方向X上，供电布线20可以与框架条70一一正对设置，从而便于布置引线74。
框架条70为电源框架条70P或接地框架条70G，电源框架条70P与电源布线20P电连接，接地框架条70G与接地布线20G与电连接。电源框架条70P与接地框架条70G在第二方向Y上交替排列，即，供电布线20远离基板9的端面也可以在第二方向Y上交替排列。由于电源信号与接地信号的差异较大，因此二者交替排列有利于降低相邻框架条70的电磁干扰。
参考图2和图5，引线框架7包括相连的支撑架71和主体架72；支撑架71焊接在基板9的上表面；主体架72在垂直于基板9上表面的方向上延伸，即主体架72在第三方向Z延伸；支撑架71在第一方向X上的宽度大于主体架72在第一方向X的宽度。
即，支撑架71在平行于基板9上表面的方向上延伸，从而有利于增大引线框架7与基板9的焊接面积，以增强焊接的牢固性。示例地。支撑架71与基板9之间还具有焊接凸块51和焊料层52。
参考图2，在一些实施例中，支撑架71的端部与主体架72的端部连接，即，将一个条状的导电材料弯折成两段以分别作为支撑架71和主体架72，生产工艺更简单。
参考图5，在另一些实施例中，主体架72在基板9上表面的正投影位于支撑架71在基板9上表面的正投影内的中心位置。也就是说，主体架72和支撑架71可以构成倒T型，引线框架7的平稳性更好。
继续参考图2和图5，引线框架7还包括焊接架73，焊接架73在第一方向X上的宽度大于主体架72在第一方向X上的宽度；焊接架73与引线74焊接；主体架72远离支撑架71的一端与焊接架73相连。即，焊接架73在平行于基板9上表面的方向上延伸，从而有利于增大引线74与引线框架7的焊接面积，以便于进行焊接。
在另一些实施例种，引线框架7还可以只包括主体架72，而不包括焊接架73和支撑架71，即主体架72的相对两端分别与基板9上表面和引线74焊接。
值得说明的是，由于引线框架7包括多个间隔设置的框架条70，换言之，每个框架条70均可以包括主体架72、焊接架73以及支撑架71。
继续参考图2和图5，半导体结构还包括：第一密封层81，第一密封层81环绕存储模块100，并露出存储模块100远离基板9的表面。第一密封层81能够保护存储模块100不受外界环境的影响，比如抵抗外部湿气、溶剂，还能够抵抗半导体结构安装时的热冲击和机械振动。
示例地，第一密封层81与焊接架73相接触。如此，第一密封层81能够对焊接架73起到支撑作用，从而提高结构的稳定性；此外，也有利于减小焊接架73与存储模块100的距离，从而减小引线74长度。
举例而言，参考图2，焊接架73的底面可以位于第一密封层81的顶面。在另一些实施例中，参考图5，第一密封层81远离基板9的一侧具有凹槽75，焊接架73卡合在凹槽75内。示例地，焊接架73排列在第二方向Y的相对两侧可以与凹槽75的侧壁相接触，焊接架73的底面可以与凹槽75的底面相接触。即，第一密封层81能够起到固定焊接架73的作用，以提高引线框架7的稳定性。
参考图2和图5，半导体结构还包括：第二密封层82，第二密封层82覆盖存储模块100、引线74、引线框架7、第二布线层22以及第一密封层81。第二密封层82能够提高保护和隔离效果，以保证半导体结构的性能。
在一个实施例中，第一密封层81与第二密封层82的材料可以相同，例如，第一密封层81和第二密封层82可以是环氧类树脂。
在一个实施例中，第一密封层81与第二密封层82的材料可以不相同，例如，第二密封层82的导热率高于第一密封层81，通过这样的设置，通过引线框架7引入到第二密封层82中的热量可以更快的传递到外界环境中，降低高温环境对存储模块100的不良影响。
参考图2和图5，半导体结构还包括：逻辑芯片3，位于基板9的上表面与存储模块100之间；逻辑芯片3内具有第一无线通信部31；存储芯片1内具有第二无线通信部11；第二无线通信部11与第一无线通信部31进行无线通信。
由于多个存储芯片1与逻辑芯片3的距离相同，因此，多个存储芯片1与逻辑芯片3的无线通信的延时保持一致。在一些实施例中，第二无线通信部11位于存储芯片1朝向逻辑芯片3的一侧。由此，可以减小第一无线通信部31与第二无线通信部11之间的距离，从而提升无线通信的质量。
需要说明的是，若多个存储芯片1的排列方向垂直于逻辑芯片3的上表面，则不同层的存储芯片1与逻辑芯片3的通讯延迟相差较大；此外，随着层数增加，用于通讯的硅通孔(TSV，Through-Silicon Vias)的数量会正比例增高，从而牺牲晶圆面积。而本公开实施例中，改变了存储芯片1的堆叠方向和通信方式，从而有利于提高通信质量，还可以节约晶圆面积。
继续参考图2和图5，存储芯片1的侧面朝向逻辑芯片3设置，侧面的面积较小；而采用无线通信的方式则无需在存储芯片1与逻辑芯片3之间设置有线通信部，从而可以降低工艺难度，还可以为存储芯片1与逻辑芯片3之间的连接结构提供充足的空间位置，以提高二者结构强度。此外，存储模块100的下侧用于进行无线通信，存储模块100的上侧用于布局有线供电路径，从而能够降低有线供电路径中的电流对无线通信部中的线圈产生的电磁干扰，避免信号损失。
在一些实施例中，存储模块100与逻辑芯片3之间还具有粘结层6。即，存储模块100和逻辑芯片3通过胶粘的方式连接在一起，从而构成一个内存芯粒。示例地，粘结层6可以为固晶用胶膜(die attach film，DAF)。粘结工艺较为简单，能够节约成本。此外，粘结层6中还可以掺杂有金属离子，以提高存储模块100和逻辑芯片3的散热效果。在另一些实施例中，存储模块100与逻辑芯片3之间可以具有焊接层(图中未示出)，即存储模块100和逻辑芯片3通过焊接的方式连接在一起。
也就是说，从存储模块100的上方引出供电信号线12，能够在存储模块100的下方留下充足的空间位置以连接逻辑芯片3，从而提高结构强度。
继续参考图2和图5，逻辑芯片3与基板9之间还具有焊接凸块51和焊料层52，即逻辑芯片3通过倒装焊接的方式焊接在基板9上。如此，基板9可以通过有线方式对逻辑芯片3进行供电以及信号交换，有线方式的可靠性较高。
综上所述，在本公开实施例中，在引线框架7的上端采用引线74的连接方式，使得引线框架7与存储模块100的连接方式更灵活；同时引线框架7的下端采用焊接凸块51的连接方式，使得引线框架7与基板9的连接稳定性更高；两种连接方式相配合从而使得有线供电路径兼具灵活性和稳定性。
如图8-图9和图2所示，本公开另一实施例提供一种半导体结构的制造方法，此制造方法可以制造前述实施例提供的半导体结构。有关此半导体结构的详细说明可参考前述实施例。
具体地，参考图8，提供存储模块100；存储模块100包括沿第一方向X堆叠的多个存储芯片1；每个存储芯片1内具有供电信号线12，多个存储芯片1中的至少一者具有供电布线层2，供电信号线12与供电布线层2电连接；供电布线层2包括相连的第一布线层21和第二布线层22，第一布线层21所在的平面垂直于基板9的上表面；第二布线层22位于存储芯片1远离基板9的表面。
具体地，提供多个存储芯片1；在多个存储芯片1中的至少一者上形成第一布线层21，形成第一布线层21后，将多个存储芯片1堆叠且键合。示例地，各层存储芯片1的供电信号线12通过导电通孔41和键合部42引出到顶层和底层的存储芯片1上，再通过加工在顶层和底层存储芯片1的供电布线层2引出到了存储芯片1的边缘。需要说明的是，在键合过程中，存储芯片1水平放置。
参考图9，对存储模块100进行第一模塑工艺，以形成环绕存储模块100的第一密封层81，第一密封层81还露出存储芯片1和第一布线层21远离基板9的表面；第一模塑工艺后，在存储芯片1的远离基板9的表面形成第二布线层22。
示例地，将存储模块100旋转90°，以使每个存储芯片1垂直于逻辑芯片3，通过DAF膜固定存储芯片1和逻辑芯片3；通过第一模塑工艺将多个存储模块100重构，形成重构晶圆；通过重布线工艺在重构晶圆顶面沉积第二布线层22以作为焊盘。
参考图2，提供基板9，基板9具有供电端口92；将存储模块100固定在基板9上，且第一方向X平行于基板9的上表面。提供引线74和引线框架7，将引线74与第二布线层22相连；将引线框架7与引线74和供电端口92相连。
具体地，对重构晶圆划片，以形成内存芯粒，每个内存芯粒包括一个存储模块100和一个逻辑芯片3。将内存芯粒通过倒装焊接的方式焊在已预先焊接好引线框架7的基板9上，将供电布线20通过引线74分别连接到相 应的框架条70上，实现存储芯片1和基板9之间供电信号的连接。此后，通过第二模塑工艺形成覆盖存储模块100、引线74、引线框架7等结构的第二密封层82。
值得注意的是，先后采用两次模塑工艺的原因在于：第一次模塑工艺可以将多个存储模块100连接在一起，因此，后续可以在多个存储模块100上同时形成第二布线层22，从而有利于减少工艺步骤。此外，单个存储模块100的体积较小，多个存储模块100连接在一起后的总体积变大，稳定性更高，不易发生倾倒。此外，第一模塑工艺所形成的第一密封层81能够在后续形成第二布线层22以及倒装焊接等步骤中对存储模块100起到保护和固定作用，避免存储模块100发生坍塌或受到损伤，从而有利于保证存储模块100的性能。此外，先后两次模塑工艺能够提高密封的效果。基板9的底面可以具有焊球91，从而将基板9焊接在外围的电路板上。
综上所述，多层存储芯片1和逻辑芯片3之间通过垂直堆叠的方式形成内存芯粒，再通过引线框架7将供电布线层2引出到基板9上进行封装。存储芯片1和逻辑芯片3之间的信号通讯通过无线实现，可以有效解决平行堆叠中随着存储芯片1堆叠层数增多给通讯带来的困难。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (17)

  1. 一种半导体结构，包括：
    基板，所述基板具有供电端口；
    存储模块，位于所述基板上；所述存储模块包括沿第一方向堆叠的多个存储芯片，所述第一方向平行于所述基板的上表面；
    每个所述存储芯片内具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；
    所述供电布线层包括相连的第一布线层和第二布线层，所述第一布线层所在的平面垂直于所述基板的上表面；所述第二布线层位于所述存储芯片远离所述基板的表面；
    引线，与所述第二布线层相连；
    引线框架，与所述引线和所述供电端口相连。
  2. 根据权利要求1所述的半导体结构，其中，所述引线框架与所述存储模块在所述第一方向上排列。
  3. 根据权利要求2所述的半导体结构，其中，所述存储模块最外两侧的所述存储芯片中的至少一者具有所述供电布线层；
    所述存储芯片内具有导电通孔，所述导电通孔与所述供电信号线电连接；相邻所述存储芯片之间具有键合部，所述键合部与所述导电通孔相连；
    多个所述存储芯片的所述供电信号线通过所述导电通孔和所述键合部电连接。
  4. 根据权利要求3所述的半导体结构，其中，所述存储模块最外两侧的所述存储芯片具有所述供电布线层；
    所述引线框架为两组，且两组所述引线框架分别靠近最外两侧的所述存储芯片，并分别与两个所述供电布线层相连。
  5. 根据权利要求4所述的半导体结构，其中，
    每个所述存储芯片具有第一供电信号线组和第二供电信号线组，所述第一供电信号线组和所述第二供电信号线组均包括多个所述供电信号线；
    所有所述第一供电信号线组与一所述供电布线层电连接；所有所述 第二供电信号线组与另一所述供电布线层电连接。
  6. 根据权利要求4所述的半导体结构，其中，
    所述存储模块包括在所述第一方向排布的两个芯片组，所述芯片组均包括多个所述存储芯片；
    同一所述芯片组的所述供电信号线与其距离最近的所述供电布线层电连接。
  7. 根据权利要求1所述的半导体结构，其中，所述引线框架包括多个间隔设置的框架条，所述框架条为电源框架条或接地框架条；所述电源框架条与所述接地框架条在第二方向上交替排列，所述第二方向平行于所述基板的上表面，且垂直于所述第一方向；
    所述供电布线层包括多个电源布线和多个接地布线；所述供电信号线包括电源信号线和接地信号线；
    所述电源布线与所述电源框架条和所述电源信号线电连接；所述接地布线与所述接地框架条和所述接地信号线电连接。
  8. 根据权利要求1所述的半导体结构，其中，
    所述引线框架包括相连的支撑架和主体架；
    所述支撑架焊接在所述基板的上表面；
    所述主体架在垂直于所述基板上表面的方向上延伸；
    所述支撑架在所述第一方向上的宽度大于所述主体架在所述第一方向的宽度。
  9. 根据权利要求8所述的半导体结构，其中，
    所述引线框架还包括焊接架，所述焊接架在所述第一方向上的宽度大于所述主体架在所述第一方向上的宽度；
    所述焊接架与所述引线焊接；
    所述主体架远离所述支撑架的一端与所述焊接架相连。
  10. 根据权利要求8所述的半导体结构，其中，所述主体架在所述基板上表面的正投影位于所述支撑架在所述基板上表面的正投影内的中心位置。
  11. 根据权利要求9所述的半导体结构，其中，
    还包括：第一密封层，所述第一密封层环绕所述存储模块，并露出 所述存储模块远离所述基板的表面；
    所述第一密封层与所述焊接架相接触。
  12. 根据权利要求11所述的半导体结构，其中，所述第一密封层远离所述基板的一侧具有凹槽，所述焊接架卡合在所述凹槽内。
  13. 根据权利要求1所述的半导体结构，其中，还包括：逻辑芯片，位于所述基板的上表面与所述存储模块之间；
    所述逻辑芯片内具有第一无线通信部；
    所述存储芯片内具有第二无线通信部；
    所述第二无线通信部与所述第一无线通信部进行无线通信。
  14. 根据权利要求13所述的半导体结构，其中，所述存储模块与所述逻辑芯片之间还具有粘结层或焊接层。
  15. 根据权利要求1所述的半导体结构，其中，所述第二布线层在所述第一方向上的宽度与所述存储芯片在所述第一方向上的宽度之比为0.8～2。
  16. 一种半导体结构的制造方法，包括：
    提供基板，所述基板具有供电端口；
    提供存储模块；所述存储模块包括沿第一方向堆叠的多个存储芯片；
    每个所述存储芯片内具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层包括相连的第一布线层和第二布线层，所述第一布线层所在的平面垂直于所述基板的上表面；所述第二布线层位于所述存储芯片远离所述基板的表面；
    将所述存储模块固定在所述基板上，且所述第一方向平行于所述基板的上表面；
    提供引线和引线框架，将所述引线与所述第二布线层相连；将所述引线框架与所述引线和所述供电端口相连。
  17. 根据权利要求16所述的半导体结构的制造方法，其中，包括：
    提供所述存储模块，包括：
    提供多个所述存储芯片；
    在多个所述存储芯片中的至少一者上形成第一布线层；
    形成所述第一布线层后，将多个所述存储芯片堆叠且键合；
    将所述存储模块固定在所述基板上之前，还包括：
    对所述存储模块进行第一模塑工艺，以形成环绕所述存储模块的第一密封层，所述第一密封层还露出所述存储芯片和所述第一布线层远离所述基板的表面；
    所述第一模塑工艺后，在所述存储芯片的远离所述基板的表面形成所述第二布线层。
PCT/CN2022/117375 2022-08-10 2022-09-06 半导体结构和半导体结构的制造方法 WO2024031767A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490195B1 (en) * 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9728524B1 (en) * 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US20180012864A1 (en) * 2016-07-11 2018-01-11 International Business Machines Corporation Dense Assembly of Laterally Soldered, Overmolded Chip Packages
CN112908945A (zh) * 2021-01-12 2021-06-04 江苏晶凯半导体技术有限公司 一种封装组件、电子设备及封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490195B1 (en) * 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9728524B1 (en) * 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US20180012864A1 (en) * 2016-07-11 2018-01-11 International Business Machines Corporation Dense Assembly of Laterally Soldered, Overmolded Chip Packages
CN112908945A (zh) * 2021-01-12 2021-06-04 江苏晶凯半导体技术有限公司 一种封装组件、电子设备及封装方法

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