WO2024031768A1 - 半导体结构和半导体结构的制造方法 - Google Patents

半导体结构和半导体结构的制造方法 Download PDF

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Publication number
WO2024031768A1
WO2024031768A1 PCT/CN2022/117380 CN2022117380W WO2024031768A1 WO 2024031768 A1 WO2024031768 A1 WO 2024031768A1 CN 2022117380 W CN2022117380 W CN 2022117380W WO 2024031768 A1 WO2024031768 A1 WO 2024031768A1
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Prior art keywords
power supply
frame
semiconductor structure
wiring layer
bump
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PCT/CN2022/117380
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English (en)
French (fr)
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吕开敏
庄凌艺
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长鑫存储技术有限公司
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Priority to EP22924568.3A priority Critical patent/EP4350767A4/en
Priority to US18/153,334 priority patent/US20240055325A1/en
Publication of WO2024031768A1 publication Critical patent/WO2024031768A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body

Definitions

  • the present disclosure belongs to the field of semiconductors, and specifically relates to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • HBM High Bandwidth Memory
  • Memory chip stacking technology represented by HBM extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thus greatly increasing the density of memory chips and achieving large capacity and high performance. bandwidth.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a power supply port; a memory module located on the upper surface of the substrate; the memory module includes A plurality of memory chips stacked in a first direction, the first direction being parallel to the upper surface of the substrate; each of the memory chips having a power supply signal line, and at least one of the plurality of memory chips having a power supply signal line.
  • a wiring layer, the power supply signal line is electrically connected to the power supply wiring layer;
  • the power supply wiring layer is located in the memory module, and the end surface of the power supply wiring layer away from the substrate is exposed by the memory module;
  • the end face also has welding bumps;
  • a lead frame is connected to the welding bumps; the lead frame is also electrically connected to the power supply port.
  • embodiments of the present disclosure provide a manufacturing method of a semiconductor structure.
  • the manufacturing method includes: providing a substrate having a power supply port; providing a memory module; the memory module includes: A plurality of stacked memory chips; each memory chip has a power supply signal line, at least one of the plurality of memory chips has a power supply wiring layer, and the power supply signal line is electrically connected to the power supply wiring layer;
  • the power supply wiring layer is located in the memory module, and the end surface of the power supply wiring layer away from the substrate is exposed by the memory module; the end surface also has welding bumps;
  • the memory module is fixed on the substrate, And the first direction is parallel to the upper surface of the substrate; a lead frame is provided; the lead frame is connected to the soldering bump, and the lead frame is electrically connected to the power supply port.
  • the technical solution provided by the embodiments of the present disclosure has at least the following advantages: the stacking direction of multiple memory chips is parallel to the substrate. Therefore, the communication distance of multiple memory chips is the same, which facilitates unified communication delay and improves the operation rate.
  • the power supply wiring layer in the memory chip can lead the power supply signal line out of the memory chip to achieve wired power supply. Wired power supply has high stability and reliability.
  • solder bumps are connected to the lead frame, thereby increasing the strength of the structure.
  • Figure 1 shows a schematic diagram of a semiconductor structure
  • Figure 7 shows a schematic diagram of the active surface of a memory chip provided by an embodiment of the present disclosure
  • FIGS. 10-11 show structural schematic diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • HBM adopts a parallel stacking method, that is, the front surfaces of multiple memory chips 200 are parallel to the upper surface of the substrate 300 .
  • the arrangement direction of the multiple memory chips 200 is perpendicular to the upper surface of the substrate 300 .
  • the communication distance between the uppermost memory chip 200 and the lowermost memory chip 200 and the logic chip 400 is greatly different, resulting in a large communication delay difference between different memory chips 200 and the logic chip 400.
  • how the semiconductor structure is powered can also affect its performance.
  • Embodiments of the present disclosure provide a semiconductor structure, in which multiple memory chips are stacked in a direction parallel to the upper surface of the substrate, that is, the arrangement direction of the multiple memory chips is parallel to the upper surface of the substrate. Therefore, the communication distance of multiple memory chips is the same, which is beneficial to unifying communication delays and improving operating speed.
  • the power supply wiring layer can change the layout of the power supply signal lines and lead the power supply signal lines out of the memory module. That is, the reliability of the power supply can be improved through wired power supply.
  • the welding bumps make the connection between the lead frame and the memory module stronger, and the lead frame can regulate the layout of the power supply path to ensure the stability of the power supply.
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a substrate 9 having a power supply port 92; a memory module 100 located on the upper surface of the substrate 9; the memory module 100 is included in A plurality of memory chips 1 stacked in a first direction X, the first direction 2.
  • the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 is located in the memory module 100, and the end face 14 of the power supply wiring layer 2 away from the substrate 9 is exposed by the memory module 100; the end face 14 also has a welding bump 8, And connected to the soldering bump 8; the lead frame 7 is connected to the soldering bump 8; the lead frame 7 is also electrically connected to the power supply port 92.
  • the power supply wiring layer 2 can lead out the power supply signal line 12 to facilitate wired power supply to the memory chip 1, thereby improving power supply stability.
  • the surface of the memory chip 1 includes an opposite front and a back, and a side connected between them. The area of the front and the back is larger than the area of the side.
  • the plane where the power supply wiring layer 21 is located is perpendicular to the upper surface of the substrate 9 . In other words, the power supply wiring layer 21 can be located on the front or back of the memory chip 1 for connecting the power supply signal line 12 .
  • the soldering bump 1 can not only electrically connect the power supply wiring layer 2 and the lead frame 2, but also play a role in fixing the lead frame 2, thereby improving the structural strength.
  • the lead frame 7 has high strength and is not prone to deformation, thereby regulating the direction of the wired power supply path.
  • multiple memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the multiple memory chips 1 is parallel to the substrate 9 . Therefore, the side surface of the memory chip 1 faces the substrate 9. Since the area of the side surface of the memory chip 1 is smaller, it occupies a smaller area on the upper surface of the substrate 9, which is beneficial to increasing the number of stacked memory chips 1.
  • the semiconductor structure has a first direction X, a second direction Y, and a third direction Z.
  • the first direction X is the stacking direction of the memory chip 1;
  • the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the substrate 9;
  • the surface of the memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together through molecular force or other forces.
  • the surface of the memory chip 1 may also have bonding portions 42. Under temperature rising conditions, adjacent bonding portions 42 are bonded and connected together. That is to say, the dielectric layer 43 is made of insulating material and can play an isolation role; the bonding portion 42 is made of conductive material and can play an electrical connection role.
  • the dielectric layer 43 also exposes the end surface 4 of the power supply wiring layer 2 facing away from the substrate 9 and covers the surface of the power supply wiring layer 2 except the end surface 4 .
  • the memory chip 1 may be a chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory).
  • adjacent memory chips 1 can be stacked front to back, which facilitates the unification of the bonding steps of the memory chips 1 and makes the production process simpler.
  • the stacking manner of adjacent memory chips 1 may also include front-to-front, or back-to-back.
  • the front surface of the memory chip 1 can also be understood as the active surface 13
  • the back surface of the memory chip 1 can be understood as the non-active surface opposite to the active surface 13 .
  • the power supply wiring layer 2 and the power supply signal line 12 will be described in detail below.
  • the power supply wiring layer 2 may be located on the front side of the memory chip 1 , that is, extending along the active surface 13 of the memory chip 1 . Therefore, after the components in the memory chip 1 are manufactured, the original back-end process can be used to manufacture the power supply wiring layer 2, making the process simpler. In addition, the power supply wiring layer 2 can only extend at the edge of the side close to the active surface 13 of the memory chip 1 without covering the entire active surface 13 of the memory chip 1 . Therefore, the connection between the power supply wiring layer 2 and the memory chip 1 The contact area is small, which reduces the impact of heat generated by the power supply wiring layer 2 on the memory chip 1 .
  • FIG. 7 is a schematic diagram of the active surface 13 of the memory chip 1.
  • Each memory chip 1 has a plurality of power supply signal lines 12.
  • the power supply signal lines 12 extend from the memory chip 1 to the active surface 13, so as to Used to connect power supply wiring layer 2.
  • Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to components in the memory chip 1 .
  • the power supply signal line 12 may be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.
  • Each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals.
  • One power supply wiring 20 is electrically connected to a power supply signal line 12.
  • Different power supply signal lines 12 have different voltage signals.
  • different power supply wirings 20 have different voltage signals. voltage signal.
  • the power supply wiring layer 2 includes a ground wiring 20G and a power wiring 20P.
  • the ground wiring 20G is electrically connected to the ground signal line 12G
  • the power wiring 20P is electrically connected to the power signal line 12P.
  • each memory chip has a power supply wiring layer 2 , and the power supply wiring layer 2 in each memory chip 1 is connected correspondingly to the power supply signal line 12 . That is, the power supply signal lines 12 of different memory chips 1 are independent of each other and do not need to be electrically connected through the conductive vias 41 and the bonding portion 42; the power supply signal lines 12 in each memory chip 1 can be connected through the power supply wiring of the memory chip 1 itself.
  • the power supply wiring layer 2 is led out without borrowing the power supply wiring layer 2 of other memory chips 1. Since the power supply signal line 12 of each memory chip 1 can be drawn out individually, it is beneficial to improve the stability of the power supply.
  • the preparation step of the conductive via 41 (refer to FIG. 3 ) can also be omitted, thereby reducing production costs.
  • the bonding portion 42 does not need to be provided between adjacent memory chips 1 .
  • FIG. 8 is a top view of the semiconductor structure shown in FIGS. 2 and 4 to 6 .
  • the lead frame 7 and the soldering bumps 8 are shown in FIG. 8 .
  • each memory chip 1 since each memory chip 1 has a power supply wiring layer 2 , correspondingly, each memory chip 1 also has soldering bumps 8 . That is, the number of welding bumps 8 is larger, thereby enhancing the connection strength between the lead frame 7 and the memory module 100, thereby improving the stability of the structure.
  • the number of power supply wiring layers 2 may also be less than the number of memory chips 1 .
  • the conductive through hole 41 is connected to the power supply signal line 12; there is a bonding portion 42 between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive hole in the adjacent memory chip 1.
  • Via 41 connection That is to say, the power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive vias 41 and the bonding portions 42 .
  • the power supply signal lines 12 with the same voltage signal in two adjacent memory chips 1 are electrically connected. In this way, one of the two memory chips 1 only needs to have the power supply wiring layer 2 .
  • multiple memory chips 1 can share one power supply wiring layer 2 . If a memory chip 1 has its own power supply wiring layer 2, the power supply signal line 12 of the memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, it can be led out through its own power supply wiring layer 2. If a memory chip 1 does not have a power supply wiring layer 2, the memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby passing through the power supply wiring layer 2 of other memory chips 1 Lead out the power supply signal line 12.
  • FIG. 9 is a top view of the semiconductor structure shown in FIG. 3 .
  • FIG. 9 only shows the lead frame 7 and the soldering bumps 8 .
  • the number of power supply wiring layers 2 is smaller, and accordingly, the number of soldering bumps 8 is smaller, thereby increasing the number of adjacent soldering bumps 8 . spacing to avoid incorrect electrical connections between adjacent solder bumps 8.
  • the lead frame 7 will be described in detail below.
  • the lead frame 7 includes a plurality of spaced frame bars 70 , and the plurality of frame bars 70 are arranged in the second direction Y; the second direction Y is perpendicular to the first direction X and parallel to the substrate 9
  • the upper surface of the power supply wiring layer 2 includes a plurality of power supply wirings 20, and different power supply wirings 20 have different voltages; different frame bars 70 are connected to the power supply wirings 20 with different voltages.
  • the soldering bumps 8 with the same voltage signal may be aligned in the first direction X, that is, the power supply wiring 20 with the same voltage signal in the plurality of power supply wiring layers 2 are facing each other in the first direction X. Therefore, the orthographic projection of the frame bar 70 on the substrate 9 can be linear, which facilitates the alignment of the frame bar 70 with the welding bumps 8 , simplifies the welding process, and saves the material of the frame bar 70 .
  • the frame bar 70 includes a ground frame bar 70G and a power frame bar 70P.
  • the ground frame bar 70G is electrically connected to the ground wiring 20G
  • the power frame bar 70P is electrically connected to the power wiring 20P.
  • the ground frame bars 70G and the power frame bars 70P are alternately arranged in the second direction Y. Accordingly, the ground wiring 20G and the power wiring 20P are alternately arranged in the second direction Y. In this way, it is beneficial to reduce electromagnetic interference between adjacent power supply wirings 20 and adjacent frame bars 70 .
  • multiple frame bars 70 are arranged at equal intervals, which is beneficial to improving structural uniformity and avoiding incorrect electrical connections caused by adjacent frame bars 70 being too close.
  • the lead frame 7 includes a connected support frame 71 and a welding frame 72; the support frame 71 extends in a direction perpendicular to the upper surface of the substrate 9; the welding frame 72 extends in a direction parallel to the upper surface of the substrate 9, and Welded to solder bump 8. That is to say, the welding bumps 8 can fix the welding frame 72 above the memory module 100, so that the memory module 100 can support the lead frame 7 to improve the stability of the structure.
  • the supporting frames 71 are respectively located on opposite sides of the storage module 100 and are respectively connected to the opposite ends of the welding frame 72 .
  • Multiple support frames 71 are helpful to improve the stability of the lead frame 7, thereby improving the reliability of power supply.
  • the lead frame 7 may also have a support frame 71 , thereby saving material.
  • the lead frame 7 may also have a groove 7a, and the welding bumps 8 are directly opposite to the groove 7a and welded. That is, the groove 7a is located in the welding frame 72. It should be noted that the top surface of the soldering bump 8 also has a solder layer 83 to connect the soldering bump 8 and the lead frame 7 .
  • the groove 7a can accommodate more solder to improve the soldering strength and reduce the contact resistance between the soldering bump 8 and the lead frame 7 .
  • the width of the welding frame 72 in the second direction Y may be greater than the width of the welding bump 8 in the second direction Y, and the opening area of the groove 7a is greater than the top surface area of the welding bump 8 . In this way, the capacity of the solder is larger, and the soldering firmness is higher; in addition, the larger opening facilitates the alignment of the soldering bump 8 and the groove 7a. In other embodiments, the width of the soldering frame 72 in the second direction Y may also be less than or equal to the width of the soldering bump 8 .
  • each frame bar 70 has a plurality of grooves 7 a , and the plurality of grooves 7 a correspond to the plurality of welding bumps 8 one-to-one. Therefore, the groove 7a can guide the flow direction of the solder during the welding process, that is, guide the solder to flow into the groove 7a to avoid electrical connection between adjacent soldering bumps 8.
  • each frame bar 70 has a groove 7a, one groove 7a corresponds to a plurality of welding bumps 8, and the groove 7a extends in the first direction X. In this way, the production process is simpler.
  • the groove 7a may penetrate the lead frame 7 so that the groove 7a accommodates more solder.
  • the bottom surface of the groove 7a can be located within the lead frame 7, that is, it does not penetrate the lead frame 7. In this way, the bottom surface of the groove 7a can also be in contact with the solder, thereby increasing the contact area and reducing the contact resistance. .
  • the lead frame 7 also includes an extension frame 73, which is connected to the side of the support frame 71 away from the welding frame 72; the cross-sectional area of the extension frame 73 is larger than the cross-sectional area of the support frame 71, and the extension frame 73 and The cross-sections of the support frame 71 are parallel to the upper surface of the substrate 9 ; the semiconductor structure also includes: leads 74 connected between the extension frame 73 and the power supply port 92 .
  • the extension frame 73 extends in a direction parallel to the upper surface of the substrate 9, and the extension frame 73 is beneficial to increasing the welding area of the lead 74 and the lead frame 7 to facilitate welding.
  • the lead wires 74 can improve the flexibility of connecting the lead frame 7 to the power supply port 92 .
  • the front and rear ends of the extension frame 73 , the support frame 71 and the welding frame 72 are connected in sequence, that is, a strip of conductive material is bent into multiple sections to serve as the extension frame 73 , the support frame 71 and the welding frame respectively.
  • Frame 72, the production process is simpler.
  • the semiconductor structure further includes: a power supply line 75 connected to the side of the support frame 71 away from the welding frame 72 ; the substrate 9 also has a first through hole 93 .
  • the hole 93 serves as the power supply port 92; the power supply line 75 is provided in the first through hole 93.
  • the connection method between the lead frame 7 and the power supply port 92 is simpler; in addition, since the sides of the power supply line 75 are surrounded by the first through holes 93, the contact area between the two is larger and the contact resistance is smaller.
  • the cross-sectional area of the power supply line 75 is smaller than the cross-sectional area of the support frame 71 , and the cross-sections of the power supply line 75 and the support frame 71 are parallel to the upper surface of the substrate 9 .
  • the cross-sectional area of the support frame 71 is large, it is beneficial to improve the structural strength of the lead frame 7; when the cross-sectional area of the power supply wire 75 is small, it is beneficial to reduce the volume occupied by the power supply wire 75 in the substrate 9, thereby avoiding crowding.
  • each frame bar 70 may include a welding frame 72 , a support frame 71 , or an extension frame 73 .
  • the welding bump 8 includes a stacked first bump 81 and a second bump 82; the first bump 81 is connected to the power supply wiring layer 2; the second bump 82 is welded to the lead frame 7 ; The cross-sectional area of the first bump 81 is larger than the cross-sectional area of the second bump 82, and the cross-sections of the first bump 81 and the second bump 82 are both parallel to the upper surface of the substrate 9.
  • the larger cross-sectional area of the first bump 81 is beneficial to increasing the contact area between the soldering bump 8 and the power supply wiring layer 2 to reduce contact resistance.
  • the smaller cross-sectional area of the second bump 82 is conducive to increasing the distance between adjacent soldering bumps 8 to avoid erroneous electrical connections between adjacent soldering bumps 8 .
  • the ratio of the width of the first bump 81 to the width of the memory chip 1 is 0.8 ⁇ 1.2.
  • the widths of the two are kept within the above range, it is helpful to ensure that the soldering bumps 8 and the power supply wiring layer 2 have a relatively sufficient contact area, and to ensure that the adjacent soldering bumps 8 have an appropriate distance to avoid adjacent soldering bumps. 8 An incorrect electrical connection has occurred.
  • the semiconductor structure further includes: a first sealing layer 51 surrounding the memory module 100 and exposing the surface of the memory module 100 away from the substrate 9 .
  • the first sealing layer 51 can protect the memory module 100 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed.
  • the semiconductor structure further includes: a second sealing layer 52 , which may cover the memory module 100 , the lead frame 7 , the soldering bumps 8 and the first sealing layer 51 .
  • the second sealing layer 52 can fix the soldering bumps 8 and the lead frame 7 to ensure structural strength. That is, the second sealing layer 52 can improve the protection and isolation effect to ensure the performance of the semiconductor structure.
  • first sealing layer 51 and the second sealing layer 52 may be made of the same material.
  • first sealing layer 51 and the second sealing layer 52 may be epoxy resin.
  • the materials of the first sealing layer 51 and the second sealing layer 52 may be different.
  • the second sealing layer 52 has a higher thermal conductivity than the first sealing layer 51 .
  • the lead frame 7 The heat introduced into the second sealing layer 52 can be transferred to the external environment faster, thereby reducing the adverse effects of the high temperature environment on the memory module 100 .
  • the semiconductor structure also includes: a logic chip 3, located between the substrate 9 and the memory module 100.
  • the logic chip 3 has a first wireless communication part 31; the memory chip 1 has a second wireless communication part 11, and the second The wireless communication unit 11 performs wireless communication with the first wireless communication unit 31 .
  • the second wireless communication part 11 is located on the side of the memory chip 1 facing the logic chip 3 . As a result, the distance between the first wireless communication unit 31 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.
  • the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delays of the memory chips 1 and the logic chip 3 of different layers will be greatly different; in addition, as the number of layers increases, the The number of through-silicon vias (TSV, Through-Silicon Vias) used for communication will increase proportionally, thus sacrificing wafer area.
  • TSV through-silicon vias
  • the stacking direction and communication method of the memory chip 1 are changed, which is beneficial to improving communication quality and saving wafer area.
  • the side of the memory chip 1 is arranged toward the logic chip 3, and the area of the side is smaller; and using wireless communication, there is no need to set up a wired communication unit between the memory chip 1 and the logic chip 3, so that Reducing the process difficulty can also provide sufficient space for the connection structure between the memory chip 1 and the logic chip 3 to improve the structural strength of the two.
  • the lower side of the storage module 100 is used for wireless communication, and the upper side of the storage module 100 is used to lay out the wired power supply path, thereby reducing the electromagnetic interference caused by the current in the wired power supply path to the coil in the wireless communication unit and avoiding signals. loss.
  • the adhesive layer 6 there is an adhesive layer 6 between the memory module 100 and the logic chip 3 . That is, the memory module 100 and the logic chip 3 are connected together through adhesive means to form a memory core.
  • the adhesive layer 6 may be a die attach film (DAF).
  • DAF die attach film
  • the adhesive layer 6 can also be doped with metal ions to improve the heat dissipation effect of the memory module 100 and the logic chip 3 .
  • drawing the power supply signal line 12 from the top of the memory module 100 can leave sufficient space below the memory module 100 to connect the logic chip 3, thereby improving the structural strength.
  • solder pads 84 and solder paste layers 85 between the logic chip 3 and the substrate 9 that is, the logic chip 3 is soldered to the substrate 9 through flip-chip soldering.
  • the substrate 9 can provide power supply and signal exchange to the logic chip 3 through a wired method, and the wired method has high reliability.
  • the bottom of the substrate 9 also has solder balls 91 so that the semiconductor structure can be connected to peripheral devices.
  • connection method of welding bumps 8 is used on the upper side of the memory module 100, so that the connection stability between the lead frame 7 and the memory module 100 is higher.
  • connection method of lead wires 74 or power supply wires 75 is used on the lower side of the memory module 100, which has a simple structure and higher flexibility. The two connection methods work together to make the wired power supply path both flexible and stable.
  • another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • This manufacturing method can manufacture the semiconductor structure provided in the previous embodiment.
  • this semiconductor structure please refer to the foregoing embodiments.
  • a memory module 100 is provided; the memory module 100 includes a plurality of memory chips 1 stacked in a first direction X; each memory chip 1 has a power supply signal line 12, and at least one of the plurality of memory chips 1
  • the power supply wiring layer 2 has a power supply wiring layer 2, the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 is located in the memory module 100, and the end surface 14 of the power supply wiring layer 2 away from the substrate 9 is exposed by the memory module 100; the end surface 14 also has Solder bumps 8.
  • a plurality of memory chips 1 are provided; a power supply wiring layer 2 is formed on at least one of the plurality of memory chips 1 .
  • the plurality of memory chips 1 are stacked.
  • the power supply signal lines 12 of each layer of memory chips 1 are led out to the edge of the memory chip 1 through the power supply wiring layer 2, and the multi-layer memory chips 1 are stacked using hybrid bonding. It should be noted that during the bonding process, the memory chip 1 is placed horizontally.
  • the memory module 100 is rotated 90° so that each memory chip 1 is perpendicular to the logic chip 3, and the memory chip 1 and the logic chip 3 are fixed through the DAF film; the multiple memory modules 100 are reassembled through the first molding process. structure to form a reconstructed wafer; the first bump 81 is processed on the top surface of the reconstructed wafer through a rewiring process; thereafter, a second bump 82 is formed on the first bump 81, and the first bump 81 and the second bump 82 are formed on the first bump 81.
  • the bumps 82 constitute the solder bumps 8 , and a solder layer 83 is formed on the solder bumps 8 .
  • the reconstructed wafer is diced to form memory chips, each of which includes a memory module 100 and a logic chip 3 .
  • a substrate 9 is provided, and the substrate 9 has a power supply port 92; the memory module 100 is fixed on the substrate 9, and the first direction Block 8 is electrically connected to the power supply port 92.
  • the memory core is soldered to the substrate 9 by flip-chip welding, and the lead frame 7 is welded to the soldering bump 8 on the top surface of the memory core. Thereafter, the lead frame 7 is connected to the power supply port 92 through a wire connection method to realize the connection of the power supply signal between the memory chip 1 and the substrate 9 . Thereafter, a second sealing layer 52 covering the memory module 100, the lead frame 7 and other structures is formed through a second molding process.
  • the reason why two molding processes are used in succession is that the first molding process can connect multiple memory modules 100 together. Therefore, the second wiring layer can be formed on multiple memory modules 100 at the same time subsequently. 22, thus helping to reduce process steps.
  • the volume of a single storage module 100 is small. When multiple storage modules 100 are connected together, the total volume becomes larger, the stability is higher, and it is less likely to tip over.
  • the first sealing layer 51 formed by the first molding process can protect and fix the memory module 100 in the subsequent steps of forming the welding bumps 8 and flip-chip welding to prevent the memory module 100 from collapsing or being damaged. , thereby helping to ensure the performance of the storage module 100.
  • two molding processes in succession can improve the sealing effect.
  • the multi-layer memory chip 1 and the logic chip 3 are vertically stacked to form a memory core, and then the power supply wiring layer 2 is led out to the substrate 9 through the lead frame 7 for packaging.
  • the signal communication between the memory chip 1 and the logic chip 3 is implemented wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the memory chip 1 in parallel stacking, and ensure the reliability of power supply.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构和半导体结构的制造方法，半导体结构包括：基板，所述基板具有供电端口；存储模块，位于所述基板的上表面；所述存储模块包括在第一方向上堆叠的多个存储芯片，所述第一方向平行于所述基板的上表面；每个所述存储芯片具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层位于所述存储模块内，且所述供电布线层远离所述基板的端面被所述存储模块露出；所述端面还具有焊接凸块；引线框架，与所述焊接凸块和所述供电端口电连接。本公开实施例至少可以提高半导体结构的性能。

Description

半导体结构和半导体结构的制造方法
交叉引用
本申请引用于2022年8月10日递交的名称为“半导体结构和半导体结构的制造方法”的第202210957799.8号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开属于半导体领域，具体涉及一种半导体结构和半导体结构的制造方法。
背景技术
为提高半导体结构的集成度，可以在同一封装结构内放置一个以上的存储芯片。HBM(High Bandwidth Memory，高带宽内存)是一款新型的内存。以HBM为代表的存储芯片堆叠技术，将原本一维的存储器布局扩展到三维，即将很多个存储芯片堆叠在一起并进行封装，从而大幅度提高了存储芯片的密度，并实现了大容量和高带宽。
然而，随着堆叠层数的增加，HBM的性能有待提升。
发明内容
本公开实施例提供一种半导体结构和半导体结构的制造方法，至少有利于提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，其中，半导体结构包括：基板，所述基板具有供电端口；存储模块，位于所述基板的上表面；所述存储模块包括在第一方向上堆叠的多个存储芯片，所述第一方向平行于所述基板的上表面；每个所述存储芯片具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层位于所述存储模块内，且所述供电布线层远离所述基板的端面被所述存储模块露出；所述端面还具有焊接凸块；引线框架，与所述焊接凸块连接；所述引线框架还与所述供电端口电连接。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，制造方法包括：提供基板，所述基板具有供电端口；提供存储模块；所述存储模块包括在第一方向上堆叠的多个存储芯片；每个所述存储芯片具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层位于所述存储模块内，且所述供电布线层远离所述基板的端面被所述存储模块露出；所述端面还具有焊接凸块；将所述存储模块固定在所述基板上，且所述第一方向平行于所述基板的上表面；提供引线框架；将所述引线框架与所述焊接凸块连接，并将所述引线框架与所述供电端口电连接。
本公开实施例提供的技术方案至少具有以下优点：多个存储芯片的堆叠方向平行于基板，因此，多个存储芯片的通信距离相同，从而利于统一通信延时，且提高运行速率。此外，存储芯片内的供电布线层可以将供电信号线引出至存储芯片外，从而实现有线供电。有线供电的稳定性、可靠性较高。此外，焊接凸块与引线框架相连接，从而提高结构的强度。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种半导体结构的示意图；
图2-图6分别示出了本公开一实施例提供的不同半导体结构的剖面图；
图7示出了本公开一实施例提供的存储芯片的有源面的示意图；
图8-图9分别示出了本公开一实施例提供的不同半导体结构的俯视图；
图10-图11示出了本公开另一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
参考图1，HBM采用平行堆叠方式，即，多个存储芯片200的正面平行于基板300的上表面，换言之，多个存储芯片200的排列方向垂直于基板300的上表面。当堆叠层数较多时，最上层的存储芯片200和最下层的存储芯片200与逻辑芯片400的通信距离相差较大，导致不同的存储芯片200与逻辑芯片400的通信延时相差较大，从而影响产品的运行速率。此外，半导 体结构的供电方式也会影响其性能。
本公开实施例提供一种半导体结构，其中，多个存储芯片在平行于基板上表面的方向上堆叠，即多个存储芯片的排列方向平行于基板的上表面。因此，多个存储芯片的通信距离相同，从而利于统一通信延时，且提高运行速率。此外，供电布线层可以改变供电信号线的布局，并将供电信号线引出至存储模块外，即，通过有线供电的方式能够提高供电的可靠性。此外，焊接凸块使得引线框架与存储模块的连接更为牢固，而引线框架能够规范供电路径的布局，从而保证供电的稳定性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图2-图9所示，本公开一实施例提供一种半导体结构，半导体结构包括：基板9，基板9具有供电端口92；存储模块100，位于基板9的上表面；存储模块100包括在第一方向X上堆叠的多个存储芯片1，第一方向X平行于基板9的上表面；每个存储芯片1具有供电信号线12，多个存储芯片1中的至少一者具有供电布线层2，供电信号线12与供电布线层2电连接；供电布线层2位于存储模块100内，且供电布线层2远离基板9的端面14被存储模块100露出；端面14还具有焊接凸块8，并与焊接凸块8相连；引线框架7，与焊接凸块8连接；引线框架7还与供电端口92电连接。
这样的设计至少包括以下几个方面的效果：
第一，供电布线层2可以引出供电信号线12，以便于为存储芯片1进行有线供电，从而提高供电稳定性。具体地，存储芯片1的表面包括相对的正面和背面，以及连接在二者之间的侧面，正面和背面的面积大于侧面的面积。供电布线层21所在的平面垂直于基板9的上表面，换言之，供电布线层21可以位于存储芯片1的正面或背面，以用于连接供电信号线12。
第二，焊接凸块1不仅能够将供电布线层2与引线框架2电连接，还能够起到固定引线框架2的作用，从而提高结构强度。
第三，引线框架7的强度较高，不易发生变形，从而能够规范有线供电路径的走向。
第四，多个存储芯片1的沿第一方向X堆叠，即多个存储芯片1的排列方向平行于基板9。由此，存储芯片1的侧面朝向基板9，由于存储芯片1的侧面的面积较小，所占据的基板9上表面的面积较小，从而有利于提高存储芯片1的堆叠数量。
以下将结合附图对半导体结构进行详细说明。
首先，需要说明的是，半导体结构内具有第一方向X、第二方向Y和第三方向Z。其中，第一方向X为存储芯片1的堆叠方向；第二方向Y垂直于第一方向X，且平行于基板9的上表面，第三方向Z垂直于基板9的上 表面。
参考图2-图6，多个存储芯片1可以采用混合键合的方式进行堆叠。举例而言，存储芯片1的表面还具有介质层43，相邻存储芯片1的介质层43可以通过分子力等作用力连接在一起。此外，存储芯片1的表面还可以具有键合部42，在升温条件下，相邻键合部42发生键合连接在一起。也就是说，介质层43为绝缘材料，能够起到隔离作用；键合部42为导电材料，能够起到电气连接的作用。此外，介质层43还露出供电布线层2背向基板9的端面4，并覆盖供电布线层2除端面4之外的表面。
存储芯片1可以为DRAM(Dynamic Random Access Memory，动态随机存储器)或SRAM(Static Random-Access Memory，静态随机存储器)等芯片。在一些实施例中，相邻存储芯片1的堆叠方式可以均为正面对背面，从而有利于统一存储芯片1的键合步骤，生产工艺更加简单。在一些实施例中，相邻存储芯片1的堆叠方式还可以包括正面对正面，或背面对背面。存储芯片1的正面也可以理解为有源面13，存储芯片1的背面可以理解为与有源面13相对的非有源面。
以下将对供电布线层2和供电信号线12进行详细说明。
参考图2-图6，供电布线层2可以位于存储芯片1正面，即沿着存储芯片1的有源面13延伸。因此，在存储芯片1内的元件制造完成后，可以利用原有的后段工艺制造供电布线层2，工艺更加简单。另外，供电布线层2可以只在靠近存储芯片1的有源面13的一侧的边缘位置延伸，而无需覆盖整个存储芯片1的有源面13，因此，供电布线层2与存储芯片1的接触面积小，降低供电布线层2的发热对存储芯片1的影响。
参考图7，图7为存储芯片1的有源面13的示意图，每个存储芯片1内均具有多个供电信号线12，供电信号线12从存储芯片1内延伸至有源面13，以用于连接供电布线层2。不同供电信号线12可以为存储芯片1内的元件提供不同的电压信号，比如，数字信号或模拟信号。供电信号线12可以为接地信号线12G或电源信号线12P。不同的接地信号线12G具有不同的电压信号，不同的电源信号线12P具有不同的电压信号。
每个供电布线层2包括多条间隔设置的供电布线20，一供电布线20与一供电信号线12电连接，不同供电信号线12具有不同的电压信号，相应的，不同供电布线20具有不同的电压信号。供电布线层2包括接地布线20G和电源布线20P，接地布线20G与接地信号线12G对应电连接，电源布线20P与电源信号线12P对应电连接。
在一些实施例中，参考图2和图4-图6，每个存储芯片均具有一个供电布线层2，且每个存储芯片1内的供电布线层2与供电信号线12对应连接。即不同存储芯片1的供电信号线12相互独立，而无需通过导电通孔41和键合部42电连接在一起；每个存储芯片1内的供电信号线12可以通过存储芯片1自身的供电布线层2引出，而无需借用其他存储芯片1的供电布线层2引出。由于每个存储芯片1的供电信号线12可以被单独引出，因此， 有利于提高供电的稳定性。此外，还可以省去导电通孔41(参考图3)的制备步骤，从而降低生产成本。另外，由于多个存储芯片相互独立，因此，相邻存储芯片1之间也可以不设置键合部42。
图8为图2、图4-图6所示的半导体结构的俯视图，为了更加直观，图8中仅示出引线框架7和焊接凸块8。参考图8，由于每个存储芯片1具有供电布线层2，相应的，每个存储芯片1也具有焊接凸块8。即焊接凸块8的数量较多，由此，可以增强引线框架7与存储模块100的连接强度，从而提高结构的稳定性。
在另一些实施例中，参考图3，供电布线层2的数量也可以少于存储芯片1的数量。具体地，存储芯片1内具有导电通孔41，导电通孔41与供电信号线12连接；相邻存储芯片1之间具有键合部42，键合部42与相邻存储芯片1内的导电通孔41连接。也就是说，不同存储芯片1中具有相同电压信号的供电信号线12可以通过导电通孔41和键合部42可以被连接在一起。示例地，两个相邻存储芯片1中具有相同电压信号的供电信号线12电连接，如此，两个存储芯片1中的一者具有供电布线层2即可。
换言之，多个存储芯片1可以共用一个供电布线层2。若一个存储芯片1自身具有供电布线层2，则此存储芯片1的供电信号线12可以直接与自身的供电布线层2连接，即，通过自身的供电布线层2引出。若一个存储芯片1自身不具有供电布线层2，此存储芯片1可以通过导电通孔41以及键合部42与其他的存储芯片1建立电连接关系，从而通过其他存储芯片1的供电布线层2引出供电信号线12。
图9为图3所示的半导体结构的俯视图，为了更加直观，图9仅示出引线框架7和焊接凸块8。参考图9，由于多个存储芯片1可以共用一个供电布线层2，因此供电布线层2的数量较少，相应地，焊接凸块8的数量较少，从而增大相邻焊接凸块8的间距，以避免相邻焊接凸块8发生错误的电连接。
以下将对引线框架7进行详细说明。
参考图8-图9，引线框架7包括多个间隔设置的框架条70，且多个框架条70在第二方向Y上排列；第二方向Y垂直于第一方向X，且平行于基板9的上表面；每个供电布线层2包括多条供电布线20，且不同供电布线20具有不同的电压；不同框架条70与具有不同电压的供电布线20相连。
具有相同电压信号的焊接凸块8可以在第一方向X上排成直列，即多个供电布线层2中具有相同电压信号的供电布线20在第一方向X上正对。由此，框架条70在基板9上的正投影可以为直线型，从而便于将框架条70与焊接凸块8对准，简化焊接工艺，并节约框架条70的材料。
继续参考图8-图9，框架条70包括接地框架条70G和电源框架条70P，其中接地框架条70G与接地布线20G电连接，电源框架条70P与电源布线20P电连接。在一些实施例中，接地框架条70G和电源框架条70P在第二方向Y上交替排布。相应地，接地布线20G与电源布线20P在第二方向Y上 交替排布。如此，有利于降低相邻供电布线20以及相邻框架条70之间的电磁干扰。
在一些实施例中，多个框架条70等间距排列，从而有利于提高结构的均一性，并避免相邻框架条70因距离过近而造成错误的电连接。
参考图2-图6，引线框架7包括相连的支撑架71和焊接架72；支撑架71在垂直于基板9上表面的方向延伸；焊接架72在平行于基板9上表面的方向延伸，并与焊接凸块8相焊接。也就是说，焊接凸块8可以将焊接架72固定在存储模块100的上方，从而使得存储模块100能够支撑引线框架7，以提高结构的稳定性。
在一些实施例中，支撑架71至少为两个，所述支撑架71分别位于存储模块100的相对两侧，并分别与焊接架72的相对两端连接。多个支撑架71有利于提高引线框架7的稳定性，从而提高供电的可靠性。在另一些实施例中，引线框架7也可以具有一个支撑架71，从而有利于节省材料。
参考图5-图6，引线框架7内还可以具有凹槽7a，焊接凸块8与凹槽7a正对且焊接。即，凹槽7a位于焊接架72内。需要说明的是，焊接凸块8的顶面还具有焊料层83，以连接焊接凸块8和引线框架7。凹槽7a可以容纳更多的焊料，以提高焊接强度，且降低焊接凸块8与引线框架7的接触电阻。
在一些实施例中，焊接架72在第二方向Y上的宽度可以大于焊接凸块8在第二方向Y上的宽度，且凹槽7a的开口面积大于焊接凸块8的顶面面积。如此，焊料的容量更大，焊接的牢固性更高；此外，较大的开口便于将焊接凸块8与凹槽7a进行对准。在另一些实施例中，焊接架72在第二方向Y上的宽度也可以小于或等于焊接凸块8的宽度。
在一些实施例中，参考图5，每个框架条70具有多个凹槽7a，且多个凹槽7a与多个焊接凸块8一一对应。由此，凹槽7a可以在焊接过程中对焊料的流动方向起到引导作用，即引导焊料朝向凹槽7a内流动，避免相邻焊接凸块8发生电连接。
在另一些实施例中，参考图6，每个框架条70具有一个凹槽7a，一个凹槽7a与多个焊接凸块8相对应，且凹槽7a在第一方向X上延伸。如此，生产工艺更加简单。
此外，在一些实施例中，凹槽7a可以贯穿引线框架7，从而使得凹槽7a容纳更多的焊料。在另一些实施例中，凹槽7a的底面可以位于引线框架7内，即不贯穿引线框架7，如此，凹槽7a的底面也可以与焊料相接触，从而增大接触面积，以降低接触电阻。
参考图2-图3，引线框架7还包括延伸架73，延伸架73与支撑架71远离焊接架72的侧面相连；延伸架73的截面面积大于支撑架71的截面面积，且延伸架73和支撑架71的截面均平行于基板9的上表面；半导体结构还包括：引线74，连接在延伸架73与供电端口92之间。
即，延伸架73在平行于基板9上表面的方向上延伸，延伸架73有利 于增大引线74与引线框架7的焊接面积，以便于进行焊接。此外，引线74可以提高引线框架7与供电端口92连接的灵活性。
在一些实施例中，延伸架73、支撑架71和焊接架72的首尾端部顺次连接，即，将一个条状的导电材料弯折成多段以分别作为延伸架73、支撑架71和焊接架72，生产工艺更简单。
在另一些实施例中，参考图4-图6，半导体结构还包括：供电线75，与支撑架71远离焊接架72的侧面相连；基板9还具有贯穿的第一通孔93，第一通孔93作为供电端口92；供电线75设置在第一通孔93内。如此，引线框架7与供电端口92的连接方式更为简单；此外，由于供电线75的侧面都被第一通孔93所环绕，因此，二者的接触面积较大，接触电阻较小。
供电线75的截面面积小于支撑架71的截面面积，且供电线75和支撑架71的截面均平行于基板9的上表面。在支撑架71的截面面积较大时，有利于提高引线框架7的结构强度；在供电线75的截面面积较小时，有利于减小供电线75在基板9内所占据的体积，从而避免挤占基板9内其他元件的空间位置。
值得说明的是，由于引线框架7包括多个间隔设置的框架条70，因此，可以理解为：每个框架条70均可以包括焊接架72、支撑架71或延伸架73等结构。
参考图2-图6，焊接凸块8包括层叠设置的第一凸块81和第二凸块82；第一凸块81与供电布线层2相连；第二凸块82与引线框架7相焊接；第一凸块81的截面面积大于第二凸块82的截面面积，且第一凸块81和第二凸块82的截面均平行于基板9的上表面。
第一凸块81具有较大的截面面积有利于增大焊接凸块8与供电布线层2之间的接触面积，以降低接触电阻。第二凸块82较小的截面面积有利于增大相邻焊接凸块8之间的距离，以避免相邻焊接凸块8发生错误的电连接。
示例地，在第一方向X上，第一凸块81的宽度与存储芯片1的宽度之比为0.8～1.2。在二者的宽度保持在上述范围时，有利于保证焊接凸块8与供电布线层2具有较充足的接触面积，且保证相邻焊接凸块8具有合适的距离，以避免相邻焊接凸块8发生错误的电连接。
继续参考图2-图6，半导体结构还包括：第一密封层51，第一密封层51环绕存储模块100，并露出存储模块100远离基板9的表面。第一密封层51能够保护存储模块100不受外界环境的影响，比如抵抗外部湿气、溶剂，还能够抵抗半导体结构安装时的热冲击和机械振动。
半导体结构还包括：第二密封层52，第二密封层52可以覆盖存储模块100、引线框架7、焊接凸块8以及第一密封层51。第二密封层52可以对焊接凸块8和引线框架7起到固定作用，以保证结构强度。即第二密封层52能够提高保护和隔离效果，以保证半导体结构的性能。
在一个实施例中，第一密封层51与第二密封层52的材料可以相同， 例如，第一密封层51和第二密封层52可以是环氧类树脂。
在一个实施例中，第一密封层51与第二密封层52的材料可以不相同，例如，第二密封层52的导热率高于第一密封层51，通过这样的设置，通过引线框架7引入到第二密封层52中的热量可以更快的传递到外界环境中，降低高温环境对存储模块100的不良影响。
参考图2-图6，半导体结构还包括：逻辑芯片3，位于基板9与存储模块100之间，逻辑芯片3具有第一无线通信部31；存储芯片1具有第二无线通信部11，第二无线通信部11与第一无线通信部31进行无线通信。
由于多个存储芯片1与逻辑芯片3的距离相同，因此，多个存储芯片1与逻辑芯片3的无线通信的延时保持一致。在一些实施例中，第二无线通信部11位于存储芯片1朝向逻辑芯片3的一侧。由此，可以减小第一无线通信部31与第二无线通信部11之间的距离，从而提升无线通信的质量。
需要说明的是，若多个存储芯片1的排列方向垂直于逻辑芯片3的上表面，则不同层的存储芯片1与逻辑芯片3的通讯延迟相差较大；此外，随着层数增加，用于通讯的硅通孔(TSV，Through-Silicon Vias)的数量会正比例增高，从而牺牲晶圆面积。而本公开实施例中，改变了存储芯片1的堆叠方向和通信方式，从而有利于提高通信质量，还可以节约晶圆面积。
继续参考图2-图6，存储芯片1的侧面朝向逻辑芯片3设置，侧面的面积较小；而采用无线通信的方式则无需在存储芯片1与逻辑芯片3之间设置有线通信部，从而可以降低工艺难度，还可以为存储芯片1与逻辑芯片3之间的连接结构提供充足的空间位置，以提高二者结构强度。此外，存储模块100的下侧用于进行无线通信，存储模块100的上侧用于布局有线供电路径，从而能够降低有线供电路径中的电流对无线通信部中的线圈产生的电磁干扰，避免信号损失。
在一些实施例中，存储模块100与逻辑芯片3之间还具有粘结层6。即，存储模块100和逻辑芯片3通过胶粘的方式连接在一起，从而构成一个内存芯粒。示例地，粘结层6可以为固晶用胶膜(die attach film，DAF)。粘结工艺较为简单，能够节约成本。此外，粘结层6中还可以掺杂有金属离子，以提高存储模块100和逻辑芯片3的散热效果。在另一些实施例中，存储模块100与逻辑芯片3之间可以具有焊接层(图中未示出)，即存储模块100和逻辑芯片3通过焊接的方式连接在一起。
也就是说，从存储模块100的上方引出供电信号线12，能够在存储模块100的下方留下充足的空间位置以连接逻辑芯片3，从而提高结构强度。
继续参考图2-图6，逻辑芯片3与基板9之间还具有焊盘84和焊膏层85，即逻辑芯片3通过倒装焊接的方式焊接在基板9上。如此，基板9可以通有线方式对逻辑芯片3进行供电以及信号交换，有线方式的高可靠性较高。此外，基板9的底部还具有焊球91，从而可以将半导体结构与外围的器件相连。
综上所述，在本公开实施例中，在存储模块100的上侧采用焊接凸块 8的连接方式，使得引线框架7与存储模块100的连接稳定性更高。在存储模块100的下侧采用引线74或供电线75的连接方式，结构简单且灵活性更高。两种连接方式相配合从而使得有线供电路径兼具灵活性和稳定性。
如图10-图11和图2所示，本公开另一实施例提供一种半导体结构的制造方法，此制造方法可以制造前述实施例提供的半导体结构。有关此半导体结构的详细说明可参考前述实施例。
参考图10-图11，提供存储模块100；存储模块100包括在第一方向X上堆叠的多个存储芯片1；每个存储芯片1具有供电信号线12，多个存储芯片1中的至少一者具有供电布线层2，供电信号线12与供电布线层2电连接；供电布线层2位于存储模块100内，且供电布线层2远离基板9的端面14被存储模块100露出；端面14还具有焊接凸块8。
具体地，参考图10，提供多个存储芯片1；在多个存储芯片1中的至少一者上形成供电布线层2，形成供电布线层2后，将多个存储芯片1堆叠设置。示例地，各层存储芯片1的供电信号线12通过供电布线层2引出到了存储芯片1的边缘，采用混合键合的方式将多层存储芯片1进行堆叠。需要说明的是，在键合过程中，存储芯片1水平放置。
参考图11，将存储模块100旋转90°，以使每个存储芯片1垂直于逻辑芯片3，通过DAF膜固定存储芯片1和逻辑芯片3；通过第一模塑工艺将多个存储模块100重构，以形成重构晶圆；通过重布线工艺在重构晶圆顶面加工第一凸块81；此后在第一凸块81上形成第二凸块82，第一凸块81和第二凸块82构成焊接凸块8，并在焊接凸块8上形成焊料层83。此后，对重构晶圆划片，以形成内存芯粒，每个内存芯粒包括一个存储模块100和一个逻辑芯片3。
参考图2，提供基板9，基板9具有供电端口92；将存储模块100固定在基板9上，且第一方向X平行于基板9的上表面；提供引线框架7；将引线框架7与焊接凸块8和供电端口92电连接。
具体地，将内存芯粒通过倒装焊接的方式焊在基板9上，将引线框架7焊接在内存芯粒顶面的焊接凸块8上。此后，通过引线连接的方法将引线框架7与供电端口92相连，实现存储芯片1和基板9之间供电信号的连接。此后，通过第二模塑工艺形成覆盖存储模块100、引线框架7等结构的第二密封层52。
值得注意的是，先后采用两次模塑工艺的原因在于：第一次模塑工艺可以将多个存储模块100连接在一起，因此，后续可以在多个存储模块100上同时形成第二布线层22，从而有利于减少工艺步骤。此外，单个存储模块100的体积较小，多个存储模块100连接在一起后的总体积变大，稳定性更高，不易发生倾倒。此外，第一模塑工艺所形成的第一密封层51能够在后续形成焊接凸块8以及倒装焊接等步骤中对存储模块100起到保护和固定作用，避免存储模块100发生坍塌或受到损伤，从而有利于保证存储模块100的性能。此外，先后两次模塑工艺能够提高密封的效果。
综上所述，多层存储芯片1和逻辑芯片3之间通过垂直堆叠的方式形成内存芯粒，再通过引线框架7将供电布线层2引出到基板9上进行封装。存储芯片1和逻辑芯片3之间的信号通讯通过无线实现，可以有效解决平行堆叠中随着存储芯片1堆叠层数增多给通讯带来的困难，并保证供电的可靠性。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (16)

  1. 一种半导体结构，包括：
    基板，所述基板具有供电端口；
    存储模块，位于所述基板的上表面；所述存储模块包括在第一方向上堆叠的多个存储芯片，所述第一方向平行于所述基板的上表面；
    每个所述存储芯片具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；
    所述供电布线层位于所述存储模块内，且所述供电布线层远离所述基板的端面被所述存储模块露出；所述端面还具有焊接凸块；
    引线框架，与所述焊接凸块和所述供电端口电连接。
  2. 根据权利要求1所述的半导体结构，其中，
    所述引线框架包括相连的支撑架和焊接架；
    所述支撑架在垂直于所述基板上表面的方向延伸；
    所述焊接架在平行于所述基板上表面的方向延伸，并与所述焊接凸块相焊接。
  3. 根据权利要求2所述的半导体结构，其中，所述支撑架至少为两个，且所述支撑架分别位于所述存储模块的相对两侧，并分别与所述焊接架的相对两端连接。
  4. 根据权利要求2所述的半导体结构，其中，所述引线框架还包括：延伸架，与所述支撑架远离所述焊接架的侧面相连；
    所述延伸架的截面面积大于所述支撑架的截面面积，且所述延伸架和所述支撑架的截面均平行于所述基板的上表面；
    还包括：引线，连接在所述延伸架与所述供电端口之间。
  5. 根据权利要求2所述的半导体结构，其中，
    还包括：供电线，分别与所述支撑架远离所述焊接架的侧面相连；
    所述基板还具有贯穿的第一通孔，所述第一通孔作为所述供电端口；所述供电线设置在所述第一通孔内。
  6. 根据权利要求5所述的半导体结构，其中，
    所述供电线的截面面积小于所述支撑架的截面面积，且所述供电线和所述支撑架的截面均平行于所述基板的上表面。
  7. 根据权利要求1所述的半导体结构，其中，所述引线框架内还具有凹槽，所述焊接凸块与所述凹槽正对且焊接。
  8. 根据权利要求7所述的半导体结构，其中，所述凹槽的开口面积大于所述焊接凸块的顶面面积。
  9. 根据权利要求1所述的半导体结构，其中，所述引线框架包括多个间隔设置的框架条，且多个所述框架条在第二方向上排列；所述第二方向垂直于所述第一方向，且平行于所述基板的上表面；
    每个所述供电布线层包括多条供电布线，且不同所述供电布线具有不同的电压；
    不同所述框架条与具有不同电压的所述供电布线相连。
  10. 根据权利要求9所述的半导体结构，其中，所述供电布线包括接地布线和电源布线，所述框架条包括接地框架条和电源框架条，所述接地框架条与所述接地布线电连接，所述电源框架条与所述电源布线电连接，所述接地框架条与所述电源框架条在所述第二方向上交替排列。
  11. 根据权利要求9所述的半导体结构，其中，多个所述框架条等间距排列。
  12. 根据权利要求1所述的半导体结构，其中，
    每个所述存储芯片均具有一个所述供电布线层，且每个所述存储芯片内的所述供电布线层与所述供电信号线对应连接。
  13. 根据权利要求1所述的半导体结构，其中，所述焊接凸块包括层叠设置的第一凸块和第二凸块；所述第一凸块与所述供电布线层相连；所述第二凸块与所述引线框架相焊接；
    所述第一凸块的截面面积大于所述第二凸块的截面面积，且所述第一凸块和所述第二凸块的截面均平行于所述基板的上表面。
  14. 根据权利要求13所述的半导体结构，其中，在所述第一方向上，所述第一凸块的宽度与所述存储芯片的宽度之比为0.8～1.2。
  15. 根据权利要求1所述的半导体结构，其中，还包括：逻辑芯片，位于所述基板与所述存储模块之间，所述逻辑芯片具有第一无线通信部；
    所述存储芯片具有第二无线通信部，所述第二无线通信部与所述第一无线通信部进行无线通信。
  16. 一种半导体结构的制造方法，包括：
    提供基板，所述基板具有供电端口；
    提供存储模块；所述存储模块包括在第一方向上堆叠的多个存储芯片；每个所述存储芯片具有供电信号线，多个所述存储芯片中的至少一者具有供电布线层，所述供电信号线与所述供电布线层电连接；所述供电布线层位于所述存储模块内，且所述供电布线层远离所述基板的端面被所述存储模块露出；所述端面还具有焊接凸块；
    将所述存储模块固定在所述基板上，且所述第一方向平行于所述基板的上表面；
    提供引线框架；将所述引线框架与所述焊接凸块和所述供电端口电连接。
PCT/CN2022/117380 2022-08-10 2022-09-06 半导体结构和半导体结构的制造方法 WO2024031768A1 (zh)

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CN101999167A (zh) * 2008-03-12 2011-03-30 垂直电路公司 支撑安装的电互连管芯组件
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