200424999 九、發明說明： 【發明所辱之技術領域】 本發明係關於-種具備像素電極與對向該像素電極之丑 通電極之顯示裝置。更詳細的是關於—種生成施加於共通 電極之交流共通電壓之電路周圍的改良技術。 【先前技術】 以白知之主動矩陣液晶面板等代表之平坦型之顯示裳 置，大多利用作為電子機器的顯示器零件。主動矩陣型之 顯示面板係因應由電子機器的本體側供給之顯示資料 源電壓作動，一般採取在絕緣 攸上體的積體形成顯示 …驅動該顯示區域之周邊之電路部之所謂系統顯示写 該情形，顯示區域包含電氣光學物質；該電氣光 予胃係保持於配置成矩陣狀之像素電極與對向於像素電 二共通電極兩者之間。一方面，包圍顯示區域之周邊的 ，：係包含驅動器與共通驅動器；該驅動器，係因應顯 :貝：、，寫：信號電壓至像素電極側；該共通驅動器，係 、通龍至共通電極側。具有如此構成之顯示裝置係 揭不於特開2000-193941號公報。 材：：液晶作為電氣光學物質的情形’通常為了防止液晶 化採用著交流驅動。在每特定之週期反轉施加於 =電極側之信號電壓之極性，並且配合此等共通電厂堅也 通電二Γ習知之共通驅動器以特定之週期反轉生成共 動元㈣Γ而’液晶材料與驅動此等之薄膜電晶體等之主 件據有關於極性之非對稱性。從而，若❹號電㈣ 89410.doc 200424999 共通電壓之中心雷办+ 辦望+ θ 位元全一致，則顯露非對稱性糾結與閃 二之：像顧著劣化。在此，習知之顯示裝置加上共通驅 位準之文，者具傷有對信號電壓生成用以調整共通電麼之 關於液晶材料血主：泛::合電谷之㈣電路。為了抵銷 兩，^、 +/、主動疋件的極性之非對稱性，藉設定偏置 私ι σ以防止影像的、纟彳結與閃燦。 在才又入顯示裝晉& φ 耗合電容至特定之：須充電包含於偏昼電路之 … 偏置電堡為止。若完成充電，則由於在 可以二動=輸出之共通電壓加上特定之偏置電壓，所以 二正常的影像。但是，在電源投入後到耦合電容之 心成之過度期’由於共通㈣之位準不安^，所以有 =看見閃燦的情形。為了防止此等，從習知使用著在電 源才又入時用以使耦合雷 電路即…電之啟動電路。該啟動 電料使在電源遮斷時放電輕合電容的情形亦可以使用。 但疋’習知之共通驅動器用啟動器電路（急速充放電電 路），在採取系統顯示構成之顯示裝置外的驅動系統已實 形’存在有零件件數的增加與顯示襄置外部的驅 動糸統規模變大之問題。 【發明内容】 蓉於上述習知之技術課題，本發明以將共通驅動器用之 啟動電路搭載於採取系統顯示構成之顯示裝置内為目的。 為了達成該目的採取以下的手段。亦即，本發明之顯示裝 置，其特徵在於可以使用作為電子機器的顯示器零件，因 應由電子機器的本體側供給之顯示資料及電_作動， 89410.doc 200424999 由在絕緣U ±rz . 之 土板上一體的積體形成顯示區域與驅動顯示區域 ^ 勺電路部之面板所形成；前述顯示區域包含電氣 學物質·七念_ 、’心電氣光學物質係保持於配置成矩陣狀之像素電 柽與對向於像素電極之共通電極兩者之間；前述電路部包 含：驅動哭、 /么 〇 係因應顯示資料’寫入信號電麼至該像素電 才虽你| · 、g ，/、逋驅動器，係施加共通電壓至共通電極侧； 電路，作且供士 有對彳§號電壓生成用以調節共通電壓之位準 定之偏置電壓之耦合電容；以及啟動電路，係當電源 電C上幵日守，將該偏壓電路之耦合電容預充電至偏置電壓 :、 並且§電源電壓下降時，放電該耦合電容。具體而 ^ 4述面板係由該顯示區域及驅動該顯示區域之周邊之 該電路都，a + 並且在共通之絕緣基板上以同一工序形成之薄 膜電曰曰體所構成，前述共通驅動器、偏壓電路及啟動電路 ^ / ^ β電谷之外搭載於該共通之絕緣基板上。較佳的 疋’月以啟動電路僅在電源電壓上昇時及電源電壓下降時 作動’除此之外的時間係形成非作動狀態。 另外’本發明之顯示t置，其特徵在於可以使用作為切 常消耗電力狀態與低消耗電力狀態之電子機器的顯示 “二件因應由電子機器的本體側供給之顯示資料及電源 電I作動，由在絕緣基板上一體的積體形成顯示區域與驅 :顯不區域之周邊的電路部之面板所形成；前述面板因應 私子機②本體側的通常消托電力狀態及低消耗電力狀態之 :換可以切換至動作模式與待機模式；包含待機控制手 段’當為動作模式時，由電子機器的本體側接受電源電壓 89410.doc 200424999 的供給作動，驅動兮鹿― μ ”、、S不區域進行所希望之顯示，當為待 、〜^ 由電子機器的本體側接受電源電壓的供給之 、 7該颂不區域的驅動，並且鈍化電路部抑制面 板的電力消耗；前述顯 疋.、、、員不£域包含電氣光學物質； 光學物質係保持於配署士、&去 、-置成矩陣狀之像素電極與對向於像素 電極之共通電極兩者之間；前述電路部包含：驅動器，係 因應由電子機器的本體- μ你 遐側傳迗之顯不貧料，寫入信號電壓 至该像素電極側；共通驅動器，係施加共 極側；偏壓電踗，筏目m 〃 電路係具備有對信號電壓生成用以調節丘通 電厂堅之位準之料之偏置電屡之麵合電容；以及啟= 路，係由待機模式回復至動作模式時，事先將該偏壓電路 之^合電容預充電至偏置為止，並且由動作模式移動 至待機模式時，放電該耦合電 电谷具體而吕，前述面板係 貝不區域及驅動該顯示區域之周邊之該電路部，並且 之絕緣基板上以同1序形成之薄膜電晶體所構 # Μ述共通驅動H、偏壓電路及啟動電路除了該輕合電 今之外搭载於該共通之絕緣基板上。較佳的是，前述啟動 由待機模式回復至動作模式時及由動作模式移動 + 土模式時作動，除此之外的時間係形成非作動狀能。 若依據本發明，將使施加於顯示裝置的共通電極之二通 電壓之偏置用搞合電容急速的充電至電源投入時所希望之 偏置電位之系統搭載於液晶顯示裝置内。也就是，系統顯 不構成之顯示面板，係由該顯示區域及驅動該顯示區域之 周邊之該電路部，並且在共通之絕緣基板上以同—工序形 89410.doc 成之薄膜電晶體所構成，屬於該 壓電路及啟動電路，除了Μ 敎共通驅動器、偏 I# ^ 〇電各之外以薄膜電晶體等積 體形成於共通之絕緣基板上。 寺積 播、$ Α ^ ’兄’可以使用為可以士 77 換通常之動作模式與待機模式 乂切 u. , ^ ^ 糸、、先顯不。此時，由待拖 杈式回设至動作模式時，同樣 子機 偏私用之耦合電容。為此，啟 莹 置。 路也可以内藏於顯示裳 【實施方式】 參照以下圖面詳細說明本發明之實施形態。圖^關 勒明之顯示裝置之全體構成之塊圖。如圖示，本顯示裝置〇 係積體形成於由玻料㈣叙絕緣基板丨之上。在絕緣基 ㈣中央形成著顯示區域2’為了包圍此等周邊的電路部 也一體的形成著。在矩形的絕緣基板1的上邊形成著連接端 子’透過軟性印刷t_PC)u’形成與電子機器本體側（設 定側)連接。FPCU係形成多數之配線平面的配列之單層構 造之平的電纜。 顯示區域2係形成列狀之閘極線⑴〜如與行狀之信號線 S1〜Sn相互交叉配置之矩陣構成。在各閘極線g與信號線§ 之交叉部形成著像素。在本實施形態，各像素係以液晶元 件LC、補助電容CS及薄膜電晶體TET所構成。液晶元件lc 係以保持於像素電極與對向於此等之共通電極（c〇M)兩者 之間之液晶（電氣光學物質）所構成。TF丁之閘極電極係連接 於閘極線G，源極電極係連接於信號線s，汲極電極係連接 於液晶元件LC的像素電極。補助電容CS係連接於tft之汲 89410.doc -10- 200424999 極電極與補助電容線之間。TFT係以由閘極線〇供給之選擇 脈衝導通，寫，入對應由信號線S供給之信號電壓之液晶元件 LC的像素電極。補助電容CS係在一框或一場之間預先保持 信號電壓。 液晶元件LC 一般作交流驅動。也就是，透過信號線s寫 入液晶元件LC之信號電壓週期的極性反轉。配合此等，施 加於液晶元件LC之共通電極COM之共通電壓vc〇M也必項 週期的作極性反轉。在此，在液晶元件LC與開關驅動此等 之TFT具有關於極性之非對稱性。為此，在像素電極側與共 通電極侧若預先配合中心位準，則顯示關於極性之非對稱 性’產生附著在一起等之畫質的劣化。該對策，係對信號 電壓僅特定電壓份偏置共通電壓，進行打消關於極性之非 對稱性。又，補助電容CS也必須配合液晶素子LCW交流驅 動，作交流動作。為此，在共通連接於各補助電容cs之補 助電容線，必須以相同之特定之週期施加極性反轉之電壓。 在包圍上述之顯示區域2之上下左右四邊，積體形成周邊 之電路部。在本實施型態的情形，該周邊電路部，係包含 垂直驅動器3、水平願動器4、⑶M驅動器5、以驅動器6、 DC/DC轉換器7、DC/DC轉換器7a、包含位準移相器（L/s) 之介面8、定時信號發生器9、模擬電壓信號發生器等。 但是’本發明並不限制於該構成，因應顯示裝置㈣規格， 追加適度必須之電路，一方面刪除不必要之電路。例如， 依情況也組入生成使用於與信號電壓不同之完全的白顯示 與完全的黑顯示之信號電壓位準之驅動器等。 89410.doc 200424999 垂直驅動器3係連接於各閘極線G1〜Gm,以線順序供給選 擇脈衝。水乎驅動器4係形成上下一對，連接於各信號線 S1〜Sn的兩端，由兩侧同時供給特定之信號電壓。又，該信 號包C係透過FPC 11形成因應由設定側送來之顯示資料 (影像資訊）者。 共通驅動器（COM驅動器）5係週期的將極性反轉之共通 電壓VCOM施加於共通於各液晶元件LC之共通電極。在 COM驅動器5附屬著偏壓電路與啟動電路（c〇M啟動器）。偏 壓電路係以共通驅動器調節生成之共通電壓之偏置位準。 啟動電路（COM啟動器）在面板之啟動時，充電偏壓電路， 迅速上昇共通電壓VC0M的施加。cs驅動器6係週期的將極 性反轉之電壓施加於共通於各補助電容CS2補助電容線。 DC/DC轉換态7，係由電子機器本體透過Fpc丨丨供給之一 次之電源電壓，變換成因應面板（顯示裝置〇)的規格之二次 的電源電壓。特別{，DC/DC轉換器7可以使用於正側之電 源電壓VDD的變換。對於此，dc/dc轉換器7a可以使用於 負側之電源電壓VSS的變換。 包含L/S介面8，係接受透過FPC u由設定側供給之計時 L號同步^號、影像#號等之控制信號。位準移相器 係將由設定側送來之控制信號（外部控制信號）作位準移 相，生成適合於顯不裝置内部的電路動作規格之控制信號 (内部控制^號）。又，在本說明書有必要區別外部控制信號 與内部控制信號的情形，在表示各控制信號的種類之記號的 後面，具有附上外部控制信號的場合之數字（3)、附上内部控 89410.doc -12- 200424999 制信號的情形之數字（5)。定時信號發生器9係處理由包含 L/S之介面送身之計時信號與同步信號，生成電路各部之時 序控制必要之計時信號等。模擬電壓信號發生器10係預先 將因應等級之多數之位準之模擬電壓供給至水平驅動器 4。水平驅動器4因應由電子機器的本體側送來之影像資 訊，將等級化之模擬之信號電壓寫入液晶元件LC。 圖2為對顯示裝置側之設定側的控制序列之時間分配 表，（A)為表示ON-序列；（B)為表示OFF-序列。圖2為表示 沒有關於待機模式（待用模式）之序列控制之通常的情形。對 於顯示側由設定側依照特定之序列輸入主計時MCK、水平 同步信號HS YNC、垂直同步信號VSYNC、顯示資料DATA、 重置信號RST、顯示許可信號PCI、電源電壓VDD。在由設 定側上昇顯示側之ON-序列（A)，最初VDD上昇，其次 MCK、HSYNC、VSYNC動作。經過時間tonl後，重置信號 RST由低切換至高，初期化顯示器的電路部。之後經過時 間ton2後，DATA由低切換至主動，並且顯示許可信號PCI 由低切換至高。藉此，影像放映至顯示器的顯示區域。 在由設定側上昇顯示器之OFF-序列（B)，首先DATA由主 動切換至低，並且顯示許可信號PCI由高切換至低。經過時 間toff 1後，重置信號RST由高切換至低，重置顯示器的電 路之内部狀態。經過時間toff2後，遮斷MCK、HSYNC、 VSYNC的供給，最後上昇VDD。藉此，VDD型承接地電位 或漂移電位。 圖3為顯示採用待機模式（待用模式）之ON-序列及OFF-序 89410.doc -13- 200424999 列之時間分配表。為了容易了解，在顯示於圖2之通常之ON-序列及與OFF-序列對應之部分使用對應之參照符號。設定 側可以切換通常消耗電力狀態與低消耗電力狀態。配合此 有必要作將顯示側切換成動作模式與待機模式（待用模式） 之控制，為此，設定側對顯示側輸入待用信號STB。 在ON-序列（A)，首先待用信號STB由低上昇至高，顯示 器由待機模式回復至動作模式。配合STB的上昇，MCK、 HSYNC、VSYNC形成主動。但是，VDD不管STB經常供給 著。經過時間tonl後，RST由低切換至高，初期化顯示器的 電路狀態。經過時間ton2後，DATA形成主動，並且PCI切 換至高，影像放映至顯示區域。 在OFF-序列（B)，首先DATA及PCI形成非主動。經過toff 1 後，RST由高變低，重置顯示器的内部電路。經過toff2後， STB由高切換至低，並且MCK、HS YNC、VS YNC形成主動。 藉STB由高變低，顯示側由動作模式移動至待機模式。一 方面VDD不管移動至待機模式，經常維持於電源電壓。 如此在採用待用模式之系統，在將VDD作成主動之狀態 下，因應STB將顯示側之驅動電路系統作成非主動。使用 於待用模式控制之信號STB，雖也有如圖示由設定側獨立 輸入之控制信號的情形，不過亦可以將由設定側供給之其 他之外部信號在顯示側内部的作邏輯處理生成。在OFF-序 列，以RST邏輯重置顯示器的内部電路之後，STB升起。此 時，由設定側供給之主計時MCK與同步信號HSYNC、 VSYNC等由主動之狀態固定於特定電位。在圖示之例雖固 89410.doc -14- 200424999 疋於低位準（GND位準），不過依情況即使固定於VDD亦可。 因應待用號S TB的上昇移動至待機模式之顯示裝置包 含待機控制手段，該待機控制手段係由電子機器的本體側 接文電源電壓VDD的供給之狀態下，停止顯示區域的驅 動’並且鈍化電路部控制面板的電力消耗。該待機控制手 段係分散配置於電路部的各塊，在每一各電路塊反應STB 的上幵貫行為了鈍化之控制序列。 圖4為附隨於圖丨之c〇M驅動器5之偏壓電路與顯示啟動 電路之具體的構成例之電路圖。本實施例係使用未對應於 待用模式之通常之啟動電路。如圖示，以共通驅動器（COM 驅動器）5作為中心配置著偏壓電路51及啟動電路52。c〇M 驅動器5因應特定之週期信號^^卩，將極性反轉之共通電壓 VCOM送出至輸出郎點vc〇MO。在本實施例，週期信號FRp 形成限制框週期之信號。又c〇M驅動器5係藉内部重置信號 RST〗形成如邏輯重置。 偏壓電路51包含耦合電容c卜該耦合電容C1係對信號電 壓為了調節共通電壓之位準，生成特定之偏置電壓Δν。該 耦合電容ci係外加零件，搭載於與組入面板之絕緣基板i 不同之基板。偏壓電路51除此之外包含著可變電阻R3與以 溥膜電晶體構成之開關SW4。可變電阻幻為外加零件。開 關SW4係包含於絕緣基板丨上之電路。顯現於可變電阻u 之即點VCOMI完成偏置之共通電壓vc〇M，係透過形成於 絕緣基板1上之配線，供給至共通電極連接墊53〇(c〇m連接 墊）。 89410.doc -15- 200424999 啟動電路52，在電源電壓上昇時將偏壓電路51之耦合電 谷C1預充電至偏置電壓Δν為止，並且在電源電壓之下降 時放電耦合電容C卜該啟動電路52為積體形成於絕緣基板工 上之内藏電路，包含輸入内部重置信號RST之緩衝器 (BUF)5 12、變換器515、緩衝器516、位準移相器520等。進 一步包含直列連接於正側之電源電壓VDD2與負側之電源 電M VSS之間之電阻in、R2。電阻汉丨與…之間之中間節 點，係透過節點VCOMO與開關SW3連接著。除此之外電阻 R1的上端側介在開關S W1，在電阻R2的上端側也介在著開 關S W2。由以上之構成可以明白，c〇M驅動器5、偏壓電路 5 1及啟動電路52之幾乎全部之部分積體形成於絕緣基板1 上，僅耦合電容C1及可變電阻R3形成外加。 持續參照圖4，說明電源投入時之啟動電路52之〇小序 列。在第一階段上昇顯示裝置之電源電壓VDD2。藉此，開 關SW1、SW2、SW3及SW4形成導通之狀態。藉直列電阻w、 R2 ’電阻分割VDD2，節點A形成中間電位△ V。由於開關 SW3、SW4也形成導通之狀態’所以節點vc〇MO也形成與 節點A同電位，充電耦合電容c 1。直列電阻ri、r2之比， 係設定成節點A與節點VCOMO的電位差成為△ V。 顯示裝置内之驅動電路用重置信號RST5上昇作為第二 階段。藉此，顯示裝置内之COM驅動器5形成主動，輸出交 流之共通電壓。此時反應至重置信號rST5,開關SW卜SW2、 SW3及SW4形成非導通之狀態。在耦合電容ci由於在第一階 段電荷已充分的充電，所以耦合COM驅動器5的輸出，僅 89410.doc -16 - 200424999 Λ V^DC偏移之電位輸出至飭 y Δ 即點VCOMI。可變電阻R3係設 定成節點VCOMI的電位Μ v偏移。之後，顯*開始信號 PCI上昇作為第三階段，影像敌映至顯示區域。 其次，說明啟動電路52之0FF-序列。在第一階段顯示命 令Ρα下降，示區域的晝面形成非顯示。接著在第二階 段，顯示裝置内之驅動電路用重置信號RST5下降。藉此， 開關SW1、SW2、SW3及SW4形成導通之狀態。開關SW1 係以 PMOSTFT構成，SW2、SW3 及 SW4 係以 NMOSTFT構 成。一方面顯示裝置内之CQM驅動器形成非主動。藉直列 電阻Rl、R2電阻分割電源電位VDD2，在節點A中形成中間 電位Δν。由於SW4也形成導通狀態，所以節點vc〇MI形 成GND位準。藉此，耦合電容ci被放電。之後，電源電壓 VDD2下降作為第三階段。 圖5為上述之ON-序列之時間分配表。比一點虛線上面之 部分係表示由設定側輸入面板側之顯示資料DATA、重置信 號RST3、顯示開始信號PCI、電源電壓VDD之狀態變化。 比一點虛線下面之部分係表示在面板内產生之電源線、節 點、内部信號等之狀態變化。如圖示，在時序T1由設定側 供給電源電壓VDD，在時序T3輸入為了初期化之重置信號 3，在時序T5輸入顯示資料DATA及顯示開始信號PCI。一方 面在面板内部，在時序T1設定正側之電源電壓VDD2及負側 之電源電壓VSS2。藉此，啟動電路開始動作，開始耦合電 容的充電。因應充電節點VCOMO之電位上昇。在時序T3 節點VCOMO上昇到特定之偏置電位△ V為止。配合此等週 89410.doc -17- 200424999 期信號FRP形成主動，並且信號電位設定於黑位準。進一牛 在時序T5信號電位SIG由黑位準形成主動，顯示（Dispi=) 形成有效。 圖6為上述之OFF-序列之時間分配表。由設定側在時序 T1顯示資料DATA及顯示命令PCI落入低位準。更進一步， 在日^序T3重置#號RST3落入低位準，之後在時序η電源電 壓VDD落入低位準。在配合此等之面板内部，在時序”信 號電壓SIG由主動變化成黑位準，並且顯示狀態由有效切換 成黑顯示。進一步在時序Τ3内部重置信號RST5下降，開始 搞合電容的放電。藉此，節點VC0M0的電位慢慢的降低， 在時序T5到達低位準。配合此等，遮斷電源電壓VDD2及 VSS2 〇 圖7為顯示具備待機模式之啟動電路52之實施例之電路 圖。為了容易了解，在與顯示於圖4之剛才之啟動電路對應 之部分賦予對應之參照符號。在具備待機模式之系統顯示 為’即使由動作模式移動至待機模式的情形，電源Vdd也 不會被遮斷。在此，藉待用信號STB作為電源vdd之代用， 控制啟動電路52。 與顯示於圖4之剛才之實施例同樣，共通驅動器5係施加 共通電壓VCOM於共通電極。偏壓電路51具備有對信號電 壓為了相對的調節共通電壓之位準生成特定之偏置電壓 △ V之搞合電容ci。啟動電路52當電源電壓VDD2之上昇 時’將偏壓電路51之耦合電容ci充電至偏置電壓av為 止’並且當電源電壓VDD2之下降時將耦合電容C1放電。如 89410.doc -18- 200424999 圖不，COM驅動器5、偏壓電路51及啟動電路52，除了耦合 電容C1及可變電阻R3之外搭載於共通之絕緣基板1上。 偏塵電路51除了前述之麵合電容〇之外，包含電晶體開 關SW4與電壓位準調整用之可變電阻R3。電阻们係與麵合 電容C1同樣為外加零件。電晶體開關_係形成於絕緣基 板1。由絕緣基板丨外之耦合電容〇1輸入之偏置處理完成之 共通電壓VCOMI，係連繫於系統顯示器内部之共通電極， 以内部配線連接於COM連接墊530。 啟動電路52包含著輸入待用信號STB之位準移相器 511、輸入内部重置信號RST5之變換器512、輸入外部重置 信號RST3之變換器513、非與元件NAND 514、變換器515、 緩衝器（BUF)516、緩衝器517、位準移相器520等之邏輯電 路。進一步，包含著以薄膜電晶體構成之開關SW1、SW2、 S W3、S W5。加上包含著直列連接於正側之電源電壓vdd2 與負側之電源電壓V S S 2之間之一對之電阻r 1、R2。以節點 A表示電阻R1與R2之連接點。 接著參照圖7，說明啟動電路52之ON-序列及OFF序列。 首先’在由待機模式回復至動作模式之〇N_序列，stb信號 由低上昇至高作為第一階段。藉此，開關Swi、SW2、SW3、 SW4形成導通狀悲。精直列電阻ri、R2，電阻分割電源電 位VDD2，在節點A中形成所希望之中間電位。該中間電位 等於必要之偏置電位△ V。由於SW3、SW4形成導通之狀 態，所以節點VCOMO也形成與節點A同電位，預充電麵合 電容C1。直列電阻Rl、R2之比，係設定成節點a與節點 89410.doc -19 - 200424999 VCOMO的電位差成為△ V。之後，重置信號RST3、RST5 上昇作為第.二階段，COM驅動器5形成主動。同時，開關 SW1、SW2、SW3、SW4形成非導通之狀態。一方面開關SW5 形成導通狀態，節點VCOMPWR形成VDD2，電流流至可變 電阻R3。在耦合電容C1由於在最初之第一階段電荷已充分 的充電，所以耦合COM驅動器5的輸出，僅△ V之DC偏移之 電位輸出至節點VCOMI。可變電阻R3係設定成節點VCOMI 的電位剛好僅為Δν偏移。之後，顯示開始信號PCI上昇作 為第三階段，影像放映至顯示區域。 其次，說明由動作模式移動至待機模式之OFF-序列。最 初由設定側之顯示命令PCI下降作為第一階段，影像由顯示 區域消失。接著重置信號RST3、RST5下降作為第二階段。 藉此，開關SW1、SW2、SW3、SW4形成導通狀態。反之SW5 形成非導通狀態。藉此電流不能流動於外加之可變電阻 R3，可以得到所希望之節電效果。同時由於絕緣基板1内之 COM驅動器5形成非主動，所以可以得到節電效果。藉導通 開關SW1、SW2，利用直列電阻Rl、R2，電源電位VDD2 在節點A中形成所希望之中間電位。此時SW4由於也形成導 通狀態，所以節點VCOMI形成GND位準。最後STB信號下 降作為第三階段，開關SW1、SW2、SW3、SW4形成非導通 之狀態。藉此直列電阻Rl、R2由正侧電源線VDD2及負側 電源線V S S 2切離，形成不要之電流不會流動。從而5可以 得到所希望之節電效果。 圖8為具備待機模式之啟動電路之ON-序列之時間分配 89410.doc -20- 200424999 表。在ON·序列由待機模式回復至動作模式時，由設定側待 用L號8丁8在時序丁1上昇。—方面電源電壓¥〇〇由當初维 持在高位準。㈣序T5顯示資料DATA及顯*開始信號ρα 形成主動。對應於此等在面板内部，在時序τι内部電源電 壓VDD2及VSS2有效化。進—步因應剌信號咖開始輕合 電容的充電，節點VC0M0的電位開始上昇至特定之偏置電 位。在時序T3當到達特定之偏置電位時，内部重置信號 RST5上幵，共通驅動器形成主動。更進一步，在時序η信 號電位SIG形成主動並且顯示有效化。 圖9為表示具備待機模式之啟動電路之0FF序列。當由動 :模式移動至待機模式時，實行該·序列。與電源遮斷 時之OFF-序列不同，可以維持VDD，一方面待用信號則 在時序T5由高位準下降至低位準。在此之前在時序T3重置 乜號RST下降。因應此等在面板内部開始輕合電容之放 電，節點VCOMO的電位向低位準降低。 (產業上利用的可能性） 如以上說明，在本發明藉設置在電源投入時急速的使耦 合電容充電之啟動電路，可以抑制影像之閃爍等，可以實 現高畫質化。特別是，藉在絕緣基板上内藏在電源投入時 急速充電共通電壓DC偏移用之耦合電容之啟動電路，可以 實現設定的小型化及低成本化。又，即使在具備待機模式 之顯示系統中，亦可以因應待用信號的切換，藉設置急速 的充放電共通電壓〇(：偏移用之耦合電容之啟動電路，可以 減輕閃爍的發生等。又，藉將如此之啟動電路搭載於絕緣 89410.doc 21 200424999 基板上可以貫現具備低消耗電力模式之設定之小型化及 低成本化。 【圖式簡單說明】 圖1為關於本發明之顯示裝置之全體構成之塊圖。 圖2(a)(b)為顯示裝置之〇N_序列及〇卯_序列之時間分配 表。 圖3(A)(B)為具備待機模式之顯示裝置之ON-序列及OFF_ 序列之時間分配表。 圖4為搭載於圖1之顯示裝置之啟動電路之實施例之電路 圖。 圖5為顯示於圖4之啟動電路on-序列之時間分配表。 圖6為顯示於圖4之啟動電路0FF_序列之時間分配表。 圖7為對應待機模式之啟動電路的實施例之電路圖。 圖8為顯示於圖7之啟動電路〇N_序列之時間分配表。 圖9為顯示於圖7之啟動電路off-序列之時間分配表。 【主要元件符號說明】 0 顯示裝置 1 絕緣基板 2 顯示區域 3 垂直驅動器 4 水平驅動器 5 COM驅動器 6 C S驅動器 7 > 7a DC/DC轉換器 89410.doc -22- 200424999 8 介面 9 … 定時信號發生器 10 模擬電壓信號發生器 11 軟性印刷電纜（FPC) 51 偏壓電路 52 啟動電路 512 緩衝器（BUF) 514 非與元件NAND 515 變換器 516 、 517 緩衝器（BUF) 520 位準移相器 530 共通電極連接墊 G 閘極線 S 信號線 R1、R2 電阻 R3 可變電阻 Δ V 偏置電壓 Cl 耦合電容 L/S 位準移相器 LC 液晶元件 CS 補助電容 TET 薄膜電晶體 COM 共通電極 VDD 正側之電源電壓 89410.doc -23- 200424999 vss 負側之電源電壓 MCK … 主計時 RST 重置信號 PCI 顯示許可信號 STB 待用信號 SW1、SW2、 開關 SW3 及 SW4 SIG 信號電位 VCOM 共通電壓 HSYNC 水平同步信號 VSYNC 垂直同步信號 DATA 顯不資料 VCOMO 節點 89410.doc 24-200424999 IX. Description of the invention: [Technical field insulted by the invention] The present invention relates to a display device having a pixel electrode and an ugly electrode facing the pixel electrode. More detailed is about an improved technique around a circuit that generates an AC common voltage applied to a common electrode. [Prior art] Flat display devices such as Bai Zhi's active matrix liquid crystal panels are mostly used as display parts for electronic devices. The active matrix type display panel is operated in response to the voltage of the display data source supplied from the main body of the electronic device. Generally, the display is formed by the integration of the insulating body. The so-called system display that drives the circuit part around the display area writes this In some cases, the display area contains an electro-optical substance; the electro-optic stomach is held between the pixel electrodes arranged in a matrix and the common electrodes facing the pixel electrodes. On the one hand, the area surrounding the display area includes: a driver and a common driver; the driver responds to: ::,, write: signal voltage to the pixel electrode side; the common driver, from the dragon to the common electrode side . A display device having such a structure is disclosed in Japanese Patent Application Laid-Open No. 2000-193941. Material: In the case of liquid crystal as an electro-optical substance, an AC drive is usually used to prevent liquid crystal. The polarity of the signal voltage applied to the = electrode side is reversed at each specific cycle, and in conjunction with these common power plants, the conventional common driver inverts to generate a common element ㈣Γ at a specific cycle. The main components driving these thin film transistors etc. are based on asymmetry with respect to polarity. Therefore, if the number ❹ 89410.doc 200424999 of the common voltage center + office + office + θ bits are all the same, then the asymmetry entanglement and flashing are revealed. Second: the image is deteriorated. Here, the conventional display device is added with the common drive level, which can hurt the generation of signal voltage to adjust the common current. About the liquid crystal material blood master: Pan :: Hedian Valley of the circuit. In order to offset the asymmetry of the polarities of the two, ^, + /, and the active file, the bias private σ is set to prevent the image from being lumpy and flashy. Before entering the display, install the & φ dissipation capacitor to a specific one: it must be charged until the bias circuit is included in the daylight circuit. If charging is completed, the normal image can be obtained because the common voltage that can be double-moved = output plus a specific bias voltage. However, after the power is turned on, the transition period of the coupling capacitor's heart ’is uneasy due to the common level of ^, so there is a case of seeing a flashing light. In order to prevent this, it is conventionally known to use a start-up circuit for coupling the lightning circuit, that is, the electricity when the power is turned on again. This starting material can also be used when the light-emitting capacitor is discharged when the power is interrupted. However, the "starter circuit (rapid charge / discharge circuit) for the common driver of the conventional system has been realized in the driving system outside the display device which adopts the system display structure." There is an increase in the number of parts and a display driving system The problem of getting bigger. [Summary of the Invention] Based on the above-mentioned conventional technical problems, the present invention aims to mount a startup circuit for a common driver in a display device adopting a system display configuration. To achieve this, the following measures are taken. That is, the display device of the present invention is characterized in that it can be used as a display part of an electronic device, and according to the display data and electricity supplied from the main body side of the electronic device, 89410.doc 200424999 is made of insulating U ± rz. The integrated body on the board forms a display area and a panel that drives the display area. The display area includes the electrical substance, the seven minds, and the electrocardio-optical substance. The pixels are arranged in a matrix. And the common electrode opposite to the pixel electrode; the aforementioned circuit section includes: driving the cry, /? 0 in response to the display data 'write signal electricity to the pixel electricity only though you | ·, g, /, 逋The driver is to apply a common voltage to the common electrode side; the circuit is designed to provide a coupling capacitor that generates a bias voltage for adjusting the common voltage level to the voltage of 彳 §; and the start-up circuit The following day, the coupling capacitor of the bias circuit was precharged to the bias voltage :, and when the power supply voltage dropped, the coupling capacitor was discharged. Specifically, the panel described above is composed of the display area and the circuit that drives the periphery of the display area, a + and a thin film electrical body formed in the same process on a common insulating substrate. The aforementioned common driver, bias The voltage-voltage circuit and the start-up circuit ^ / ^ β are not mounted on the common insulating substrate. It is preferred that the start-up circuit be in a non-actuated state at a time other than when the start-up circuit is operated only when the power supply voltage is increased and when the power supply voltage is decreased. In addition, the display device of the present invention is characterized in that it can be used as a display of an electronic device that has a constant power consumption state and a low power consumption state. "The two pieces operate according to the display data and power supply I supplied from the body side of the electronic device. The display area and the panel of the circuit part around the display area are formed by an integrated body on an insulating substrate; the foregoing panel is in accordance with the general power-saving state and low power-consumption state of the private machine ② body side: Switching can be switched to operation mode and standby mode; including standby control means' When it is in operation mode, the main body side of the electronic device receives the supply voltage 89410.doc 200424999 to actuate the drive. The desired display is to wait until the main body side of the electronic device receives the supply of power voltage, the drive of this area, and the passivation circuit section to suppress the power consumption of the panel; The domain does not contain electrical and optical materials; the optical materials are kept in the matrix, pixel electrodes and opposite The common electrode of the pixel electrode is between the two; the aforementioned circuit section includes: a driver, which is based on the electronic device's body, and writes the signal voltage to the pixel electrode side; the common driver, The common-electrode side is applied; the bias voltage 筏, 目 目 m 具备 circuit is equipped with a surface capacitor for the bias voltage of the signal voltage generation to adjust the level of the Qiutong power plant; and Kai = circuit, When returning from the standby mode to the operation mode, pre-charge the coupling capacitor of the bias circuit to the offset in advance, and when moving from the operation mode to the standby mode, the coupling electric valley is discharged specifically. It is composed of a region and the circuit portion that drives the periphery of the display region, and is formed by a thin film transistor formed in the same sequence on an insulating substrate. The common driving H, the bias circuit and the startup circuit Electricity is mounted on this common insulating substrate. Preferably, the above-mentioned activation is activated when returning from the standby mode to the operation mode and when the operation mode is moved + the earth mode, and the rest of the time is to form a non-active energy. According to the present invention, a system for rapidly charging a bias capacitor for a two-way voltage applied to a common electrode of a display device to quickly charge a capacitor to a desired bias potential at power-on is installed in a liquid crystal display device. That is, the display panel constituted by the system display is composed of the display area and the circuit part driving the periphery of the display area, and a thin-film transistor formed in the same process shape on a common insulating substrate. It belongs to the voltage circuit and the startup circuit, and is formed on the common insulating substrate by a thin film transistor or the like in addition to the MEMS common driver and the bias I # ^ 0. Siji Broadcasting, $ Α ^ ‘Brother’ can be used to change the normal operation mode and standby mode 77. 乂 切 u., ^ ^ 糸 ,, first display. At this time, when returning from the to-be-armed mode to the action mode, the slave unit also has a private coupling capacitor. To this end, Qi Ying set. The road may be embedded in the display. [Embodiment] An embodiment of the present invention will be described in detail with reference to the following drawings. Figure ^ Off The block diagram of the overall structure of the display device. As shown in the figure, the display device 0 is formed on the insulating substrate 丨 described by glass material. A display area 2 'is formed in the center of the insulating substrate 为了 so as to surround these peripheral circuit portions. On the rectangular insulating substrate 1, a connection terminal is formed through the flexible printing t_PC) u 'to form a connection with the electronic device body side (setting side). FPCU is a flat cable with a single layer structure that forms a large number of wiring planes. The display area 2 is formed by a matrix of gate lines ⑴ arranged in columns, such as a matrix that is arranged to intersect with the row of signal lines S1 to Sn. Pixels are formed at the intersections of the gate lines g and the signal lines §. In this embodiment, each pixel is composed of a liquid crystal element LC, a storage capacitor CS, and a thin film transistor TET. The liquid crystal element lc is constituted by a liquid crystal (electro-optical substance) held between a pixel electrode and a common electrode (com) opposed to these. The gate electrode of TF D is connected to the gate line G, the source electrode is connected to the signal line s, and the drain electrode is connected to the pixel electrode of the liquid crystal element LC. The auxiliary capacitor CS is connected between the electrode of the tft 89410.doc -10- 200424999 and the auxiliary capacitor line. The TFT is turned on with a selection pulse supplied from the gate line 0, writes, and enters a pixel electrode of the liquid crystal element LC corresponding to the signal voltage supplied from the signal line S. The auxiliary capacitor CS holds a signal voltage in advance between a frame or a field. The liquid crystal element LC is generally driven by an AC. That is, the polarity of the signal voltage period written to the liquid crystal element LC through the signal line s is reversed. In conjunction with this, the common voltage vc0M applied to the common electrode COM of the liquid crystal element LC must also be periodically reversed in polarity. Here, the liquid crystal element LC and the TFTs that drive the switches have asymmetry with respect to polarity. For this reason, if the center level is set in advance on the pixel electrode side and the common electrode side, it is shown that the asymmetry of the polarity 'causes deterioration of the image quality such as adhesion. This countermeasure is to offset the common voltage by a specific voltage portion of the signal voltage to cancel the asymmetry of the polarity. In addition, the auxiliary capacitor CS must also cooperate with the liquid crystal element LCW AC drive for AC operation. For this reason, in the auxiliary capacitor lines commonly connected to the respective auxiliary capacitors cs, it is necessary to apply a voltage with a polarity reversal at the same specific cycle. On the four sides surrounding the display area 2 above and below, the integrated body forms a peripheral circuit portion. In the case of this embodiment, the peripheral circuit unit includes a vertical driver 3, a horizontal actuator 4, a CDM driver 5, a driver 6, a DC / DC converter 7, a DC / DC converter 7a, and a level Interface 8 of phase shifter (L / s), timing signal generator 9, analog voltage signal generator, etc. However, the present invention is not limited to this configuration. In accordance with the specifications of the display device, a moderately necessary circuit is added, and unnecessary circuits are deleted. For example, a driver for generating a signal voltage level that is used for a completely white display and a completely black display that is different from the signal voltage may also be incorporated. 89410.doc 200424999 The vertical driver 3 is connected to each of the gate lines G1 to Gm, and supplies selection pulses in line order. Shuihu driver 4 is a pair of top and bottom, connected to both ends of each signal line S1 ~ Sn, and a specific signal voltage is simultaneously supplied from both sides. The signal package C is formed by the FPC 11 in response to display data (image information) sent from the setting side. The common driver (COM driver) applies a common voltage VCOM whose polarity is reversed for 5 cycles to a common electrode that is common to each liquid crystal element LC. The COM driver 5 is provided with a bias circuit and a start-up circuit (common starter). The bias circuit adjusts the bias level of the common voltage generated by the common driver. When the start-up circuit (COM starter) is started on the panel, the charging bias circuit rapidly increases the application of the common voltage VCOM. The cs driver 6 is a cycle in which a polarity-reversed voltage is applied to the auxiliary capacitor lines common to the auxiliary capacitors CS2. The DC / DC conversion state 7 is a primary power voltage supplied by the electronic device body through Fpc 丨 丨, and is converted into a secondary power voltage according to the specifications of the panel (display device 0). In particular, the DC / DC converter 7 can be used to convert the power supply voltage VDD on the positive side. For this, the dc / dc converter 7a can be used for conversion of the power supply voltage VSS on the negative side. Including L / S interface 8, it accepts the control signals of timing L number synchronization ^ number, image # number, etc. supplied from the setting side through FPC u. Level phase shifter Phase control phase control signal (external control signal) sent from the setting side for phase shifting to generate a control signal (internal control ^) suitable for the circuit operation specifications inside the display device. Also, in this description, it is necessary to distinguish between external control signals and internal control signals. After the mark indicating the type of each control signal, there is a number (3) where an external control signal is attached, and an internal control 89410 is attached. doc -12- 200424999 The number of cases (5). The timing signal generator 9 processes timing signals and synchronization signals sent from the interface including L / S, and generates timing signals necessary for timing control of each part of the circuit. The analog voltage signal generator 10 supplies an analog voltage corresponding to a majority of levels to the horizontal driver 4 in advance. The horizontal driver 4 writes the hierarchical analog signal voltage into the liquid crystal element LC in response to the image information sent from the main body side of the electronic device. Fig. 2 is a time allocation table for a control sequence on a setting side of a display device side, (A) represents an ON-sequence and (B) represents an OFF-sequence. Fig. 2 shows the general case without the sequence control regarding the standby mode (standby mode). For the display side, the setting side inputs the master timing MCK, the horizontal synchronization signal HS YNC, the vertical synchronization signal VSYNC, the display data DATA, the reset signal RST, the display permission signal PCI, and the power supply voltage VDD according to a specific sequence. In the ON-sequence (A) of the display side rising from the setting side, VDD rises first, and then MCK, HSYNC, and VSYNC operate. After the time tonl has elapsed, the reset signal RST is switched from low to high to initialize the circuit portion of the display. After the time ton2 later, DATA switches from low to active, and the display permission signal PCI switches from low to high. Thereby, the image is projected to the display area of the display. In the OFF-sequence (B) of the display rising from the setting side, first DATA is switched from active to low, and the display permission signal PCI is switched from high to low. After the time toff 1 has elapsed, the reset signal RST is switched from high to low to reset the internal state of the display circuit. After the time toff2 elapses, the supply of MCK, HSYNC, and VSYNC is interrupted, and finally VDD rises. As a result, the VDD type receives ground potential or drift potential. Fig. 3 shows the time allocation table of the ON-sequence and OFF-sequence using the standby mode (standby mode) 89410.doc -13- 200424999 column. For easy understanding, the corresponding ON-sequences shown in FIG. 2 and the portions corresponding to the OFF-sequences are used with corresponding reference symbols. The setting side can switch between the normal power consumption state and the low power consumption state. To cope with this, it is necessary to control the display side to switch to the operation mode and the standby mode (standby mode). To this end, the setting side inputs the standby signal STB to the display side. In the ON-sequence (A), the standby signal STB rises from low to high first, and the display returns from standby mode to operation mode. With the rise of STB, MCK, HSYNC, and VSYNC become active. However, VDD is always supplied regardless of the STB. After the time tonl has elapsed, RST is switched from low to high to initialize the circuit state of the display. After the time ton2, DATA becomes active, and the PCI switches to high, and the image is projected to the display area. In the OFF-sequence (B), DATA and PCI first become inactive. After toff 1, RST changes from high to low to reset the internal circuit of the display. After toff2, STB switches from high to low, and MCK, HS YNC, and VS YNC become active. As STB changes from high to low, the display side moves from the operation mode to the standby mode. On the one hand, VDD is always maintained at the power supply voltage regardless of moving to standby mode. Thus, in the system using the standby mode, when the VDD is made active, the display side drive circuit system is made inactive according to the STB. Although the signal STB used for the standby mode control may be a control signal independently input by the setting side as shown in the figure, other external signals supplied by the setting side may be generated by logic processing inside the display side. After the OFF-sequence resets the internal circuit of the display with RST logic, the STB rises. At this time, the main timing MCK and synchronization signals HSYNC, VSYNC, etc. supplied from the setting side are fixed at a certain potential by the active state. The example shown in the figure is fixed at 89410.doc -14- 200424999 at the low level (GND level), but it can be fixed to VDD depending on the situation. The display device that moves to the standby mode in response to the rise of the standby number S TB includes a standby control means. The standby control means stops the driving of the display area while the supply of the power supply voltage VDD is received from the main body of the electronic device. The power consumption of the control panel of the circuit section. The standby control means is distributed in each block of the circuit section, and each of the circuit blocks reacts to the upper part of the STB to perform a passivation control sequence. FIG. 4 is a circuit diagram of a specific configuration example of the bias circuit and the display start circuit of the CMOS driver 5 attached to FIG. This embodiment uses a normal startup circuit which does not correspond to the standby mode. As shown in the figure, a bias circuit 51 and a start-up circuit 52 are arranged around a common driver (COM driver) 5 as a center. The cOM driver 5 sends the common voltage VCOM with the polarity reversed to the output point vcOMO in response to a specific periodic signal ^^ 卩. In this embodiment, the periodic signal FRp forms a signal that restricts the frame period. The CMOS driver 5 is formed as a logic reset by the internal reset signal RST. The bias circuit 51 includes a coupling capacitor c. The coupling capacitor C1 generates a specific bias voltage Δν for adjusting the level of the common voltage to the signal voltage. The coupling capacitor ci is an external component and is mounted on a substrate different from the insulating substrate i incorporated in the panel. The bias circuit 51 includes, in addition, a variable resistor R3 and a switch SW4 composed of a diaphragm transistor. The variable resistor is an extra part. The switch SW4 is a circuit included on the insulating substrate. The common voltage vcom, which appears at the point where VCOMI of the variable resistor u is biased, is supplied to the common electrode connection pad 53o (c0 connection pad) through the wiring formed on the insulating substrate 1. 89410.doc -15- 200424999 The start-up circuit 52 precharges the coupling valley C1 of the bias circuit 51 to the bias voltage Δν when the power supply voltage rises, and discharges the coupling capacitor C when the power supply voltage drops. The circuit 52 is a built-in circuit formed on an insulating substrate, and includes a buffer (BUF) 5 12 that inputs an internal reset signal RST, a converter 515, a buffer 516, a level phase shifter 520, and the like. Further, the resistances in, R2 between the power supply voltage VDD2 connected to the positive side and the power supply M VSS on the negative side are included in series. The intermediate node between the resistor Han and ... is connected to the switch SW3 through the node VCOMO. In addition, the upper end of the resistor R1 is connected to the switch SW1, and the upper end of the resistor R2 is also connected to the switch SW2. It can be understood from the above structure that almost all of the integrated components of the CMOS driver 5, the bias circuit 51, and the start circuit 52 are formed on the insulating substrate 1, and only the coupling capacitor C1 and the variable resistor R3 are added. With continued reference to Fig. 4, a small sequence of the start-up circuit 52o when the power is turned on will be described. In the first stage, the power supply voltage VDD2 of the display device is increased. Thereby, the switches SW1, SW2, SW3, and SW4 are turned on. VDD2 is divided by the in-line resistors w, R2 ', and the node A forms an intermediate potential ΔV. Since the switches SW3 and SW4 are also in a conductive state ', the node vc0MO also forms the same potential as the node A, and charges the coupling capacitor c1. The ratio of the in-line resistances ri and r2 is set so that the potential difference between the node A and the node VCOMO becomes ΔV. The driving circuit in the display device uses the rising of the reset signal RST5 as the second stage. As a result, the COM driver 5 in the display device becomes active and outputs a common voltage for AC. At this time, the signal is reset to the reset signal rST5, and the switches SW2, SW2, SW3, and SW4 become non-conductive. Since the charge in the coupling capacitor ci is fully charged in the first stage, the output of the coupled COM driver 5 is only 89410.doc -16-200424999 Λ V ^ DC offset potential is output to 饬 y Δ that is the point VCOMI. The variable resistor R3 is set so that the potential M v of the node VCOMI is shifted. After that, the display start signal PCI rises as the third stage, and the image is reflected to the display area. Next, the OFF-sequence of the start-up circuit 52 will be described. In the first stage, the display command Pα decreases, and the daytime surface of the display area becomes non-display. Then in the second stage, the driving circuit in the display device is lowered with the reset signal RST5. Accordingly, the switches SW1, SW2, SW3, and SW4 are turned on. The switch SW1 is composed of a PMOSTFT, and SW2, SW3, and SW4 are composed of an NMOSTFT. On the one hand, the CQM driver in the display device becomes inactive. The power supply potential VDD2 is divided by the in-line resistors R1 and R2 to form an intermediate potential Δν in the node A. Since SW4 is also turned on, the node vcMI forms the GND level. Thereby, the coupling capacitor ci is discharged. After that, the power supply voltage VDD2 drops as the third stage. FIG. 5 is a time allocation table of the above-mentioned ON-sequence. The part above the dotted line indicates changes in the state of the display data DATA, the reset signal RST3, the display start signal PCI, and the power supply voltage VDD from the setting side input panel side. The part below the one-dot dotted line indicates the state change of the power line, node, and internal signal generated in the panel. As shown in the figure, the power supply voltage VDD is supplied from the setting side at timing T1, the reset signal 3 for initialization is input at timing T3, and the display data DATA and the display start signal PCI are input at timing T5. On one side, the power supply voltage VDD2 on the positive side and the power supply voltage VSS2 on the negative side are set at timing T1. Thereby, the start-up circuit starts to operate, and the charging of the coupling capacitor is started. The potential of the charging node VCOMO rises. At time T3, the node VCOMO rises to a specific bias potential ΔV. In accordance with these weeks, 89410.doc -17- 200424999 period signal FRP is active, and the signal potential is set at the black level. Further, at the timing T5, the signal potential SIG is actively formed from the black level, and the display (Dispi =) is effective. FIG. 6 is a time allocation table of the above-mentioned OFF-sequence. The setting side displays the data DATA at the timing T1 and the display command PCI falls to a low level. Further, at the sequence T3, the reset number # RST3 falls to the low level, and then at time η, the power supply voltage VDD falls to the low level. Within these panels, the "signal voltage SIG" changes from active to black level at the time sequence, and the display state changes from active to black display. Further, the reset signal RST5 falls within time sequence T3 and starts to discharge the capacitor. As a result, the potential of the node VC0M0 gradually decreases and reaches a low level at the timing T5. With this, the power supply voltages VDD2 and VSS2 are interrupted. FIG. 7 is a circuit diagram showing an embodiment of the startup circuit 52 having a standby mode. It is understood that the corresponding reference symbols are assigned to the parts corresponding to the start-up circuit shown in Fig. 4. In a system with a standby mode, it is displayed as' even if it moves from the operating mode to the standby mode, the power supply Vdd will not be interrupted. Here, the standby signal STB is used as a substitute for the power source vdd to control the start-up circuit 52. As in the previous embodiment shown in FIG. 4, the common driver 5 applies a common voltage VCOM to the common electrode. The bias circuit 51 includes There is a coupling capacitor ci that generates a specific bias voltage Δ V for the relative adjustment of the common voltage level of the signal voltage. When the power supply voltage VDD2 rises, 'the coupling capacitor ci of the bias circuit 51 is charged up to the bias voltage av' and when the power supply voltage VDD2 falls, the coupling capacitor C1 is discharged. As shown in 89410.doc -18- 200424999 The COM driver 5, the bias circuit 51, and the start-up circuit 52 are mounted on a common insulating substrate 1 in addition to the coupling capacitor C1 and the variable resistor R3. The dust bias circuit 51 includes electricity in addition to the aforementioned surface capacitor 〇 The crystal switch SW4 and the variable resistor R3 for voltage level adjustment. The resistors are the same external components as the planar capacitor C1. The transistor switch_ is formed on the insulating substrate 1. It is input by the coupling capacitor outside the insulating substrate The common voltage VCOMI after the bias processing is completed is connected to the common electrode inside the system display, and is connected to the COM connection pad 530 by internal wiring. The start-up circuit 52 includes a level shifter 511 for inputting the signal STB to be used, an input Converter 512 with internal reset signal RST5, converter 513 with external reset signal RST3 input, NAND 514, converter 515, buffer (BUF) 516, buffer 517, level shifter 520, etc. Logic circuit. In addition, it includes switches SW1, SW2, SW3, and SW5 made of thin-film transistors. It also includes a pair between the positive-side power supply voltage vdd2 and the negative-side power supply voltage VSS2. Resistor r1, R2. Node A represents the connection point between resistors R1 and R2. Next, the ON-sequence and OFF-sequence of the start-up circuit 52 will be described with reference to Fig. 7. First, 'from the standby mode to the ON mode of ON_ In sequence, the stb signal rises from low to high as the first stage. As a result, the switches Swi, SW2, SW3, and SW4 form a conductive state. The precision in-line resistors ri, R2 and the resistor-divided power supply potential VDD2 form a desired intermediate potential in the node A. This intermediate potential is equal to the necessary bias potential ΔV. Since SW3 and SW4 are turned on, the node VCOMO also forms the same potential as the node A, and the pre-charged surface capacitor C1. The ratio of the in-line resistors R1 and R2 is set such that the potential difference between the node a and the node 89410.doc -19-200424999 VCOMO becomes ΔV. After that, the reset signals RST3 and RST5 rise as the second phase, and the COM driver 5 becomes active. At the same time, the switches SW1, SW2, SW3, and SW4 become non-conductive. On the one hand, the switch SW5 is turned on, the node VCOMPWR forms VDD2, and the current flows to the variable resistor R3. In the coupling capacitor C1, since the charge is fully charged in the first stage, the output of the coupled COM driver 5 only outputs the potential of the DC offset of ΔV to the node VCOMI. The variable resistor R3 is set so that the potential of the node VCOMI is just shifted by Δν. After that, the display start signal PCI rises as the third stage, and the image is projected to the display area. Next, an OFF-sequence for moving from the operation mode to the standby mode will be described. Initially, the display command of the setting side PCI is lowered as the first stage, and the image disappears from the display area. Then the reset signals RST3 and RST5 fall as the second phase. Thereby, the switches SW1, SW2, SW3, and SW4 are turned on. Conversely, SW5 becomes non-conducting. As a result, the current cannot flow through the external variable resistor R3, and the desired power saving effect can be obtained. At the same time, since the COM driver 5 in the insulating substrate 1 is inactive, a power saving effect can be obtained. By turning on the switches SW1 and SW2 and using the in-line resistors R1 and R2, the power supply potential VDD2 forms a desired intermediate potential in the node A. At this time, since SW4 is also turned on, the node VCOMI forms the GND level. Finally, the STB signal drops as the third stage, and the switches SW1, SW2, SW3, and SW4 become non-conductive. As a result, the in-line resistors R1 and R2 are cut off by the positive-side power supply line VDD2 and the negative-side power supply line V S S 2, and an unnecessary current does not flow. Thus 5 can obtain the desired power saving effect. Figure 8 shows the time allocation of the ON-sequence of the start-up circuit with standby mode. 89410.doc -20- 200424999 table. When the ON · sequence returns from the standby mode to the operation mode, the setting side standby L number 8 to 8 rises at the timing D1. —The supply voltage ¥ 〇〇 has been maintained at a high level since the beginning. The sequence T5 display data DATA and the * start signal ρα form an initiative. Corresponding to this, within the panel, the internal power supply voltages VDD2 and VSS2 are enabled at timing τι. Further-in response to the signal signal, the light-on capacitor is charged, and the potential of the node VC0M0 starts to rise to a specific bias potential. At timing T3, when a certain bias potential is reached, the internal reset signal RST5 is asserted, and the common driver becomes active. Furthermore, the signal potential SIG becomes active at the timing n and is shown to be effective. FIG. 9 shows an 0FF sequence of a startup circuit having a standby mode. This sequence is executed when the auto: mode is moved to the standby mode. Unlike the OFF-sequence when the power is turned off, VDD can be maintained. On the one hand, the standby signal falls from the high level to the low level at timing T5. Prior to this reset at timing T3, the number RST falls. In response to this, the discharge of the light-on capacitor is started inside the panel, and the potential of the node VCOMO decreases to a low level. (Possibility of Industrial Utilization) As described above, in the present invention, by providing a start-up circuit that rapidly charges the coupling capacitor when the power is turned on, it is possible to suppress image flicker and the like, and achieve high image quality. In particular, the start-up circuit of the coupling capacitor for the DC offset of the common charging voltage at the time of power-on is built in the insulating substrate, so that the setting can be miniaturized and the cost can be reduced. In addition, even in a display system equipped with a standby mode, it is possible to reduce the occurrence of flickers by setting a rapid charging / discharging common voltage 0 (: the starting circuit of the coupling capacitor for the offset) in response to the switching of the standby signal. By mounting such a startup circuit on an insulated 89410.doc 21 200424999 substrate, it is possible to realize the miniaturization and low cost of a setting with a low power consumption mode. [Brief description of the drawings] FIG. 1 is a display device related to the present invention Block diagram of the overall structure. Figure 2 (a) (b) is the time allocation table of the ○ N_ sequence and 〇__ sequence of the display device. Figure 3 (A) (B) is the ON of the display device with standby mode -Sequence and OFF_sequence time allocation table. Fig. 4 is a circuit diagram of an embodiment of a startup circuit mounted on the display device of Fig. 1. Fig. 5 is a time allocation table of the on-sequence of the startup circuit shown in Fig. 4. Fig. 6 is The time allocation table of the startup circuit 0FF_ sequence shown in Fig. 4. Fig. 7 is a circuit diagram of an embodiment of the startup circuit corresponding to the standby mode. Fig. 8 is the time allocation table of the startup circuit ON_ sequence shown in Fig. 7. 9 is obvious Time distribution table for the off-sequence of the start-up circuit in Figure 7. [Description of the main component symbols] 0 Display device 1 Insulating substrate 2 Display area 3 Vertical driver 4 Horizontal driver 5 COM driver 6 CS driver 7 > 7a DC / DC converter 89410.doc -22- 200424999 8 Interface 9… Timing signal generator 10 Analog voltage signal generator 11 Flexible printed cable (FPC) 51 Bias circuit 52 Start circuit 512 Buffer (BUF) 514 Non-NAND NAND 515 converter 516, 517 Buffer (BUF) 520-bit quasi-phase shifter 530 Common electrode connection pad G Gate line S Signal line R1, R2 Resistor R3 Variable resistor Δ V Bias voltage Cl Coupling capacitor L / S Level phase shifter LC liquid crystal element CS auxiliary capacitor TET thin film transistor COM common electrode VDD supply voltage on the positive side 89410.doc -23- 200424999 vss supply voltage on the negative side MCK… master timing RST reset signal PCI display permission signal STB standby signal SW1, SW2, SW3 and SW4 SIG signal potential VCOM common voltage HSYNC horizontal synchronization signal VSYNC vertical synchronization signal DATA Display data VCOMO node 89410.doc 24-