JP2008107855A - Display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a power saving effect of a display apparatus in standby mode. <P>SOLUTION: The display apparatus 0 consists of a panel formed integral with a display area 2 and a peripheral circuit part for driving the area on an insulating substrate 1. The circuit part can be changed over to/from the operating mode from/to the standby mode according to switching between a normal power consumption state and a low power consumption state on an electronic apparatus main body side. In the operating mode, the display apparatus operates to drive the display area to perform display by receiving power voltage supply from the electronic apparatus main body side. In the standby mode, the display apparatus is provided with a standby control means for suppressing the power consumption by halting the drive of the display area 2 to make the circuit inactive while receiving the power voltage supply from the electronic apparatus main body side. The standby control means carries out a control sequence to suppress charge/discharge produced within the circuit part at least a clock supplied to the peripheral circuit part in the process of the inactivation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state. More specifically, the present invention relates to a power saving technique for a display device that enters a standby mode under a low power consumption state.

  A flat panel such as an active matrix liquid crystal panel is often used as a display component of an electronic device. In the active matrix liquid crystal panel, a display region and a peripheral circuit unit for driving the display region are integrally formed on an insulating substrate, thereby forming a system-on-chip display (system display).

JP 7-271323 A

  Small electronic devices such as mobile phone terminals and PDAs have been developed that can switch between a normal power consumption state and a low power consumption state. When the electronic device main body side (set side) is in a low power consumption state, a technique for performing so-called partial mode display is known as a response to the low power consumption state on the display device side (system display side). For example, a liquid crystal panel incorporated in a mobile phone terminal performs a so-called “standby display” in a low power consumption state. That is, only necessary minimum information is displayed (partial mode display) to save power. However, in this partial mode, since the display device is substantially in an operating state, a power saving effect cannot be expected so much. As another countermeasure when the set side is in a low power consumption state, a method of cutting power supply to the display device after performing a preparation process (off sequence) for shutting off the power on the display device side is taken. In applications where it is required to suppress power consumption on the display device side (system display side), a method of shutting off this power supply is adopted. However, in this case, a large-capacity power switch is required to cut off the power supply from the set side to the system display side. For this reason, disadvantages such as an increase in set size and an increase in cost due to an increase in the number of parts occur.

  In recent years, a technology for switching a display device between an operation mode and a standby mode (standby mode) according to switching between a normal power consumption state and a low power consumption state on the electronic device main body side has been developed. is there. In the standby mode, the display of the system display is stopped while the power supply voltage is supplied from the set side, and the peripheral circuit portion included in the system display is deactivated to suppress the power consumption of the panel. In this standby mode, active power consumption on the system display side is suppressed while power supply from the set side to the system display side is kept active. This eliminates the need for a large-capacity switch for cutting off the power supply, and has advantages in terms of set size and cost. However, since the conventional standby mode has insufficient means for suppressing the active power consumption on the display device side, a sufficient power saving effect has not been achieved in the standby mode, which is a problem to be solved.

  In view of the above-described problems of the related art, an object of the present invention is to improve the power saving effect of a display device in a standby mode. The following measures were taken in order to achieve this purpose. That is, it is used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state, and from a panel in which a display region and a peripheral circuit portion for driving the display region are integrally formed on an insulating substrate. The circuit unit can be switched between an operation mode and a standby mode in accordance with switching between a normal power consumption state and a low power consumption state on the electronic device main body side. The display area operates in response to the supply of power supply voltage from the side, drives the display area to perform a desired display, and remains in a state in which the supply of power supply voltage is received from the main body side of the electronic device in the standby mode. And a standby control means for suppressing the power consumption of the panel by deactivating the circuit section. The standby control means executes a control sequence that stops at least a clock supplied to the circuit unit during the inactivation process and suppresses charge / discharge generated in the circuit unit.

  For example, the circuit unit includes a DC / DC converter that converts a primary power supply voltage supplied from the electronic device main body into a secondary power supply voltage according to the specifications of the panel, and the standby control unit is inactivated In this process, the clock supplied to the DC / DC converter is stopped, and a control sequence for suppressing charge / discharge generated in the DC / DC converter is executed.

  According to the present invention, the standby control means is distributed in each block of the circuit unit arranged around the system display. This standby control means executes a predetermined control sequence in response to a standby command from the set side, inactivates each part of the peripheral circuit of the system display, and suppresses power consumption of the panel. During this inactivation process, the standby control means stops the clock supplied to each part of the peripheral circuit of the system display in particular, and suppresses charging / discharging in the circuit part. Reduced. In this way, the standby control means executes a predetermined deactivation control sequence in response to a standby command from the set side, so that the supercurrent and the through current flowing in the peripheral circuit section of the system display are sequentially sequential as the entire system. It is to suppress.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, the display device 0 is integrated on an insulating substrate 1 made of glass or the like. A display region 2 is formed at the center of the insulating substrate 1, and peripheral circuit portions are also integrally formed so as to surround it. A connection terminal is formed on the upper side of the rectangular insulating substrate 1 and is connected to the electronic device main body side (set side) via a flexible printed cable (FPC) 11. The FPC 11 is a flat cable having a single layer structure in which a plurality of wirings are arranged in a plane.

  The display region 2 has a matrix configuration in which row-like gate lines G1 to Gm and column-like signal lines S1 to Sn are arranged to cross each other. Pixels are formed at the intersections of the gate lines G and the signal lines S. In this embodiment, each pixel includes a liquid crystal element LC, an auxiliary capacitor CS, and a thin film transistor TFT. The liquid crystal element LC includes a pixel electrode, a common electrode (COM) facing the pixel electrode, and a liquid crystal (electro-optical material) held between the pixel electrode and the common electrode (COM). The gate electrode of the TFT is connected to the gate line G, the source electrode is connected to the signal line S, and the drain electrode is connected to the pixel electrode of the liquid crystal element LC. The auxiliary capacitor CS is connected between the drain electrode of the TFT and the auxiliary capacitor line. The TFT is turned on by the selection pulse supplied from the gate line G, and the signal voltage supplied from the signal line S is written to the pixel electrode of the corresponding liquid crystal element LC. The auxiliary capacitor CS holds the signal voltage for one frame or one field.

  The liquid crystal element LC is generally AC driven. That is, the polarity of the signal voltage written to the liquid crystal element LC via the signal line S is periodically reversed. In accordance with this, it is necessary to periodically reverse the polarity of the common voltage VCOM applied to the common electrode COM of the liquid crystal element LC. Here, the liquid crystal element LC and the TFT that performs switching driving thereof have asymmetry with respect to polarity. For this reason, if the center level is matched between the pixel electrode side and the common electrode side, asymmetry with respect to the polarity appears, and image quality deterioration such as image sticking occurs. As a countermeasure, the common voltage is offset by a predetermined voltage with respect to the signal voltage to cancel the asymmetry related to the polarity. The auxiliary capacitor CS also needs to be AC-operated in accordance with the AC driving of the liquid crystal element LC. For this reason, it is necessary to apply a voltage whose polarity is inverted in the same predetermined cycle to the auxiliary capacitor line commonly connected to each auxiliary capacitor CS.

  Peripheral circuit portions are integrated and formed on the four sides of the upper, lower, left and right sides surrounding the display area 2 described above. In the case of the present embodiment, the peripheral circuit section includes an interface 8 including a vertical driver 3, a horizontal driver 4, a COM driver 5, a CS driver 6, a DC / DC converter 7, a DC / DC converter 7a, and a level shifter (L / S). , A timing generator 9, an analog voltage generator 10, and the like. However, the present invention is not limited to this configuration, and necessary circuits are appropriately added according to the specifications of the display device (system display) 0, while unnecessary circuits are deleted. For example, in some cases, a driver for generating a signal voltage level used for complete white display or complete black display separately from the signal voltage may be incorporated.

  The vertical driver 3 is connected to each of the gate lines G1 to Gm, and supplies a selection pulse line by line. The horizontal driver 4 is formed in a pair of upper and lower sides, is connected to both ends of each signal line S1 to Sn, and supplies a predetermined signal voltage from both sides simultaneously. This signal voltage corresponds to display data (image information) sent from the set side via the FPC 11.

  The common driver (COM driver) 5 applies a common voltage VCOM whose polarity is periodically inverted to a common electrode common to each liquid crystal element LC. The COM driver 5 is attached with an offset circuit and a start circuit (COM starter). The offset circuit adjusts the offset level of the common voltage generated by the common driver 5. The start circuit (COM starter) charges the offset circuit when the panel is started, and quickly starts application of the common voltage VCOM. The CS driver 6 applies a voltage whose polarity is periodically inverted to the auxiliary capacitor line common to the auxiliary capacitors CS.

  The DC / DC converter 7 converts the primary power supply voltage supplied from the electronic device main body via the FPC 11 into a secondary power supply voltage according to the specifications of the panel (display device 0). In particular, the DC / DC converter 7 is used for conversion of the positive power supply voltage VDD. On the other hand, the DC / DC converter 7a is used for conversion of the negative power supply voltage VSS.

  The interface 8 including L / S accepts control signals such as a clock signal, a synchronization signal, and an image signal supplied from the set side via the FPC 11. The level shifter L / S shifts the level of the control signal (external control signal) sent from the set side, and generates a control signal (internal control signal) that conforms to the circuit operation specifications inside the display device. In this specification, when it is necessary to distinguish between the external control signal and the internal control signal, the number (3) is added in the case of the external control signal after the symbol indicating the type of each control signal. The number (5) may be attached. The timing generator 9 processes a clock signal and a synchronization signal sent from the interface 8 including the L / S, and generates a clock signal necessary for timing control of each part of the circuit. The analog voltage generator 10 supplies a plurality of levels of analog voltages corresponding to gradations to the horizontal driver 4 in advance. The horizontal driver 4 writes in the liquid crystal element LC an analog signal voltage that is grayscaled according to image information sent from the main body side of the electronic device.

  FIG. 2 is a timing chart showing a control sequence on the set side with respect to the display device side, where (A) represents an on sequence and (B) represents an off sequence. However, it represents a normal case where there is no sequence control related to the standby mode (standby mode). A master clock MCK, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, display data DATA, a reset signal RST, a display permission signal PCI, and a power supply voltage VDD are input according to a predetermined sequence from the set side to the display side. In the on sequence (A) in which the display side is raised from the set side, VDD first rises and then MCK, HSYNC, and VSYNC become active. After the time ton1 has elapsed, the reset signal RST switches from low to high, and the display circuit section is initialized. Thereafter, after the time ton2 has elapsed, DATA is switched from low to active, and the display permission signal PCI is switched from low to high. As a result, an image is displayed on the display area of the display.

  In the off sequence (B) in which the display is lowered from the set side, first, DATA is switched from active to low, and the display permission signal PCI is switched from high to low. After the time toff1 has elapsed, the reset signal RST switches from high to low to reset the internal state of the display circuit. After the time toff2 has elapsed, the supply of MCK, HSYNC, and VSYNC is cut off, and finally VDD is lowered. As a result, VDD becomes a ground potential or a floating potential. However, in this case, a large capacity switch for disconnecting VDD is required on the set side, and the number of parts increases.

  FIG. 3 is a timing chart showing an on sequence and an off sequence employing a standby mode (standby mode). For easy understanding, the same reference numerals are used for the portions corresponding to the normal on sequence and off sequence shown in FIG. The set side can be switched between a normal power consumption state and a low power consumption state. In accordance with this, it is necessary to switch the display side between the operation mode and the standby mode (standby mode), and for this reason, the set side inputs a standby signal STB to the display side.

  In the on sequence (A), first, the standby signal STB rises from low to high, and the display returns from the standby mode to the operation mode. MCK, HSYNC, and VSYNC become active at the rising edge of STB. However, VDD is always supplied regardless of STB. After the time ton1 has elapsed, RST changes from low to high, and the circuit state of the display is initialized. After time ton2 elapses, DATA becomes active and PCI switches to high, and an image is displayed in the display area.

  In the off sequence (B), first, DATA and PCI are inactive. After elapse of toff1, RST changes from high to low and the internal circuit of the display is reset. After toff2, STB changes from high to low, and MCK, HSYNC, and VSYNC become inactive. When STB changes from high to low, the display side shifts from the operation mode to the standby mode. On the other hand, VDD is always maintained at the power supply voltage despite the transition to the standby mode.

  In the system adopting the standby mode as described above, the necessity of a large-capacity switch is eliminated by deactivating the drive circuit system on the display side according to the STB while keeping VDD active. The signal STB used for the standby mode control may be a control signal that is input independently from the set side as shown in the figure, but other external signals supplied from the set side are internally logically displayed on the display side. It can also be generated by processing. In the off sequence, the internal circuit of the display is logically reset by RST, and then STB falls. At this time, the master clock MCK and the synchronization signals HSYNC and VSYNC supplied from the set side are fixed at a constant potential from the active state. In the illustrated example, it is fixed at the low level (GND level), but may be fixed at the VDD level depending on circumstances.

  The display device that has shifted to the standby mode in response to the fall of the standby signal STB stops driving the display area while maintaining the supply of the power supply voltage VDD from the main body side of the electronic device, and disables the circuit portion. A standby control unit is provided that is activated to suppress power consumption of the panel. This standby control means is distributed in each block of the circuit section, and executes a control sequence for inactivation in response to the fall of the STB for each circuit block. Hereinafter, a control sequence for inactivation will be specifically described for each circuit block.

  FIG. 4 is a circuit diagram showing a specific configuration example of the DC / DC converter 7 adapted to the standby mode. As shown, the DC / DC converter 7 includes an AND element (AND) 701, a delay element (DELAY) 702, a multistage buffer 703, an external flying capacitor 704, clamping transistors 705 to 707, an output transistor 708, The circuit includes an internal capacitor 709, a level shifter (L / S) 710, an AND element 711, a buffer 712, an external bypass capacitor 720, a termination resistor 721, and the like. The DC / DC converter 7 includes a built-in circuit mounted on an insulating substrate and an external component connected to the built-in circuit via a connection terminal. In the illustrated example, the flying capacitor 704 and the bypass capacitor 720 are external components, and all the remaining circuit elements are built on the insulating substrate. The built-in circuit portion is composed of a TFT formed by the same process as the switching thin film transistor TFT formed in the display region.

  The DC / DC converter 7 converts the primary power supply voltage VDD1 supplied from the set side into a secondary power supply voltage VDD2 according to the specifications of the panel. Therefore, a clock signal for pumping (pumping pulse) is supplied to the multistage buffer 703 via the AND element 701 and the delay element 702 for phase adjustment. The primary side of the flying capacitor 704 is pumped to VDD1 by the pumping pulse through the multistage buffer 703. A clamping circuit composed of TFTs 705, 706, and 707 is connected to the secondary side of the flying capacitor 704, and clamps the output voltage of the flying capacitor 704 to VDD2. In this embodiment, clamping is performed up to VDD2 = 2 × VDD1. The output transistor 708 takes out the crest portion of the rectangular wave clamped to VDD2 and outputs a DC secondary power supply voltage VDD2. At that time, the external bypass capacitor (decoupling capacitor) 720 is smoothed by removing ripple noise contained in the secondary power supply voltage VDD2. The clock signal that has passed through the delay element 702 is applied to the drains of the clamping transistors 705 and 706 via the internal capacitor 709 and to the gate of the output transistor 708. The clock signal that has passed through the AND element 701 is shaped into a clamping pulse CLP by the level shifter 710, the AND element 711, and the buffer 712, and then applied to the gates of the transistors 705 and 706. If necessary, a control signal is input via an AND element 711 to reset the DC / DC converter 7. In this manner, the DC / DC converter 7 includes a flying capacitor 704 that is pumped to the primary power supply voltage VDD1 by a pumping pulse, and a clamp circuit that clamps the pumped flying capacitor 704 and extracts the secondary power supply voltage VDD2. 705-708) and a bypass capacitor 720 for removing noise included in the secondary power supply voltage VDD.

  In order to realize the standby mode, the DC / DC converter 7 uses an AND element 701 as standby control means, and accepts the STB signal. When the STB signal is switched from high to low to instruct the transition to the standby mode, the AND element 701 is closed and the input of the clock signal (pumping pulse) is cut off. The pumping pulse is stopped and charging / discharging to the flying capacitor 704 is stopped, thereby reducing power consumption. When the standby mode is entered, the output terminal of the DC / DC converter 7 is fixed to a predetermined potential such as VDD1 or GND by the termination resistor 721. As a result, the power supply line in the system display is prevented from floating. In the illustrated example, the termination resistor 721 is built-in, but may be an external component.

  FIG. 5 is a circuit diagram showing an embodiment of the DC / DC converter 7a. For easy understanding, portions corresponding to the DC / DC converter 7 shown in FIG. 4 are denoted by corresponding reference numerals. The DC / DC converter 7 in FIG. 4 converts the primary power supply voltage VDD1 on the positive side into the secondary power supply voltage VDD2 that is doubled, whereas the DC / DC converter 7a converts the negative power supply voltage VSS1 to an absolute value. Thus, the negative secondary power supply voltage VSS2 is doubled.

  The DC / DC converter 7a inputs the STB signal to the AND element 701 via the level shifter 730 as standby control means. When the STB signal falls from high to low to instruct the transition to the standby mode, the AND element 701 is closed to cut off the clock signal (pumping pulse), thereby stopping charging and discharging to the flying capacitor 704 and consuming Reduce power. The output terminal of the DC / DC converter 7a is fixed to a constant potential of GND or VDD1 by a terminating resistor 721.

  FIG. 6 is a block diagram illustrating a configuration example of the level shifter 8 included in the input interface of the display device. As shown in the figure, the level shifter 8 has a level shift amplifier 81 and a buffer amplifier 82 connected in series. In the operating state, the external input signal IN is level-shifted and converted to an output signal OUT that conforms to the internal specifications of the display. In the standby mode, as described above, the output of the DC / DC converter is fixed at GND or VDD1. Therefore, the power supply lines of the amplifiers 81 and 82 of the level shifter 8 are also fixed to GND or VDD1. In the standby mode, since the input signal IN is fixed at the GND level or the VDD1 level, no internal charge / discharge current flows.

  FIG. 7 is a block diagram showing a configuration example of the timing generator 9. As shown in the figure, the timing generator 9 processes various input signals to generate output signals necessary for timing control inside the system display. Input signals include PCI, STB, RST, VD, MCK, HD, and the like. VD is an internal signal corresponding to the external VSYNC. HD is an internal signal corresponding to the external HSYNC. The timing generator 9 is divided into a horizontal drive timing generator (TGforH) 91 and a vertical drive timing generator (TGforV) 92. The horizontal drive timing generator 91 processes the above-described input signal and generates an output signal and the like mainly necessary for timing control of the horizontal driver 4. This includes a horizontal clock signal HCK and a horizontal start signal HST. A vertical clock signal VCK is also output. On the other hand, the timing generator 92 for vertical driving mainly outputs timing signals and the like necessary for operation control of the vertical driver 3. This includes a vertical start pulse VST and a frame signal FRP that defines a frame period.

  As described above, in the standby mode, the output of the DC / DC converter is at the GND level or the VDD1 level. Therefore, the power supply line of the timing generator 9 is also fixed to the GND level or the VDD1 level. Various input signals are also in a fixed input state of GND level or VDD1 level. Therefore, the timing generator 9 does not operate and no charge / discharge current flows.

  FIG. 8 is a circuit diagram showing an embodiment of the vertical driver 3. As illustrated, the vertical driver 3 has a shift register configuration in which a plurality of units 301 to 380 are connected in multiple stages. In this example, 80 units are connected in multiple stages, and a total of 160 gate lines (Gate 1 to Gate 160) are driven sequentially, with 2 lines per stage. Specifically, the vertical driver 3 outputs a selection pulse to each gate line by sequentially transferring the vertical start pulse VST in synchronization with the vertical clock VCK.

  In the standby state, the timing generator is not operating. Therefore, the control signal input to the vertical driver 3 is in a fixed input state with the GND level or the VDD1 level. Therefore, the vertical driver 3 does not operate and no charge / discharge current flows to the gate line, so that power consumption is reduced. Although not shown, since the horizontal driver 4 does not operate in the same manner, the charge / discharge current to the signal line does not flow and the power consumption is reduced.

  FIG. 9 is a circuit diagram showing an embodiment of the analog voltage generator 10. As shown in the figure, the analog voltage generator 10 includes various gate elements 101 to 107, a pair of switching circuits 110 and 111, and a ladder resistor 115. The ladder resistor 115 divides the power supply voltage by resistance to generate a plurality of levels of output analog potentials V1-V30. For example, when the display data is divided into 32 gradations in a 5-bit configuration, the analog voltage generator 10 outputs analog potentials V1 to V30 corresponding to the intermediate 30 levels in addition to the two levels at both ends. As described above, the liquid crystal element is AC driven. Accordingly, it is necessary to reverse the polarity of the analog potential output from the analog voltage generator 10 in a predetermined cycle. For this purpose, a pair of switching circuits 110 and 111 are connected to both ends of the ladder resistor 115. These switching circuits 110 and 111 are controlled by an input signal FRP via gate elements 101 to 107. In the standby mode, STB is applied as an input signal.

  The power supply potential of the logic circuit portion of the analog voltage generator 10 is always fixed to VDD1. In the standby mode, the input signals FRP and STB are GND level fixed inputs. In the normal operation mode, the high level and the low level of FRP are inverted in the frame period. In the normal operation mode, the switches a1 and b2 or the switches a2 and b1 in the switching circuits 110 and 111 are simultaneously turned on in response to FRP, so that the ladder resistor 115 divides the VDD1 potential and the analog output voltages V1 to V30 are Generate. In the standby mode, the switches a1 and b1 (or the switches a2 and b2) are simultaneously turned on in the switching circuits 110 and 111. As a result, the potentials at both ends of the series ladder resistor 115 are the same, and no direct current flows, so that power consumption can be reduced.

  FIG. 10 is a circuit diagram showing an embodiment of the CS driver. The CS driver 6 includes an inverter 601, a buffer 602, a buffer 603, and a switching circuit 604 including a pair of switches. Under the operation mode, a pair of switches included in the switching circuit 604 are alternately turned on in response to the input signal FRP, and an output signal whose polarity is inverted in a frame period is supplied to the auxiliary capacitance line CS. In the standby mode, the input signal FRP is fixed at the GND level. As a result, the output terminal of the CS driver 6 is fixed, the charging / discharging current to the auxiliary capacitance line CS does not flow, and the power consumption is reduced.

  FIG. 11 is a circuit diagram showing an embodiment of the COM driver 5. The COM driver 5 includes an inverter 501, an AND element 502, a buffer 503, an AND element 504, a buffer 505, and a switching circuit 506. Similar to the CS driver 6 described above, the COM driver 5 supplies an output signal VCOMO whose polarity is inverted in a frame period to the common electrode in response to the input signal FRP in the operation mode. Note that the COM driver 5 of this embodiment is configured to perform a logic reset in response to the internal reset signal RST5.

  In the standby mode, the power supply potential of the COM driver 5 is at the GND or VDD1 level due to the aforementioned stop of the DC / DC converter. Further, due to the stop of the timing generator, the input signal FRP is also in a fixed input state at the GND level or the VDD1 level. As a result, the output signal VCOMO becomes a fixed potential, the charge / discharge current to the common electrode does not flow, and the power consumption can be reduced.

  Finally, FIG. 12 is a circuit diagram showing a specific configuration example of the offset circuit 51 and the start circuit 52 associated with the COM driver 5. As described above, the common driver 5 applies the common voltage VCOM to the common electrode. The offset circuit 51 includes a coupling capacitor C1 that generates a predetermined offset voltage ΔV in order to adjust the level of the common voltage relative to the signal voltage. The start circuit 52 precharges the coupling capacitor C1 of the offset circuit 51 to the offset voltage ΔV when the power supply voltage VDD rises, and discharges the coupling capacitor C1 when the power supply voltage VDD falls. As illustrated, the COM driver 5, the offset circuit 51, and the start circuit 52 are mounted on the common insulating substrate 1 except for the coupling capacitor C1 and the variable resistor R3.

  The offset circuit 51 includes a transistor switch SW4 and a voltage level adjusting variable resistor R3 in addition to the above-described coupling capacitor C1. The resistor R3 is an external component similar to the coupling capacitor C1. The transistor switch SW4 is formed on the insulating substrate 1. The offset-processed common voltage VCOMI input from the coupling capacitor C1 outside the insulating substrate 1 is connected to the COM pad 530 connected to the common electrode inside the system display by internal wiring.

  The start circuit 52 includes a level shifter 511 to which a standby signal STB is input, an inverter 512 to which an internal reset signal RST5 is input, an inverter 513 to which an external reset signal RST3 is input, a NAND element NAND 514, an inverter 515, a buffer (BUF) 516, Logic circuits such as a buffer 517 and a level shifter 520 are included. Further, switches SW1, SW2, SW3 and SW5 constituted by thin film transistors are included. In addition, it includes a pair of resistors R1, R2 connected in series between the positive power supply voltage VDD and the negative power supply voltage VSS. The connection point of resistors R1 and R2 is represented by node A.

  The on sequence and off sequence of the start circuit 52 will be described with reference to FIG. First, in the on sequence for returning from the standby mode to the operation mode, the STB signal rises from low to high as the first step. As a result, the switches SW1, SW2, SW3, and SW4 become conductive. The power supply potential VDD is resistance-divided by the series resistors R1 and R2, and a desired intermediate potential is obtained at the node A. This intermediate potential is equal to the required offset potential ΔV. Since SW3 and SW4 are in a conductive state, the node VCOMO also has the same potential as the node A, and the coupling capacitor C1 is precharged. The ratio of the series resistors R1 and R2 is set so that the potential difference between the node A and the node VCOMO is ΔV. Thereafter, as a second stage, the reset signals RST3 and RST5 rise and the COM driver 5 becomes active. At the same time, the switches SW1, SW2, SW3 and SW4 are turned off. On the other hand, the switch SW5 becomes conductive, the node VCOMWR becomes VDD, and a current flows through the variable resistor R3. Since the coupling capacitor C1 is sufficiently charged in the first first stage, the output of the COM driver 5 is coupled, and a potential DC-shifted by ΔV is output to the node VCOMI. The variable resistor R3 is set so that the potential of VCOMI is shifted by exactly ΔV. Thereafter, as a third stage, a display start signal rises and an image is displayed in the display area.

  Next, an off sequence for shifting from the operation mode to the standby mode will be described. First, as a first step, the display command PCI from the set side falls, and the image is erased from the display area. Subsequently, as a second stage, the reset signals RST3 and RST5 fall. As a result, the switches SW1, SW2, SW3, and SW4 become conductive. Conversely, SW5 is turned off. As a result, no current flows through the external variable resistor R3, and a desired power saving effect is obtained. At the same time, since the COM driver 5 in the insulating substrate 1 becomes inactive, a power saving effect can be obtained. When the switches SW1 and SW2 are turned on, the power supply potential VDD becomes a desired intermediate potential at the node A by the series resistors R1 and R2. At this time, since SW4 is also in a conductive state, the node VCOMI is at the GND level. As a result, the coupling capacitor C1 is discharged. Finally, as the third stage, the STB signal falls, and the switches SW1, SW2, SW3, and SW4 are turned off. As a result, the series resistors R1 and R2 are disconnected from the positive power supply line VDD and the negative power supply line VSS, and no unnecessary current flows. Therefore, a desired power saving effect can be obtained.

  As described above, according to the present invention, the display is stopped while the power supply voltage is supplied from the set side in the standby mode, and the power consumption of the panel is suppressed by inactivating the circuit section in the panel. is doing. Thereby, power consumption can be significantly reduced as compared with the conventional partial mode function. Further, it is not necessary to provide a switch for shutting off the power supply on the set side, and the size and cost of the set can be reduced by reducing the number of parts. In particular, in the present invention, a control sequence for cutting off the direct current component flowing in the resistance element included in the circuit unit during the inactivation process is executed. Further, a control sequence for stopping charging / discharging generated in the circuit unit by stopping the clock supplied to the circuit unit during the inactivation process is executed. By executing the standby transition sequence systematically in this way, a significant power saving effect can be expected compared to the conventional case.

It is a block diagram which shows the whole structure of the display apparatus which concerns on this invention. It is a timing chart which shows the ON sequence and OFF sequence of a display apparatus. It is a timing chart which shows the on sequence and off sequence of a display apparatus provided with standby mode. It is a circuit diagram which shows the Example of the DC / DC converter contained in a display apparatus. It is a circuit diagram which shows the Example of the DC / DC converter contained in a display apparatus. It is a block diagram which shows the Example of the level shifter contained in a display apparatus. It is a block diagram which shows the Example of the timing generator contained in a display apparatus. It is a circuit diagram which shows the Example of the vertical driver contained in a display apparatus. It is a circuit diagram which shows the Example of the analog voltage generator contained in a display apparatus. It is a circuit diagram which shows the Example of CS driver contained in a display apparatus. It is a circuit diagram which shows the Example of the common driver contained in a display apparatus. It is a circuit diagram which shows the offset circuit and start circuit for common drivers which are included in a display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 0 ... Display apparatus, 1 ... Insulating substrate, 2 ... Display area, 3 ... Vertical driver, 4 ... Horizontal driver, 5 ... COM driver, 6 ... CS driver, 7 ... DC / DC converter, 8 ... Interface including level shifter, 9 ... Timing generator, 10 ... Analog voltage generator, 11 ... FPC

Claims (2)

A display that is used as a display component of an electronic device that can be switched between a normal power consumption state and a low power consumption state, and includes a panel in which a display region and a peripheral circuit unit that drives the display region are integrally formed on an insulating substrate. A device,
The circuit unit can be switched between an operation mode and a standby mode according to switching between a normal power consumption state and a low power consumption state on the electronic device main body side,
In the operation mode, the power supply voltage is supplied from the main body side of the electronic device, and the display area is driven to perform a desired display.
In standby mode, standby control means for stopping driving of the display area while maintaining the supply of power supply voltage from the main body side of the electronic device and deactivating the circuit unit to suppress power consumption of the panel With
The display apparatus according to claim 1, wherein the standby control unit stops a clock supplied to at least the circuit unit during the inactivation process, and executes a control sequence for suppressing charge / discharge generated in the circuit unit. The circuit unit includes a DC / DC converter that converts a primary power supply voltage supplied from the electronic device main body into a secondary power supply voltage according to the specifications of the panel.
The standby control means executes a control sequence for stopping charging and discharging generated in the DC / DC converter by stopping a clock supplied to the DC / DC converter in the process of inactivation. Item 4. The display device according to Item 1.

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