JP4062106B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device including a pixel electrode and a common electrode facing the pixel electrode. More specifically, the present invention relates to an improvement technique around a circuit that generates an AC common voltage applied to a common electrode.
[0002]
[Prior art]
2. Description of the Related Art Conventional flat display devices represented by active matrix liquid crystal panels are widely used as display parts for electronic devices. An active matrix display panel operates in accordance with display data and power supply voltage supplied from the main body side of an electronic device, and a display region and a peripheral circuit unit for driving the display region are integrally formed on an insulating substrate. The so-called system display configuration is generally used. In this case, the display region includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optical material such as liquid crystal held between the two. On the other hand, a peripheral circuit portion surrounding the display area includes a driver that writes a signal voltage on the pixel electrode side in accordance with display data, and a common driver that applies a common voltage to the common electrode side. A display device having such a configuration is disclosed in Patent Document 1.
[0003]
[Patent Document 1]
JP 2000-193941 A
[0004]
When liquid crystal is used as the electro-optical material, AC driving is generally employed to prevent deterioration of the liquid crystal material. The polarity of the signal voltage applied to the pixel electrode side is inverted every predetermined period, and the common voltage is also inverted accordingly. Therefore, the conventional common driver inverts and generates the common voltage at a predetermined cycle. By the way, active elements such as liquid crystal materials and thin film transistors for driving the liquid crystal material have asymmetry with respect to polarity. Accordingly, when the signal voltage and the center potential of the common voltage are completely matched, asymmetry appears and image deterioration such as image sticking or flicker becomes conspicuous. Therefore, the conventional display device is provided with an offset circuit including a coupling capacitor that generates a predetermined offset voltage in order to adjust the level of the common voltage with respect to the signal voltage, in addition to the common driver. Image offset and flicker can be prevented by setting the offset voltage so as to cancel the asymmetry related to the polarity of the liquid crystal material and the active element.
[0005]
[Problems to be solved by the invention]
When the display device is turned on, it is necessary to charge the coupling capacitor included in the offset circuit to a predetermined offset voltage. When charging is completed, a predetermined offset voltage is added to the common voltage output from the common driver, so that a regular image can be displayed. However, in the transition period from when the power is turned on to when the coupling capacitor is completely charged, the level of the common voltage is not stable, and flicker may be seen. In order to prevent this, a start circuit for rapidly charging the coupling capacitor when the power is turned on has been conventionally used. This start circuit is also used when discharging the coupling capacitor when the power is shut off.
[0006]
However, the conventional common driver start circuit (rapid charge / discharge circuit) has been realized by a drive system outside the display device having a system display configuration. In this case, there are problems that the number of parts is increased and the drive system scale outside the display device is increased.
[0007]
[Means for Solving the Problems]
In view of the above-described problems of the conventional technology, an object of the present invention is to mount a start circuit for a common driver in a display device having a system display configuration. The following measures were taken in order to achieve this purpose. That is, it is used as a display component of an electronic device and operates in accordance with display data and a power supply voltage supplied from the main body side of the electronic device, and the display area and a peripheral circuit unit that drives the display region are integrated on the insulating substrate. A display device comprising a panel integrated and formed, wherein the display area includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optic material held between the pixel electrodes, Includes a driver for writing a signal voltage on the pixel electrode side according to display data, a common driver for applying a common voltage to the common electrode side, and a predetermined offset voltage for adjusting the level of the common voltage with respect to the signal voltage. Offset circuit with a coupling capacitor to be generated and when the power supply voltage is raised , Before the common voltage is applied to the coupling capacitor from the common driver, Precharge the offset circuit coupling capacitor to the offset voltage You And a start circuit for discharging the coupling capacitor when the power supply voltage falls. Specifically, the panel is composed of thin film transistors formed by the same process on a common insulating substrate, both in the display region and in the peripheral circuit portion that drives the display region, and the common driver, the offset circuit, The start circuit is mounted on the common insulating substrate except for the coupling capacitor. Preferably, the start circuit operates only when the power supply voltage is raised and when the power supply voltage is lowered, and is inactive during other times.
[0008]
The present invention is also used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state, operates according to display data and a power supply voltage supplied from the main body side of the electronic device, and has a display area. And a peripheral circuit unit for driving the same are integrally formed on an insulating substrate, and the panel switches between a normal power consumption state and a low power consumption state on the electronic device body side. It is possible to switch between the operation mode and the standby mode according to the operation mode. In the operation mode, the power supply voltage is supplied from the main body side of the electronic device, and the display area is driven to perform a desired display. In the state where the power supply voltage is supplied from the main body side of the electronic device, the driving of the display area is stopped and the circuit portion is inactivated to suppress the power consumption of the panel. The display area includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optical material held between the pixel electrodes, and the circuit unit includes an electronic device. A driver for writing a signal voltage to the pixel electrode side in accordance with display data sent from the main body side, a common driver for applying a common voltage to the common electrode side, and a predetermined voltage level for adjusting the level of the common voltage with respect to the signal voltage Offset circuit with a coupling capacitor that generates an offset voltage and when returning from standby mode to operating mode , Before the common voltage is applied to the coupling capacitor from the common driver, Precharge the offset circuit coupling capacitor to the offset voltage You And a start circuit for discharging the coupling capacitor when the operation mode is shifted to the standby mode. Specifically, the panel is composed of thin film transistors formed in the same process on a common insulating substrate, together with the display region and the peripheral circuit portion that drives the display region, and the common driver, the offset circuit, The start circuit is mounted on the common insulating substrate except for the coupling capacitor. Preferably, the start circuit operates only when returning from the standby mode to the operation mode and when shifting from the operation mode to the standby mode, and is inactive during other times.
[0009]
According to the present invention, a system for rapidly charging a common voltage offset coupling capacitor applied to a common electrode of a display device to a desired offset potential when the power is turned on is mounted in the liquid crystal display device. In other words, a display panel having a system display configuration includes a thin film transistor formed on a common insulating substrate by the same process in both the display area and the peripheral circuit portion that drives the display area. The common driver, the offset circuit, and the start circuit belonging to the circuit unit are integrated and formed with a thin film transistor or the like on a common insulating substrate except for the coupling capacitor. In some cases, a system display that can be switched between a normal operation mode and a standby mode is used. At this time, when returning from the standby mode to the operation mode, it is necessary to rapidly charge the coupling capacitor for shifting the common voltage. A start circuit for this purpose can also be incorporated in the display device.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, the display device 0 is integrated on an insulating substrate 1 made of glass or the like. A display region 2 is formed at the center of the insulating substrate 1, and peripheral circuit portions are also integrally formed so as to surround it. A connection terminal is formed on the upper side of the rectangular insulating substrate 1 and is connected to the electronic device main body side (set side) via a flexible printed cable (FPC) 11. The FPC 11 is a flat cable having a single layer structure in which a plurality of wirings are arranged in a plane.
[0011]
The display region 2 has a matrix configuration in which row-like gate lines G1 to Gm and column-like signal lines S1 to Sn are arranged to cross each other. Pixels are formed at the intersections of the gate lines G and the signal lines S. In this embodiment, each pixel includes a liquid crystal element LC, an auxiliary capacitor CS, and a thin film transistor TFT. The liquid crystal element LC includes a pixel electrode, a common electrode (COM) facing the pixel electrode, and a liquid crystal (electro-optical material) held between the pixel electrode and the common electrode (COM). The gate electrode of the TFT is connected to the gate line G, the source electrode is connected to the signal line S, and the drain electrode is connected to the pixel electrode of the liquid crystal element LC. The auxiliary capacitor CS is connected between the drain electrode of the TFT and the auxiliary capacitor line. The TFT is turned on by the selection pulse supplied from the gate line G, and the signal voltage supplied from the signal line S is written to the pixel electrode of the corresponding liquid crystal element LC. The auxiliary capacitor CS holds the signal voltage for one frame or one field.
[0012]
The liquid crystal element LC is generally AC driven. That is, the polarity of the signal voltage written to the liquid crystal element LC via the signal line S is periodically reversed. In accordance with this, it is necessary to periodically reverse the polarity of the common voltage VCOM applied to the common electrode COM of the liquid crystal element LC. Here, the liquid crystal element LC and the TFT that performs switching driving thereof have asymmetry with respect to polarity. For this reason, if the center level is matched between the pixel electrode side and the common electrode side, asymmetry with respect to the polarity appears, and image quality deterioration such as image sticking occurs. As a countermeasure, the common voltage is offset by a predetermined voltage with respect to the signal voltage to cancel the asymmetry related to the polarity. The auxiliary capacitor CS also needs to be AC-operated in accordance with the AC driving of the liquid crystal element LC. For this reason, it is necessary to apply a voltage whose polarity is inverted in the same predetermined cycle to the auxiliary capacitor line commonly connected to each auxiliary capacitor CS.
[0013]
Peripheral circuit portions are integrated and formed on the four sides of the upper, lower, left and right sides surrounding the display area 2 described above. In the case of the present embodiment, the peripheral circuit section includes an interface 8 including a vertical driver 3, a horizontal driver 4, a COM driver 5, a CS driver 6, a DC / DC converter 7, a DC / DC converter 7a, and a level shifter (L / S). , A timing generator 9, an analog voltage generator 10, and the like. However, the present invention is not limited to this configuration, and necessary circuits are appropriately added according to the specifications of the display device (system display) 0, while unnecessary circuits are deleted. For example, in some cases, a driver for generating a signal voltage level used for complete white display or complete black display separately from the signal voltage may be incorporated.
[0014]
The vertical driver 3 is connected to each of the gate lines G1 to Gm, and supplies a selection pulse line by line. The horizontal driver 4 is formed in a pair of upper and lower sides, is connected to both ends of each signal line S1 to Sn, and supplies a predetermined signal voltage from both sides simultaneously. This signal voltage corresponds to display data (image information) sent from the set side via the FPC 11.
[0015]
The common driver (COM driver) 5 applies a common voltage VCOM whose polarity is periodically inverted to a common electrode common to each liquid crystal element LC. The COM driver 5 is attached with an offset circuit and a start circuit (COM starter). The offset circuit adjusts the offset level of the common voltage generated by the common driver 5. The start circuit (COM starter) charges the offset circuit when the panel is started, and quickly starts application of the common voltage VCOM. The CS driver 6 applies a voltage whose polarity is periodically inverted to the auxiliary capacitor line common to the auxiliary capacitors CS.
[0016]
The DC / DC converter 7 converts the primary power supply voltage supplied from the electronic device main body via the FPC 11 into a secondary power supply voltage according to the specifications of the panel (display device 0). In particular, the DC / DC converter 7 is used for conversion of the positive power supply voltage VDD. On the other hand, the DC / DC converter 7a is used for conversion of the negative power supply voltage VSS.
[0017]
The interface 8 including L / S accepts control signals such as a clock signal, a synchronization signal, and an image signal supplied from the set side via the FPC 11. The level shifter L / S shifts the level of the control signal (external control signal) sent from the set side, and generates a control signal (internal control signal) that conforms to the circuit operation specifications inside the display device. In this specification, when it is necessary to distinguish between the external control signal and the internal control signal, the number (3) is added in the case of the external control signal after the symbol indicating the type of each control signal. The number (5) may be attached. The timing generator 9 processes a clock signal and a synchronization signal sent from the interface 8 including the L / S, and generates a clock signal necessary for timing control of each part of the circuit. The analog voltage generator 10 supplies a plurality of levels of analog voltages corresponding to gradations to the horizontal driver 4 in advance. The horizontal driver 4 writes in the liquid crystal element LC an analog signal voltage that is grayscaled according to image information sent from the main body side of the electronic device.
[0018]
FIG. 2 is a timing chart showing a control sequence on the set side with respect to the display device side, where (A) represents an on sequence and (B) represents an off sequence. This represents a normal case where there is no sequence control related to the standby mode (standby mode). A master clock MCK, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, display data DATA, a reset signal RST, a display permission signal PCI, and a power supply voltage VDD are input according to a predetermined sequence from the set side to the display side. In the on sequence (A) in which the display side is raised from the set side, VDD first rises and then MCK, HSYNC, and VSYNC become active. After the time ton1 has elapsed, the reset signal RST switches from low to high, and the display circuit section is initialized. Thereafter, after the time ton2 has elapsed, DATA is switched from low to active, and the display permission signal PCI is switched from low to high. As a result, an image is displayed on the display area of the display.
[0019]
In the off sequence (B) in which the display is lowered from the set side, first, DATA is switched from active to low, and the display permission signal PCI is switched from high to low. After the time toff1 has elapsed, the reset signal RST switches from high to low to reset the internal state of the display circuit. After the time toff2 has elapsed, the supply of MCK, HSYNC, and VSYNC is cut off, and finally VDD is lowered. As a result, VDD becomes a ground potential or a floating potential.
[0020]
FIG. 3 is a timing chart showing an on sequence and an off sequence employing a standby mode (standby mode). For easy understanding, the same reference numerals are used for the portions corresponding to the normal on sequence and off sequence shown in FIG. The set side can be switched between a normal power consumption state and a low power consumption state. In accordance with this, it is necessary to switch the display side between the operation mode and the standby mode (standby mode), and for this reason, the set side inputs a standby signal STB to the display side.
[0021]
In the on sequence (A), first, the standby signal STB rises from low to high, and the display returns from the standby mode to the operation mode. MCK, HSYNC, and VSYNC become active at the rising edge of STB. However, VDD is always supplied regardless of STB. After the time ton1 has elapsed, RST changes from low to high, and the circuit state of the display is initialized. After time ton2 elapses, DATA becomes active and PCI switches to high, and an image is displayed in the display area.
[0022]
In the off sequence (B), first, DATA and PCI are inactive. After elapse of toff1, RST changes from high to low, and the internal circuit of the display is reset. After toff2, STB changes from high to low, and MCK, HSYNC, and VSYNC become inactive. When STB changes from high to low, the display side shifts from the operation mode to the standby mode. On the other hand, VDD is always maintained at the power supply voltage despite the transition to the standby mode.
[0023]
In the system adopting the standby mode as described above, the drive circuit system on the display side is made inactive according to the STB while VDD remains active. The signal STB used for standby mode control may be a control signal input independently from the set side as shown in the figure, but other external signals supplied from the set side are internally logically processed on the display side. Can also be generated. In the off sequence, the internal circuit of the display is logically reset by RST, and then STB falls. At this time, the master clock MCK and the synchronization signals HSYNC and VSYNC supplied from the set side are fixed at a constant potential from the active state. In the illustrated example, it is fixed at the low level (GND level), but may be fixed at the VDD level depending on circumstances.
[0024]
The display device that has shifted to the standby mode in response to the fall of the standby signal STB stops driving the display area while maintaining the supply of the power supply voltage VDD from the main body side of the electronic device, and disables the circuit portion. A standby control unit is provided that is activated to suppress power consumption of the panel. This standby control means is distributed in each block of the circuit section, and executes a control sequence for inactivation in response to the fall of the STB for each circuit block.
[0025]
FIG. 4 is a circuit diagram showing a specific configuration example of an offset circuit and a start circuit associated with the COM driver 5 shown in FIG. This embodiment uses a normal start circuit that does not support the standby mode. As illustrated, an offset circuit 51 and a start circuit 52 are laid out with a common driver (COM driver) 5 as a center. The COM driver 5 sends a common voltage VCOM whose polarity is inverted according to a predetermined periodic signal FRP to the output node VCOMO. In this embodiment, the periodic signal FRP is a signal that defines the frame period. The COM driver 5 is logically reset by an internal reset signal RST5.
[0026]
The offset circuit 51 includes a coupling capacitor C1 that generates a predetermined offset voltage ΔV in order to adjust the level of the common voltage with respect to the signal voltage. The coupling capacitor C1 is an external component and is mounted on a substrate different from the insulating substrate 1 in which the panel is incorporated. In addition, the offset circuit 51 includes a switch SW4 composed of a variable resistor R3 and a thin film transistor. The variable resistor R3 is an external component. The switch SW4 is included in a circuit on the insulating substrate 1. The offset common voltage VCOM appearing at the node VCOMI of the coupling capacitor C1 is supplied to the common electrode pad (COM pad) 530 through the wiring formed on the insulating substrate 1.
[0027]
The start circuit 52 precharges the coupling capacitor C1 of the offset circuit 51 to the offset voltage ΔV when the power supply voltage is raised, and discharges the coupling capacitor C1 when the power supply voltage is lowered. The start circuit 52 is a built-in circuit integrated on the insulating substrate 1 and includes a buffer (BUF) 512 to which an internal reset signal RST5 is input, an inverter 515, a buffer 516, a level shifter 520, and the like. Further, resistors R1 and R2 connected in series are included between the positive power supply voltage VDD2 and the negative power supply voltage VSS2. An intermediate node A between the resistors R1 and R2 is connected to the node VCOMO via the switch SW3. In addition, a switch SW1 is interposed on the upper end side of the resistor R1, and a switch SW2 is also interposed on the lower end side of the resistor R2. As is apparent from the above configuration, almost all parts of the COM driver 5, the offset circuit 51 and the start circuit 52 are integrated on the insulating substrate 1, and only the coupling capacitor C1 and the variable resistor R3 are externally connected. It has become.
[0028]
The on sequence of the start circuit 52 when the power is turned on will be described with reference to FIG. In the first stage, the power supply voltage VDD2 of the display device rises. As a result, the switches SW1, SW2, SW3 and SW4 become conductive. VDD2 is resistance-divided by the series resistors R1 and R2, and the node A becomes the intermediate potential ΔV. Since the switches SW3 and SW4 are also in the conductive state, the node VCOMO is also at the same potential as the node A, and the coupling capacitor C1 is charged. The ratio of the series resistors R1 and R2 is set so that the potential difference between the node A and the node VCOMO is ΔV.
[0029]
As a second stage, the drive circuit reset signal RST5 in the display device rises. As a result, the COM driver 5 in the display device becomes active and outputs an AC common voltage. At this time, the switches SW1, SW2, SW3, and SW4 are turned off in response to the reset signal RST5. Since the coupling capacitor C1 is sufficiently charged in the first stage, the output of the COM driver 5 is coupled, and a potential DC-shifted by ΔV is output to the node VCOMI. The variable resistor R3 is set so that the potential of the node VCOMI shifts by ΔV. Thereafter, as a third stage, the display start signal PCI rises and an image is displayed in the display area.
[0030]
Next, the off sequence of the start circuit 52 will be described. In the first stage, the display command PCI falls, and the screen in the display area is not displayed. Subsequently, in a second stage, the drive circuit reset signal RST5 in the display device falls. As a result, the switches SW1, SW2, SW3 and SW4 become conductive. The switch SW1 is composed of a PMOS TFT, and SW2, SW3 and SW4 are composed of NMOS TFTs. On the other hand, the COM driver 5 in the display device becomes inactive. The power supply potential VDD2 is resistance-divided by the series resistors R1 and R2, and becomes an intermediate potential ΔV at the node A. Since SW4 is also conductive, the node VCOMI is at the GND level. As a result, the coupling capacitor C1 is discharged. Thereafter, as a third stage, the power supply voltage VDD2 falls.
[0031]
FIG. 5 is a timing chart of the above-described on sequence. The portion above the alternate long and short dash line represents the change in state of display data DATA, reset signal RST3, display start signal PCI, and power supply voltage VDD input from the set side to the panel side. The portion below the alternate long and short dash line represents a change in the state of the power supply line, node, internal signal, etc. occurring in the panel. As shown in the figure, the power supply voltage VDD is supplied from the set side at the timing T1, the reset signal 3 for initialization is input at the timing T3, and the display data DATA and the display start signal PCI are input at the timing T5. On the other hand, inside the panel, the positive power supply voltage VDD2 and the negative power supply voltage VSS2 are set at timing T1. As a result, the start circuit starts operation, and charging of the coupling capacitor begins. The potential of the node VCOMO rises according to the charge. At timing T3, the node VCOMO rises to a predetermined offset potential ΔV. In accordance with this, the periodic signal FRP becomes active and the signal potential is set to the black level. Further, at the timing T5, the signal potential SIG becomes active from the black level, and the display (Display) becomes effective.
[0032]
FIG. 6 is a timing chart of the above-described off sequence. From the set side, the display data DATA and the display command PCI fall to the low level at the timing T1. Further, at timing T3, the reset signal RST3 falls to a low level, and thereafter, the power supply voltage VDD falls to a low level at timing T5. In accordance with this, inside the panel, the signal voltage SIG changes from active to black level at timing T1, and the display state switches from valid to black display. Further, at the timing T3, the internal reset signal RST5 falls, and the coupling capacitor starts to be discharged. As a result, the potential of the node VCOMO gradually decreases and reaches a low level at the timing T5. In accordance with this, the power supply voltages VDD2 and VSS2 are cut off.
[0033]
FIG. 7 is a circuit diagram showing an embodiment of the start circuit 52 having a standby mode. In order to facilitate understanding, portions corresponding to those of the previous start circuit shown in FIG. In the system display having the standby mode, the power supply VDD is not shut off even when the operation mode is shifted to the standby mode. Therefore, the start circuit 52 is controlled by a standby signal STB as a substitute for the power supply VDD.
[0034]
Similar to the previous embodiment shown in FIG. 4, the common driver 5 applies the common voltage VCOM to the common electrode. The offset circuit 51 includes a coupling capacitor C1 that generates a predetermined offset voltage ΔV in order to adjust the level of the common voltage relative to the signal voltage. The start circuit 52 precharges the coupling capacitor C1 of the offset circuit 51 to the offset voltage ΔV when the power supply voltage VDD2 rises, and discharges the coupling capacitor C1 when the power supply voltage VDD2 falls. As illustrated, the COM driver 5, the offset circuit 51, and the start circuit 52 are mounted on the common insulating substrate 1 except for the coupling capacitor C1 and the variable resistor R3.
[0035]
The offset circuit 51 includes a transistor switch SW4 and a voltage level adjusting variable resistor R3 in addition to the above-described coupling capacitor C1. The resistor R3 is an external component similar to the coupling capacitor C1. The transistor switch SW4 is formed on the insulating substrate 1. The offset-processed common voltage VCOMI input from the coupling capacitor C1 outside the insulating substrate 1 is connected to the COM pad 530 connected to the common electrode inside the system display by internal wiring.
[0036]
The start circuit 52 includes a level shifter 511 to which a standby signal STB is input, an inverter 512 to which an internal reset signal RST5 is input, an inverter 513 to which an external reset signal RST3 is input, a NAND element NAND 514, an inverter 515, a buffer (BUF) 516, Logic circuits such as a buffer 517 and a level shifter 520 are included. Further, switches SW1, SW2, SW3 and SW5 constituted by thin film transistors are included. In addition, it includes a pair of resistors R1, R2 connected in series between the positive power supply voltage VDD2 and the negative power supply voltage VSS2. The connection point of resistors R1 and R2 is represented by node A.
[0037]
The on sequence and off sequence of the start circuit 52 will be described with reference to FIG. First, in the on sequence for returning from the standby mode to the operation mode, the STB signal rises from low to high as the first step. As a result, the switches SW1, SW2, SW3, and SW4 become conductive. The power supply potential VDD2 is resistance-divided by the series resistors R1 and R2, and a desired intermediate potential is obtained at the node A. This intermediate potential is equal to the required offset potential ΔV. Since SW3 and SW4 are in a conductive state, the node VCOMO also has the same potential as the node A, and the coupling capacitor C1 is precharged. The ratio of the series resistors R1 and R2 is set so that the potential difference between the node A and the node VCOMO is ΔV. Thereafter, as a second stage, the reset signals RST3 and RST5 rise and the COM driver 5 becomes active. At the same time, the switches SW1, SW2, SW3 and SW4 are turned off. On the other hand, the switch SW5 becomes conductive, the node VCOMWR becomes VDD2, and a current flows through the variable resistor R3. Since the coupling capacitor C1 is sufficiently charged in the first first stage, the output of the COM driver 5 is coupled, and a potential DC-shifted by ΔV is output to the node VCOMI. The variable resistor R3 is set so that the potential of VCOMI is shifted by exactly ΔV. Thereafter, as a third stage, a display start signal rises and an image is displayed in the display area.
[0038]
Next, an off sequence for shifting from the operation mode to the standby mode will be described. First, as a first step, the display command PCI from the set side falls, and the image is erased from the display area. Subsequently, as a second stage, the reset signals RST3 and RST5 fall. As a result, the switches SW1, SW2, SW3, and SW4 become conductive. Conversely, SW5 is turned off. As a result, no current flows through the external variable resistor R3, and a desired power saving effect is obtained. At the same time, since the COM driver 5 in the insulating substrate 1 becomes inactive, a power saving effect can be obtained. When the switches SW1 and SW2 are turned on, the power supply potential VDD2 becomes a desired intermediate potential at the node A by the series resistors R1 and R2. At this time, since SW4 is also in a conductive state, the node VCOMI is at the GND level. As a result, the coupling capacitor C1 is discharged. Finally, as the third stage, the STB signal falls, and the switches SW1, SW2, SW3, and SW4 are turned off. As a result, the series resistors R1 and R2 are disconnected from the positive power supply line VDD2 and the negative power supply line VSS2, and no unnecessary current flows. Therefore, a desired power saving effect can be obtained.
[0039]
FIG. 8 is a timing chart showing an ON sequence in a start circuit having a standby mode. When returning from the standby mode to the operation mode in the ON sequence, the standby signal STB rises at timing T1 from the set side. On the other hand, the power supply voltage VDD is maintained at a high level from the beginning. The reset signal RST rises at timing T3, and the display data DATA and the display start signal PCI become active at timing T5. In correspondence with this, the internal power supply voltages VDD2 and VSS2 are validated at the timing T1 inside the panel. Further, charging of the coupling capacitor starts in response to the standby signal STB, and the potential of the node VCOMO starts to rise to a predetermined offset potential. When the predetermined offset potential is reached at timing T3, the internal reset signal RST5 rises and the common driver becomes active. Further, at the timing T5, the signal potential SIG becomes active and the display is validated.
[0040]
FIG. 9 shows an off sequence of the start circuit having the standby mode. This off sequence is executed when shifting from the operation mode to the standby mode. Unlike the off sequence when the power is shut off, VDD is maintained, while the standby signal STB falls from the high level to the low level at timing T5. Before that, the reset signal RST falls at timing T3. In response to this, the coupling capacitor starts to be discharged inside the panel, and the potential of the node VCOMO decreases toward the low level.
[0041]
【The invention's effect】
As described above, according to the present invention, by providing the start circuit that rapidly charges the coupling capacitor when the power is turned on, image flicker and the like can be suppressed, and high image quality can be realized. In particular, by incorporating a start circuit on the insulating substrate that quickly charges the coupling capacitor for shifting the common voltage DC when the power is turned on, the set can be reduced in size and cost. Further, even in a display system having a standby mode, the occurrence of flicker can be reduced by providing a start circuit that quickly charges and discharges a common voltage DC shift coupling capacitor in accordance with switching of a standby signal. In addition, by mounting such a start circuit on an insulating substrate, it is possible to reduce the size and cost of a set having a low power consumption mode.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a display device according to the present invention.
FIG. 2 is a timing chart showing an on sequence and an off sequence of the display device.
FIG. 3 is a timing chart showing an on sequence and an off sequence of a display device having a standby mode.
4 is a circuit diagram showing an embodiment of a start circuit mounted on the display device shown in FIG. 1; FIG.
FIG. 5 is a timing chart showing an ON sequence of the start circuit shown in FIG. 4;
6 is a timing chart showing an off sequence of the start circuit shown in FIG. 4. FIG.
FIG. 7 is a circuit diagram showing an embodiment of a start circuit corresponding to a standby mode.
8 is a timing chart showing an ON sequence of the start circuit shown in FIG.
9 is a timing chart showing an off sequence of the start circuit shown in FIG. 7;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 0 ... Display apparatus, 1 ... Insulating substrate, 2 ... Display area, 5 ... Common driver, 51 ... Offset circuit, 52 ... Start circuit, C1 ... Coupling capacitor

Claims (6)

Used as a display component of electronic equipment, operates according to display data and power supply voltage supplied from the main body side of the electronic equipment, and integrates the display area and the peripheral circuit section that drives it on an insulating substrate. A display device comprising a formed panel,
The display region includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optic material held between the two,
The circuit unit includes a driver that writes a signal voltage to the pixel electrode side in accordance with display data;
A common driver for applying a common voltage to the common electrode side;
An offset circuit including a coupling capacitor that generates a predetermined offset voltage to adjust the level of the common voltage with respect to the signal voltage;
Time of startup of the power supply voltage, the before said common voltage from the common driver is applied to the coupling capacitor, the offset circuit of the coupling capacitor precharged to Rutotomoni up offset voltage falling time of the power supply voltage And a start circuit for discharging the coupling capacitor. The panel is composed of thin film transistors formed in the same process on a common insulating substrate, together with the display region and the peripheral circuit portion that drives the display region.
The display device according to claim 1, wherein the common driver, the offset circuit, and the start circuit are mounted on the common insulating substrate except for the coupling capacitor.   2. The display device according to claim 1, wherein the start circuit operates only when the power supply voltage is raised and when the power supply voltage is lowered, and is inactive during other times. Used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state, operates according to display data and power supply voltage supplied from the main body side of the electronic device, and drives the display area. A display device comprising a panel in which peripheral circuit portions are integrally integrated on an insulating substrate,
The panel can be switched between an operation mode and a standby mode according to switching between a normal power consumption state and a low power consumption state on the electronic device main body side,
In the operation mode, the power supply voltage is supplied from the main body side of the electronic device, and the display area is driven to perform a desired display.
In standby mode, standby control means for stopping driving of the display area while maintaining the supply of power supply voltage from the main body side of the electronic device and deactivating the circuit unit to suppress power consumption of the panel With
The display region includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optic material held between the two,
The circuit unit includes a driver for writing a signal voltage on the pixel electrode side in accordance with display data sent from the main body side of the electronic device,
A common driver for applying a common voltage to the common electrode side;
An offset circuit including a coupling capacitor that generates a predetermined offset voltage to adjust the level of the common voltage with respect to the signal voltage;
When returning from the standby mode to the operation mode waiting, before the common voltage from the common driver is applied to the coupling capacitor, the coupling capacitor of the offset circuit precharging to Rutotomoni to the offset voltage, the operation mode And a start circuit for discharging the coupling capacitor when the mode is changed. The panel is composed of thin film transistors formed in the same process on a common insulating substrate, together with the display region and the peripheral circuit portion that drives the display region.
The display device according to claim 4, wherein the common driver, the offset circuit, and the start circuit are mounted on the common insulating substrate except for the coupling capacitor.   5. The display device according to claim 4, wherein the start circuit operates only when returning from the standby mode to the operation mode and when shifting from the operation mode to the standby mode, and is inactive at other times. .

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