Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.Fig. 1 is the integrally-built block diagram of expression display device of the present invention.As shown in the figure, this display device 0 integrated being formed on the dielectric substrate 1 that constitutes by glass etc.Central authorities in dielectric substrate 1 form viewing area 2.Also integrally formed to surround the peripheral circuit portion of viewing area 2.Top in the dielectric substrate 1 of rectangle forms splicing ear, and is connected with electronic equipment main body side (device side) by flexible print cable (FPC) 11.FPC11 is the plate cable of the single layer structure that is arranged in the plane of many wirings.
The matrix structure of reporting to the leadship after accomplishing a task mutually and be configured to for the signal wire S1~Sn of the gate lines G 1~Gm of row shape and row shape in viewing area 2.In the portion of reporting to the leadship after accomplishing a task of each gate lines G and signal wire S, form pixel.In the present embodiment, each pixel is made of liquid crystal cell LC, auxiliary capacitor CS and thin film transistor (TFT) TFT.Liquid crystal cell LC is made of pixel capacitors, the common electrode (COM) relative with it and the liquid crystal (electro-optical substance) that remains between the two.The grid of TFT is connected with gate lines G, source electrode is connected with signal wire S, drain electrode is connected with the pixel capacitors of liquid crystal cell LC.Auxiliary capacitor CS is connected between the drain electrode and auxiliary capacitance line of TFT.The TFT strobe pulse conducting of supplying with from gate lines G, and will write the pixel capacitors of corresponding liquid crystal cell LC from signal wire S signal supplied voltage.Auxiliary capacitor CS holding signal voltage in advance between a frame or field.
Generally liquid crystal cell LC is carried out AC driving.That is, the signal voltage that is written to liquid crystal cell LC by signal wire S periodically polarity take place anti-phase.Therewith as one man, being applied to utility voltage VCOM on the common electrode COM of liquid crystal cell LC, also must polarity to take place periodically anti-phase.Here, liquid crystal cell LC and there is asymmetry in the TFT that it carries out switch drive on polarity.Therefore,, then can show the asymmetry on the polarity, can produce deterioration in image quality such as afterimage if make centered level consistent in advance in pixel capacitors side and common electrode side.As its countermeasure, make utility voltage only carry out the biasing of assigned voltage share with respect to signal voltage, offset the asymmetry on the polarity.Have, auxiliary capacitor CS also must exchange action according to the AC driving of liquid crystal cell LC again.Therefore, with the common auxiliary capacitance line that is connected of each auxiliary capacitor CS on, must apply the anti-phase voltage of polarity with same specified period.
In the integrated formation peripheral circuit portion in four limits up and down of surrounding above-mentioned viewing area 2.Under the situation of present embodiment, this peripheral circuit portion comprises vertical driver 3, horizontal driver 4, COM driver 5, CS driver 6, DC/DC transducer 7, DC/DC transducer 7a, the interface 8 that comprises level shifter (L/S), timing generator 9 and analog voltage generator 10 etc.Yet the present invention is not limited to this structure, can suitably append necessary circuit or leave out unnecessary circuit according to the specification of display device (system display) 0.For example, according to circumstances also be assembled into sometimes generate different with signal voltage, be used to carry out white completely the demonstration or the driver of the signal voltage level of black demonstration etc.
Vertical driver 3 is connected with each gate lines G 1~Gm and presses line sequentially feeding strobe pulse.Horizontal driver 4 forms up and down a pair of, and is connected to supply with the signal voltage of regulation simultaneously from both sides with the two ends of each signal wire S1~Sn.Have, this signal voltage becomes the voltage corresponding to the video data that sends from device side by FPC11 (image information) again.
Public driver (COM driver) the 5 periodically anti-phase utility voltage VCOM of polarity is applied to the common electrode common with each liquid crystal cell LC.Attached in COM driver 5 have biasing circuit and a start-up circuit (COM starter).Biasing circuit is regulated the bias level of the utility voltage that is generated by public driver 5.Start-up circuit (COM starter) charges so that the voltage that applies of common electrode COM rises rapidly to biasing circuit when the screen starting.The CS driver 6 periodically anti-phase voltage of polarity is applied to the auxiliary capacitance line common with each auxiliary capacitor CS.
DC/DC transducer 7 will become the secondary power voltage corresponding to the specification of screen (display device 0) from the primary source voltage transformation that the electronic equipment main body is supplied with by FPC11.Especially, DC/DC transducer 7 is used for the conversion of the supply voltage VDD of positive side.Relative therewith, DC/DC transducer 7a is used for the conversion of the supply voltage VSS of minus side.
The control signal of the clock signal that the interface 8 that comprises L/S is accepted to supply with from device side by FPC11, synchronizing signal, picture signal etc.The L/S of level shift portion carries out level shift to the control signal of sending here from device side (external control signal), generates the control signal (internal control signal) of the circuit operation specification that is suitable for display device inside.Have again, in this manual, distinguishing under the situation of external control signal and internal control signal, behind the mark of the kind of representing each control signal, externally enclose numeral (3) under the situation of control signal, under the situation of internal control signal, enclose numeral (5) sometimes.After clock signal that 9 pairs of timing generators are sent here from the interface 8 that comprises L/S and synchronizing signal are handled, generate the circuit each several part is carried out the necessary clock signal of sequential control etc.Analog voltage generator 10 in advance will be corresponding to the aanalogvoltage supply level driver 4 of a plurality of level of gray scale.Horizontal driver 4 will be written to liquid crystal cell LC by the analog signal voltage of gray shade scaleization according to the image information of sending here from the device side of electronic equipment.
Fig. 2 is the sequential chart of the device side of expression electronic equipment to the control timing of display device side, and (A) expression conducting sequence, (B) expression are by sequence.Fig. 2 represents to be relevant to the common situation of the sequential control that does not have standby mode (standby).Sequential is according to the rules imported master clock signal MCK, horizontal-drive signal HSYNC, vertical synchronizing signal VSYNC, video data DATA, reset signal RST, is shown enabling signal PCI, supply voltage VDD to the display side from device side.The conducting sequential (A) that rises from device side to display side current potential, initial VDD rises, and then MCK, HSYNC, VSYNC become activation.Behind elapsed time ton1, reset signal RST switches to high level from low level, and the circuit part of display is initialised.When after this DATA switches to activation from low level behind the elapsed time ton2, show that enabling signal PCI switches to high level from low level.Thus, display image in the viewing area of display
What descend from device side to the display current potential ends the sequential (B), and at first DATA switches to the low level while from activation, shows that enabling signal PCI switches to low level from high level.Behind the elapsed time toff1, reset signal RST switches to low level from high level, and the internal state of the circuit of display is resetted.Behind the elapsed time toff2, cut off the supply of MCK, HSYNC, VSYNC, VDD is descended.Thus, VDD becomes earthing potential or floating potential.
Fig. 3 is that the conducting sequential of standby mode (standby) and the sequential chart that ends sequential are adopted in expression.For the convenience on understanding,, adopt corresponding reference marks for common conducting sequential shown in Figure 2 and by the corresponding part of sequential.Device side can carry out the switching of common power consumption state and low power consumption state.Correspondingly, display side switching controls must be become pattern and standby mode (standby), therefore, device side is input to the display side with standby signal STB.
In conducting sequential (A), at first, standby signal STB rises to high level from low level, and display returns to pattern from standby mode.Corresponding to the rising of STB, MCK, HSYNC, VSYNC become activation.Yet VDD often supplies with, and is irrelevant with STB.RST switches to high level from low level behind the elapsed time ton1, and the circuit state of display is initialised.Behind the elapsed time ton2, DATA becomes activation, and PCI switches to high level simultaneously, demonstrates image in the viewing area.
In sequential (B), at first, DATA and PCI become non-activation.Become low level through RST behind the toff1 from high level, the internal circuit of display is reset.Behind t off2, STB switches to low level from high level, and MCK, HSYNC, VSYNC become non-activation simultaneously.Become low level by STB from high level, the display side moves to standby mode from pattern.On the other hand, VDD often maintains supply voltage, and is irrelevant with the situation that moves to standby mode.
So adopting in the system of standby mode, keeping VDD constant and make that according to STB the drive circuit system of display side is non-activation for the state that activates.Employed signal STB in the standby mode control can be the control signal of independently import from device side like that as shown in the figure sometimes, also can be other the signal of external signal generation after the display side is done the internal logic processing that will supply with from device side.In sequential, after the internal circuit logic reset of RST with display, STB descends.At this moment, the major clock MCK that supplies with from device side and synchronizing signal HSYNC, VSYNC etc. are fixed to from the state that activates and decide current potential.In illustrated example, be to be fixed on low level (GND) level, also can according to circumstances be fixed on the VDD level.
Move to the display device of standby mode according to the decline of standby signal STB, possess the Opportunity awaiting control for linear parts, these Opportunity awaiting control for linear parts are that non-activation is to suppress the power consumption of screen keeping accepting from the device side of electronic equipment stopping the driving of viewing area and make circuit part simultaneously under the condition of supplying of supply voltage VDD.This Opportunity awaiting control for linear parts decentralized configuration is in each module of circuit part, and circuit block ground responds the decline of STB one by one, is used for the control timing of non-activation with implementation.
Fig. 4 is the circuit diagram that expression is attached to the concrete structure example of the biasing circuit of COM driver 5 shown in Figure 1 and start-up circuit.Present embodiment adopts not and the corresponding common start-up circuit of standby mode.As shown in the figure, be that biasing circuit 51 and start-up circuit 52 are laid in the center with public driver (COM driver) 5.COM driver 5 outputs to output node VCOMO with the anti-phase utility voltage VCOM of periodic signal FRP generation polarity in accordance with regulations.In the present embodiment, periodic signal FRP is the signal in regulation frame period.Have, COM driver 5 is by internal reset signal RST5 logic reset again.
Biasing circuit 51 possesses coupling condenser C1, and this coupling condenser C1 generates the bias voltage Δ V of regulation, to regulate the level of utility voltage with respect to signal voltage.This coupling condenser C1 is outer attached parts, is installed on the substrate different with the dielectric substrate 1 of assembling screen.The switch SW 4 that biasing circuit 51 comprises variable resistor R3 in addition and is made of thin film transistor (TFT).Variable resistor R3 is outer attached parts.Switch SW 4 is included in the circuit on the dielectric substrate 1.The utility voltage VCOM that finishes biasing that presents on the node VCOMI of coupling condenser C1 supplies with common electrode pad (COM pad) 530 by the wiring that is formed on the dielectric substrate 1.
Start-up circuit 52 is pre-charged to bias voltage Δ V with the coupling condenser C1 of biasing circuit 51 and when supply voltage descends coupling condenser C1 is discharged when supply voltage rises.This start-up circuit 52 is integrated built-in circuits that are formed on the dielectric substrate 1, comprises the impact damper (BUF) 512 that is transfused to internal reset signal RST5, phase inverter 515, impact damper 516, level shifter 520 etc.And, include resistance R 1, R2 between the supply voltage VSS2 of the supply voltage VDD2 that is connected in series in positive side and minus side.Resistance R 1 is connected with node VCOMO by switch SW 3 with intermediate node A between R2.In addition, get involved switch SW 1, also get involved switch SW 2 in the lower end side of resistance R 2 in the upper end side of resistance R 1.Can be clear and definite according to above structure, nearly all part of COM driver 5, biasing circuit 51 and start-up circuit 52 is integrated in advance being formed on the dielectric substrate 1, only coupling condenser C1 and variable resistor R3 are outer attached.
The conducting sequential of start-up circuit 52 when then, the access power supply being described with reference to Fig. 4.In the phase one, the supply voltage VDD2 of display device rises.Thus, switch SW 1, SW2, SW3, SW4 are conducting state.By resistance in series R1, R2 VDD2 is carried out electric resistance partial pressure, node A becomes intermediate potential Δ V.Because switch SW 3, SW4 also are conducting state, therefore, node VCOMO also becomes same potential with node A, and C1 charges to coupling condenser.The ratio of setting resistance in series R1, R2 is so that the potential difference (PD) of node A and node VCOMO is Δ V.
As subordinate phase, the driving circuit in the display device rises with reset signal RST5.Thus, the COM driver 5 in the display device becomes activation, and the utility voltage of output AC.At this moment, response reset signal RST5, switch SW 1, SW2, SW3 and SW4 become nonconducting state.Owing in the 1st stage coupling condenser C1 has been carried out charge charging fully, therefore, the output of COM driver 5 is coupled, and exports the current potential of the DC displacement of only having carried out Δ V to node VCOMI.Variable resistor R3 sets the potential change Δ V that makes node VCOMI for.After this, as the phase III, show that commencing signal PCI rises, and demonstrates image in the viewing area.
Then, describing start-up circuit 52 by sequential.In the phase one, display command PCI descends, and the picture of viewing area becomes non-demonstration.Then, in subordinate phase, the driving circuit in the display device descends with reset signal RST5.Thus, switch SW 1, SW2, SW3 and SW4 become conducting state.Switch SW 1 is to be made of PMOSTFT, and switch SW 2, SW3 and SW4 are made of NMOSTFT.On the other hand, the COM driver 5 in the display device becomes non-activation.Utilizing resistance in series R1, R2 that power supply potential VDD2 is carried out electric resistance partial pressure, is intermediate potential Δ V on node A.Because SW4 also is a conducting state, therefore, node VCOMI is the GND level.Thus, coupling condenser C1 is discharged.After this, as the phase III, supply voltage VDD2 descends.
Fig. 5 is the sequential chart of above-mentioned conducting sequential.Dashdotted top illustrates video data DATA, the reset signal RST3 from the device side input screen, the state variation of demonstration commencing signal PCI, supply voltage VDD.Dashdotted bottom illustrates the state variation of the inner power lead that produces of screen, node, internal signal etc.As shown in the figure, from device side supply line voltage VDD, be used for initialized reset signal 3, at moment T5 input video data DATA and demonstration commencing signal PCI in moment T3 input at moment T1.On the other hand, inner at screen, in the supply voltage VSS2 set of moment T1 with the supply voltage VDD2 and the minus side of positive side.Thus, start-up circuit begins action, and the charging of coupling condenser begins.Along with the carrying out of charging, the current potential of node COMO rises.Rise to the bias potential Δ V of regulation at moment T3 node VCOMO.Therewith accordingly, periodic signal FRP becomes activation, simultaneously signal potential is set at black level.Have, at moment T5, signal potential SIG becomes activation from black level again, and showing becomes effectively.
Fig. 6 is the above-mentioned sequential chart by sequential of expression.Drop to low level from device side at moment T1 video data DATA and display command PCI.Have, RST3 drops to low level in moment T3 reset signal again, and after this, VDD drops to low level at moment T5 supply voltage.Therewith accordingly, inner at screen, SIG changes to black level from activation at moment T1 signal voltage, and show state is from effectively switching to black the demonstration simultaneously.Have, descend at moment T3 internal reset signal RST5, the discharge of coupling condenser begins.Thus, the current potential of node VCOMO descends gradually, and T5 reaches low level in the moment.Therewith accordingly, supply voltage VDD2 and VSS2 are cut off.
Fig. 7 is the circuit diagram of embodiment that expression has the start-up circuit 52 of standby mode.For the convenience on understanding, to the corresponding part of previous start-up circuit shown in Figure 4, give corresponding with reference to label.In having the system display of standby mode, even moving to from pattern under the situation of standby mode, VDD does not cut off the electricity supply yet.Therefore, utilize standby signal STB to control start-up circuit 52, as substituting of power vd D.
With previous embodiment shown in Figure 4 in the same manner, public driver 5 is applied to common electrode with utility voltage VCOM.Biasing circuit 51 possesses coupling condenser C1, and this coupling condenser C1 generates the bias voltage Δ V of regulation, relatively to regulate the level of utility voltage with respect to signal voltage.Start-up circuit 52 is pre-charged to bias voltage Δ V with the coupling condenser C1 of biasing circuit 51 when supply voltage VDD2 rises, and when supply voltage VDD2 descends coupling condenser C1 is discharged.As shown in the figure, except coupling condenser C1 and variable resistor R3, COM driver 5, biasing circuit 51 and start-up circuit 52 are loaded on the common dielectric substrate 1.
Biasing circuit 51 also comprises the variable resistor R3 of transistor switch SW4 and voltage level adjustment usefulness except above-mentioned coupling condenser C1.Resistance R 3 similarly is outer attached parts with coupling condenser C1.Transistor switch SW4 is formed on the dielectric substrate 1.The utility voltage VCOMI that finishes bias treatment of the coupling condenser C1 input outside dielectric substrate 1 is connected to the COM pad 530 that links to each other with the common electrode of system display inside by internal wiring.
Start-up circuit 52 comprises: be transfused to standby signal STB level shifter 511, be transfused to internal reset signal RST5 phase inverter 512, be transfused to external reset signal RST3 phase inverter 513, with the logical circuit of negator NAND514, phase inverter 515, impact damper (BUF) 516, impact damper 517 and level shifter 520 etc.Also comprise the switch SW 1, SW2, SW3, the SW5 that constitute by thin film transistor (TFT).In addition, comprise a pair of resistance R 1, R2 between the supply voltage VSS2 of the supply voltage VDD2 that is connected in series in positive side and minus side.The tie point of representing resistance R 1 and R2 with node A.
Then, the conducting sequential of start-up circuit 52 is described and ends sequential with reference to Fig. 7.At first, the conducting sequential that returns to pattern from standby mode, as the phase one, the STB signal rises to high level from low level.Thus, switch SW 1, SW2, SW3, SW4 become conducting state.Utilize resistance in series R1, T2 that power supply potential VDD2 is carried out electric resistance partial pressure, become the intermediate potential of hope at node A.This intermediate potential equates with necessary bias potential Δ V.Because switch SW 3 and SW4 are conducting state, node VCOMO is a same potential with node A also, and coupling condenser C1 is by precharge.Set the ratio of resistance in series R1, R2, so that the potential difference (PD) of node A and node VCOMO is Δ V.After this, as subordinate phase, reset signal RST3, RST5 rise, and COM driver 5 becomes activation.Simultaneously, switch SW 1, SW2, SW3, SW4 become nonconducting state.On the other hand, switch SW 5 becomes conducting state, and node VCOMPWR becomes VDD2, flows through electric current among the variable resistor R3.Owing to coupling condenser C1 has been carried out charge charging fully in the initial phase one, therefore, the output of COM driver 5 is coupled, the current potential after the DC displacement of node VCOMI output only having carried out Δ V.Set variable resistor R3 so that the current potential of node VCOMI shifts delta V only just.After this, as the phase III, show that commencing signal rises, and demonstrates image in the viewing area.
Then, to move to describing of standby mode from pattern by sequential.At first, as the phase one, from the display command PCI decline of device side output, image disappears from the viewing area.Then, as subordinate phase, reset signal RST3, RST5 descend.Thus, switch SW 1, SW2, SW3, SW4 become conducting state.On the contrary, switch SW 5 becomes nonconducting state.Thus, do not flow through electric current among the attached outside variable resistor R3, the power saving effect that can obtain to wish.Similarly, because the COM driver 5 in the dielectric substrate 1 becomes non-activation, therefore, can obtain power saving effect.By switch SW 1, SW2 conducting, utilize resistance in series R1, R2, power supply potential VDD2 becomes the intermediate potential of hope at node A.Because this moment, switch SW 4 also became conducting state, node VCOMI becomes the GND level.Thus, coupling condenser C1 is discharged.At last, as the phase III, the STB signal descends, and switch SW 1, SW2, SW3, SW4 become nonconducting state.Thus, resistance in series R1, R2 are cut off from positive side power lead VDD2 and minus side power lead VSS2, can not flow through unwanted electric current.Therefore, the power saving effect that can obtain to wish.
Fig. 8 is the sequential chart of conducting sequential that expression has the start-up circuit of standby mode.In the conducting sequential, when standby mode returns to pattern, rise at moment T1 from device side standby signal STB.On the other hand, originally supply voltage VDD from beginning to maintain high level.Rise at moment T3 reset signal RST, become activation at moment T5 video data DATA and demonstration commencing signal PCI.Therewith accordingly, make internal power source voltage VDD2 and VSS2 for effective in screen inside in moment T1.Have again, response standby signal STB, the charging of coupling condenser begins, and the current potential of node VCOMO begins to rise to the bias potential of regulation.When moment T3 arrived the bias potential of regulation, internal reset signal RST5 rose, and public driver becomes activation.Have again, when moment T5 signal potential SIG becomes activation, make to be shown as effectively.
Fig. 9 represent to have standby mode start-up circuit by sequential.When pattern was shifted to standby mode, carrying out should be by sequential.When blocking with power supply by sequential different, keep VDD and on the other hand standby signal STB drop to low level at moment T5 from high level.Before this, descend at moment T3 reset signal RST.Therewith accordingly, begin to carry out the discharge of coupling condenser in screen inside, and the current potential of node VCOMO descends to low level.