WO2004066258A1 - Display - Google Patents
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- WO2004066258A1 WO2004066258A1 PCT/JP2003/016604 JP0316604W WO2004066258A1 WO 2004066258 A1 WO2004066258 A1 WO 2004066258A1 JP 0316604 W JP0316604 W JP 0316604W WO 2004066258 A1 WO2004066258 A1 WO 2004066258A1
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- Prior art keywords
- display
- common
- voltage
- circuit
- power supply
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Definitions
- the present invention relates to a display device including a pixel electrode and a common electrode facing the pixel electrode. More specifically, the present invention relates to an improved technique around a circuit for generating an AC common voltage applied to a common bright electrode.
- a flat display device represented by a conventional active matrix liquid crystal panel is widely used as a display component of an electronic device.
- the active matrix display panel operates in accordance with the display data and the power supply voltage supplied from the main body of the electronic device, and integrates a display area and a peripheral circuit section for driving the display area on an insulating substrate. It is generalized to adopt a so-called system display configuration integrated and formed in a computer.
- the display area includes pixel electrodes arranged in a matrix, a common electrode facing the pixel electrodes, and an electro-optical material such as a liquid crystal held between the two.
- the peripheral circuit section surrounding the display area includes a driver that writes a signal voltage on the pixel electrode side in accordance with display data, and a common driver that applies a common voltage on the common electrode side.
- a display device having such a configuration is disclosed in JP-A-2000-193394.
- the conventional display device is equipped with an offset circuit having a power coupling capacitor for generating a predetermined offset voltage in order to adjust the level of the common voltage with respect to the signal voltage, in addition to the common driver.
- the coupling capacitor included in the offset circuit When turning on the power to the display device, it is necessary to charge the coupling capacitor included in the offset circuit to a predetermined offset voltage.
- a predetermined offset voltage is added to the common voltage output from the common driver, so that a normal image can be displayed.
- the flit force may be visible because the level of the common voltage is not stable.
- a start circuit has been used to charge the coupling capacitor rapidly when the power is turned on. This start circuit is also used to discharge the power coupling capacitor when the power is cut off.
- the conventional common driver start circuit has been realized by a drive system outside the display device that has a system display configuration.
- the present invention provides a method of mounting a start circuit for a common driver in a display device having a system display configuration. With the goal. The following measures have been taken to achieve this objective.
- a display device comprising a panel integrally formed, wherein the display region includes a pixel electrode arranged in a matrix, a common electrode facing the pixel electrode, and an electro-optical material held between the two.
- a circuit driver for writing a signal voltage to the pixel electrode side according to display data, a common driver for applying a common voltage to the common electrode side, and a circuit for adjusting a level of the common voltage with respect to the signal voltage.
- An offset circuit having a power coupling capacitor for generating a predetermined offset voltage, and a coupling capacitor of the offset circuit when the power supply voltage rises Together with pre-charged to offset voltage, characterized in that it comprises a start circuit for Day scan charged fall during the coupling capacitor of the power supply voltage.
- the panel includes the thin film transistors formed on the same process on the same insulating substrate, together with the display area and the peripheral circuit portion for driving the display area, and the common driver and the offset.
- the start circuit and the start circuit are mounted on the common insulating substrate except for the coupling capacitor.
- the start circuit operates only when the power supply voltage rises and when the power supply voltage falls, and becomes inactive at other times.
- the present invention is used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state, and operates according to display data and a power supply voltage supplied from a main body side of the electronic device to perform display.
- a display device comprising a panel in which an area and peripheral circuit parts for driving the area are integrally formed on an insulating substrate, wherein the panel has a low power consumption state and a low power consumption state on the electronic device body side. Switching between operation mode and standby mode according to switching of power consumption state In the operation mode, the power supply voltage is supplied from the main body of the electronic device to operate, the display area is driven to perform a desired display, and in the standby mode, the power supply voltage is supplied from the main body of the electronic device.
- the circuit section includes a pixel electrode disposed, a common electrode facing the pixel electrode, and an electro-optical material held between the two, and the circuit unit is disposed on the pixel electrode side in accordance with display data sent from the main body of the electronic device.
- An offset circuit with a generated power coupling capacitor and when returning from the standby mode to the operation mode, the power supply capacitor of the offset circuit is precharged to the offset voltage in advance and the operation mode is switched to the standby mode.
- the panel includes the display region and the peripheral circuit portion for driving the display region, each including a thin film transistor formed on a common insulating substrate by the same process.
- the circuit and the start circuit are mounted on the common insulating substrate except for the coupling capacitor.
- the start circuit operates only when returning from the standby mode to the operation mode and when shifting from the operation mode to the standby mode, and is inactive for other times.
- a system for rapidly charging a coupling capacitor for offsetting a common voltage applied to a common electrode of a display device to a desired offset potential when the power is turned on is mounted in the liquid crystal display device.
- the display panel of the system display configuration includes a display area and a display area.
- the peripheral circuit units that drive the TFTs are composed of thin film transistors formed on the same insulating substrate by the same process.
- the common driver, offset circuit, and start circuit belonging to this circuit section are integrated and formed by thin-film transistors on a common insulating substrate, except for the coupling capacitor.
- a system display that can switch between normal operating mode and standby mode is used. In this case, when returning from the standby mode to the operation mode, it is necessary to similarly rapidly charge the coupling capacitor for the common voltage shift.
- a start circuit for this can also be incorporated in the display device.
- FIG. 1 is a block diagram showing an overall configuration of a display device according to the present invention.
- FIG. 2 is a timing chart showing the ON sequence and the OFF sequence of the display device.
- FIG. 3 is a timing chart showing an on-sequence and an off-sequence of the display device having the standby mode.
- FIG. 4 is a circuit diagram showing an embodiment of a start circuit mounted on the display device shown in FIG.
- FIG. 5 is a timing chart showing an ON sequence of the start circuit shown in FIG.
- FIG. 6 is a timing chart showing an off sequence of the start circuit shown in FIG.
- FIG. 7 is a circuit diagram showing an embodiment of the start circuit corresponding to the standby mode.
- FIG. 8 is a timing chart showing an ON sequence of the start circuit shown in FIG.
- Figure 9 is a timing chart showing the off sequence of the start circuit shown in Figure 7. It is Guciato. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram showing the entire configuration of the display device according to the present invention.
- the display device 0 is integrally formed on an insulating substrate 1 made of glass or the like.
- a display area 2 is formed at the center of the insulating substrate 1, and a peripheral circuit section is integrally formed so as to surround the display area.
- a connection terminal is formed on the upper side of the rectangular insulating substrate 1, and is connected to the electronic device main body side (set side) via a flexible printed cable (FPC) 11.
- FPC 11 has a flat-layered flat cape in which a plurality of wirings are arranged in a plane.
- the display area 2 has a matrix configuration in which row-shaped gut lines G1 to Gm and column-shaped signal lines S1 to Sn cross each other. Pixels are formed at the intersections of the gate lines G and the signal lines S.
- each pixel includes a liquid crystal element L C, a storage capacitor C S, and a thin film transistor T F T.
- the liquid crystal element L C is composed of a pixel electrode, a common electrode (C OM) facing the pixel electrode, and a liquid crystal (electro-optical material) held therebetween.
- the gate electrode of TFT is connected to the gate line G, the source electrode is connected to the signal line S, and the drain electrode is connected to the pixel electrode of the liquid crystal element LC.
- the trapping capacitance CS is connected between the drain electrode of TFT and the auxiliary capacitance line.
- the TFT is turned on by the selection pulse supplied from the gate line G, and writes the signal voltage supplied from the signal line S to the corresponding pixel electrode of the liquid crystal element LC.
- the storage capacitor CS holds the signal voltage for one frame or one field.
- the liquid crystal element LC is generally driven by an alternating current. That is, via the signal line S The polarity of the signal voltage written to the liquid crystal element LC is periodically inverted. In accordance with this, the polarity of the common voltage VCOM applied to the common electrode COM of the liquid crystal element LC also needs to be periodically inverted.
- the liquid crystal element LC and the TFT for driving the liquid crystal element have asymmetry in polarity. For this reason, if the center level is matched between the pixel electrode side and the common electrode side, asymmetry regarding the polarity is exhibited, and image quality such as image sticking is deteriorated.
- a common voltage is offset from the signal voltage by a predetermined voltage to cancel polarity asymmetry.
- the trapping capacitance CS also needs to be operated in an AC manner in accordance with the AC drive of the liquid crystal element LC. For this reason, it is necessary to apply a voltage whose polarity is inverted at the same cycle to the auxiliary capacitance line connected commonly to each auxiliary capacitance CS.
- Peripheral circuit portions are integrally formed on four sides of the upper, lower, left, and right surrounding the display area 2 described above.
- the peripheral circuit section includes a vertical driver 3, a horizontal driver 4, a COM driver 5, a CS driver 6, a DC / DC converter 7, a DC / DC converter 7a, a level shifter (L / S).
- Interface 8 a timing generator 9, an analog voltage generator 10 and the like.
- the present invention is not limited to this configuration, and necessary circuits are appropriately added according to the specifications of the display device (system display) 0, while unnecessary circuits are deleted.
- a driver that generates a signal voltage level used for a completely white display or a completely black display separately from the signal voltage may be incorporated in some cases.
- the vertical driver 3 is connected to each of the gate lines G1 to Gm, and supplies a selection pulse line by line.
- the horizontal driver 4 is formed as a pair of upper and lower parts, is connected to both ends of each signal line S1 to Sn, and supplies a predetermined signal voltage from both sides simultaneously. This signal voltage corresponds to display data (image information) sent from the set side via the FPC 11.
- the common driver (COM driver) 5 applies a common voltage VCOM whose polarity is periodically inverted to a common electrode common to each liquid crystal element LC.
- the COM Dryno 5 comes with an offset circuit and a start circuit (COM starter). The offset circuit adjusts the offset level of the common voltage generated by the common driver 5.
- the start circuit (COM starter) charges the offset circuit when the panel is started, and quickly starts applying the common voltage VCOM.
- the CS driver 6 applies a voltage whose polarity is inverted periodically to an auxiliary capacitance line common to the respective storage capacitances CS.
- the DC / DC converter 7 converts a primary power supply voltage supplied from the electronic device body via the FPC 11 to a secondary power supply voltage according to the specifications of the panel (display device 0). In particular, the DC / DC converter 7 is used to convert the positive power supply voltage VDD. On the other hand, the DC / DC converter 7a is used for converting the negative power supply voltage V s S.
- the interface 8 including the L / S receives control signals such as a clock signal, a synchronization signal, and an image signal supplied from the set side via the FPC 11.
- the level shifter L / S shifts the level of the control signal (external control signal) sent from the set side and generates a control signal (internal control signal) that meets the circuit operation specifications inside the display device.
- a numeral indicating the type of each control signal is followed by a numeral (3) in the case of the external control signal, and the internal control signal In some cases, a number (5) may be added.
- the timing generator 9 processes the clock signal and the synchronization signal sent from the interface 8 including the L / S to generate the clock signal necessary for the timing control of each part of the circuit. I do.
- the analog voltage generator 10 supplies a plurality of levels of analog voltages to the horizontal driver 4 in advance according to the gradation.
- the horizontal driver 4 performs gradation processing according to the image information sent from the main body of the electronic device. Write the analog signal voltage to the liquid crystal element LC.
- FIG. 2 is a timing chart showing a control sequence on the set side with respect to the display device side, where (A) shows an on-sequence and (B) shows an off-sequence.
- Figure 2 shows a normal case without sequence control for the standby mode (standby mode).
- the reset signal RST switches from low to high, and the display circuit is initialized.
- DATA switches from low to active, and the display enable signal PCI switches from low to high.
- an image is displayed on the display area of the display.
- DAT A In the off-sequence (B) in which the display is turned off from the set side, DAT A first switches from active to low, and the display enable signal PCI switches from high to low. After a lapse of time toff1, the reset signal RST switches from high to low, resetting the internal state of the display circuitry. After the time toff2 has elapsed, the supply of MCK, HS YNC, and VSYNC is cut off, and finally VDD falls. As a result, YDD becomes the ground potential or the floating potential.
- Figure 3 is a timing chart showing the on-sequence and off-sequence that employ the standby mode (stampy mode).
- the parts corresponding to the normal on-sequence and off-sequence shown in FIG. Normal power consumption on the set side State and low power consumption state can be switched. In accordance with this, it is necessary to control the display side to switch between the operation mode and the standby mode (stampy mode). For this reason, the set side inputs the stampy signal STB to the display side.
- the stamp signal STB first rises from low to high, and the display returns from the standby mode to the operation mode.
- MCK, HS YNC, and V S YNC become active at the rise of STB.
- VDD is always supplied regardless of the SB.
- R ST switches from low to high, and the display circuit state is initialized.
- DATA becomes active and PCI switches to high, and an image is displayed in the display area.
- the drive circuit system on the display side is deactivated according to the STB while VDD is kept active.
- the signal STB used for the standby mode control may be a control signal input independently from the set side as shown in the figure, but other external signals supplied from the set side are internally output on the display side. It can also be generated by logical processing.
- the internal circuit of the display is logically reset by RST, and then STB falls.
- the master clock MCK and synchronization signals HS YNC and VS YNC supplied from the set side are fixed at a constant potential from the active state. In the example shown, it is fixed to low level (GND level), but may be fixed to VDD level in some cases.
- the display device which has shifted to the standby mode in response to the fall of the stamp signal STB, stops driving the display area while the power supply voltage VDD is being supplied from the main body of the electronic device, and disables the circuit section. It has standby control means that is activated to suppress panel power consumption. This standby control means is distributed in each block of the circuit section, and executes a control sequence for inactivation in response to the falling of the STB for each circuit block.
- FIG. 4 is a circuit diagram showing a specific configuration example of an offset circuit and a start circuit associated with the COM driver 5 shown in FIG. This embodiment uses a normal start circuit that does not support the standby mode.
- an offset circuit 51 and a start circuit 52 are laid out with a common driver (COM driver) 5 as a center.
- the COM driver 5 sends out a common voltage VCOM whose polarity is inverted according to a predetermined periodic signal FRP to an output node VCOMO.
- the periodic signal FRP is a signal that defines the frame period.
- the COM driver 5 is set so that a logical reset is applied by the internal reset signal RST 5.
- the offset circuit 51 has a power coupling capacitor C1 for generating a predetermined offset voltage ⁇ V in order to adjust the level of the common voltage with respect to the signal voltage.
- This coupling capacitor C1 is an external component, and is mounted on a substrate different from the insulating substrate 1 in which the panel is incorporated.
- the offset circuit 51 further includes a switch SW4 composed of a variable resistor R3 and a thin film transistor.
- the variable resistor R3 is an external component.
- the switch SW4 is included in the circuit on the insulating substrate 1. Coupling condensation The offset common voltage VC OM appearing at the node VCOM I of the sub CI is supplied to the common electrode pad (C OM pad) 530 through the wiring formed on the insulating substrate 1.
- the start circuit 52 precharges the power coupling capacitor C1 of the offset circuit 51 when the power supply voltage rises to the offset voltage AV, and disassembles the power coupling capacitor C1 when the power supply voltage falls. Charge.
- the start circuit 52 is a built-in circuit integrated on the insulating substrate 1 and includes a buffer ( ⁇ UF) 512 to which the internal reset signal RS ⁇ 5 is input, an impeller 515, a buffer 516, Level shifter 520 and the like are included. Further, it includes resistors R 1 and R 2 connected in series between the positive power supply voltage VDD 2 and the negative power supply voltage VSS 2. The intermediate node ⁇ ⁇ between the resistors R 1 and R 2 is connected to the node VCOMO via the switch SW3.
- a switch SW1 is interposed at the upper end of the resistor R1, and a switch SW2 is interposed at the lower end of the resistor R2.
- the offset circuit 51 and the start circuit 52 are integrated on the insulating substrate 1, and the power coupling capacitors C1 and Only the variable resistor R3 is external.
- the ON sequence of the start circuit 52 when the power is turned on will be described with reference to FIG.
- the power supply voltage VDD 2 of the display device rises.
- switches SW1, SW2, SW3 and SW4 become conductive.
- VDD 2 is resistance-divided by the series resistances R l and R 2, and the node A has an intermediate potential ⁇ V.
- node VCOMO also has the same potential as node A, and coupling capacitor C1 is charged.
- the ratio between the series resistances R l and R 2 is set so that the potential difference between node A and node VCOMO becomes ⁇ V.
- the reset signal RST 5 for the drive circuit in the display device rises. Go up.
- the COM driver 5 in the display device becomes active, and outputs an AC common voltage.
- the switches SW1, SW2, SW3 and SW4 are turned off in response to the reset signal RST5.
- the coupling capacitor C1 Since the coupling capacitor C1 is sufficiently charged in the first stage, the output of the COM driver 5 is coupled, and the potential DC shifted by only AV is output to the node VCOMI.
- the variable resistor R3 is set so that the potential of the node VCOM I shifts by ⁇ V.
- the display start signal PCI rises, and an image is displayed in the display area.
- an off sequence of the start circuit 52 will be described.
- the display instruction PCI falls, and the screen in the display area is hidden.
- the reset signal RST 5 for the drive circuit in the display device falls.
- the switches SW1, SW2, SW3 and SW4 become conductive.
- Switch SW1 is composed of PMO STFT, and SW2, SW3 and 'SW4 are composed of NMO STFT.
- the COM driver 5 in the display device becomes inactive.
- the power supply potential VDD 2 is divided by the series resistors R 1 and R 2, and the node A has an intermediate potential ⁇ V. Since SW4 is also conducting, node VCOM I is at GND level. As a result, the coupling capacitor C1 is discharged. Thereafter, as a third stage, the power supply voltage VDD 2 falls.
- FIG. 5 is a timing chart of the above-described on-sequence.
- the part above the dashed line indicates the change in the state of the display data DATA, reset signal RST 3, display start signal PCI, and power supply voltage VDD that are input from the set side to the panel side.
- the part below the dashed line indicates the state change of the power supply line, node, internal signal, etc. occurring in the panel.
- the power supply voltage VDD is supplied from the set side at the timing T1, and the reset signal 3 for initialization is input at the timing T3.
- the display data DATA and the display start signal PCI are input.
- the power supply voltage VDD 2 on the positive side and the power supply voltage VSS 2 on the negative side are set at timing T 1.
- the start circuit starts operating, and charging of the coupling capacitor starts.
- the potential of the node VC OMO increases according to the charging.
- the node VC OMO rises to a predetermined offset potential ⁇ .
- the periodic signal FR becomes active and the signal potential is set to the black level.
- the signal potential SIG becomes active from the black level, and the display (Display) becomes valid.
- FIG. 6 is a timing chart of the above-described off sequence. From the set side, the display data DATA and the display instruction PCI fall to low level at timing T1. Further, the reset signal R ST3 falls to the mouth level at the timing T3, and thereafter, the power supply voltage VDD falls to the low level at the timing T5. At the same time, the signal voltage S IG changes from active to black level at timing T1 inside the panel, and the display state switches from valid to black. Further, at timing T3, the internal reset signal RST5 falls, and the discharge of the coupling capacitor starts. As a result, the potential of the node VCOMO gradually decreases and reaches the low level at the timing T5. At the same time, the power supply voltages VDD2 and VSS2 are cut off.
- FIG. 7 is a circuit diagram showing an embodiment of the start circuit 52 having the standby mode. To facilitate understanding, parts corresponding to the start circuit shown in FIG. 4 are denoted by corresponding reference numerals.
- the start circuit 52 is controlled by the standby signal STB as a substitute for the power supply VDD.
- the common driver 5 applies a common voltage VCOM to the common electrode.
- the offset circuit 51 includes a power coupling capacitor C1 for generating a predetermined offset voltage ⁇ V in order to adjust the level of the common voltage relative to the signal voltage.
- the start circuit 52 pre-charges the cutting capacitor C 1 of the offset circuit 51 to the offset voltage AV, and at the same time the power supply capacitor falls when the power supply voltage VDD 2 falls. Discharge C1.
- the COM driver 5, offset circuit 51 and start circuit 52 are mounted on a common insulating substrate 1 except for the power coupling capacitor C1 and the variable resistor R3.
- the offset circuit 51 includes a transistor switch SW4 and a variable resistor R3 for adjusting a voltage level, in addition to the above-described power coupling capacitor C1.
- the resistor R3 is an external component like the coupling capacitor C1.
- the transistor switch SW4 is formed on the insulating substrate 1.
- the offset-processed common voltage V COM I input from the force-pulling capacitor C 1 outside the insulating substrate 1 is connected by internal wiring to the COM pad 530 that is connected to the common electrode inside the system display. .
- the start circuit 52 includes a level shifter 5 11 to which the stamp signal STB is input, an inverter 5 12 to which the internal reset signal RST 5 is input, an inverter 5 13 to which the external reset signal RST 3 is input, and a NAND.
- the device includes logic circuits such as NAND 514, inverter 515, buffer (BUF) 516, buffer 517, and level shifter 520. Furthermore, switches SW1, SW2, SW3, and SW5 composed of thin film transistors are included. In addition, it includes a pair of resistors R 1 and R 2 connected in series between the positive power supply voltage VDD 2 and the negative power supply voltage VSS 2. The connection point between resistors R 1 and R 2 is represented by node A.
- the ON sequence and the OFF sequence of the start circuit 52 will be described with reference to FIG.
- the STB signal rises from low to high as a first step.
- the switches SW1, SW2, SW3, and SW4 become conductive.
- the power supply potential VDD 2 is resistance-divided by the series resistors R 1 and R 2, and the desired intermediate potential is obtained at the node A. This intermediate potential is equal to the required offset potential ⁇ . Since SW3 and SW4 are conducting, node VCOMO also has the same potential as node ⁇ , and the coupling capacitor C1 is precharged.
- the ratio between the series resistances R 1 and R 2 is set so that the potential difference between node A and node VC OMO becomes ⁇ V.
- the reset signals RST 3 and RST 5 rise, and the COM driver 5 becomes active.
- the switches SW1, SW2, SW3, and SW4 are turned off.
- the switch SW5 becomes conductive, the node VC OMP WR becomes VDD2, and the current flows through the variable resistor R3. Since the coupling capacitor C1 is sufficiently charged in the first stage, the output of the COM driver 5 is coupled, and the potential shifted DC by ⁇ V is output to the node VCOMI. You.
- the variable resistor R3 is set so that the potential of VCOMI shifts by just ⁇ V. Thereafter, as a third step, the display start signal rises, and the image is displayed on the display area.
- FIG. 8 is a timing chart showing an ON sequence in the start circuit having the standby mode.
- the standby signal STB rises at the timing T1 from the set side.
- the power supply voltage VDD has been maintained at a high level from the beginning.
- the reset signal RST rises, and at timing T5, the display data DATA and the display start signal PCI become active.
- the internal power supply voltage VDD 2 and VSS 2 are enabled at the timing T 1 inside the panel.
- charging of the power coupling capacitor starts in response to the standby signal STB, and the potential of the node VC OMO starts to rise to a predetermined offset potential.
- the internal reset signal RST5 rises and the common driver is activated.
- the signal potential S IG becomes active and the display is enabled.
- FIG. 9 shows an off sequence of the start circuit having the standby mode. This off sequence is executed when transitioning from the operation mode to the standby mode. Unlike the off sequence at power-off, VDD is maintained On the other hand, the standby signal STB falls from the high level to the low level at the timing T5. Before that, the reset signal RST falls at timing T3. In response to this, the discharge of the coupling capacitor starts inside the panel, and the potential of the node VCOMO decreases toward the mouth level.
- the start circuit for rapidly charging the coupling capacitor when the power is turned on it is possible to suppress image flickering and the like, and to achieve high image quality.
- a built-in start circuit on the insulating substrate that rapidly charges the coupling capacitor for the common voltage DC shift when the power is turned on makes it possible to reduce the set size and cost.
- a start circuit that quickly charges and discharges the coupling capacitor for common voltage DC shift in response to the switching of the standby signal can cause flickering, etc. Can be reduced.
- by mounting such a start circuit on an insulating substrate it is possible to realize a small-sized and low-cost set having a low power consumption mode.
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/541,092 US20060181498A1 (en) | 2003-12-24 | 2003-12-24 | Display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003015808A JP4062106B2 (en) | 2003-01-24 | 2003-01-24 | Display device |
JP2003-15808 | 2003-01-24 |
Publications (1)
Publication Number | Publication Date |
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WO2004066258A1 true WO2004066258A1 (en) | 2004-08-05 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/016604 WO2004066258A1 (en) | 2003-01-24 | 2003-12-24 | Display |
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JP (1) | JP4062106B2 (en) |
KR (1) | KR101008005B1 (en) |
CN (1) | CN100416645C (en) |
TW (1) | TWI237223B (en) |
WO (1) | WO2004066258A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4626246B2 (en) * | 2004-09-29 | 2011-02-02 | カシオ計算機株式会社 | Liquid crystal display device and drive control method for liquid crystal display device |
JP2007147848A (en) * | 2005-11-25 | 2007-06-14 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display device |
KR100804631B1 (en) * | 2006-05-12 | 2008-02-20 | 삼성전자주식회사 | VCOM Generator and Method and Liquid Crystal Display |
JP5009373B2 (en) | 2007-10-16 | 2012-08-22 | シャープ株式会社 | Driving circuit for liquid crystal display device, liquid crystal display device, and driving method for liquid crystal display device |
US8531443B2 (en) | 2008-09-16 | 2013-09-10 | Sharp Kabushiki Kaisha | Display driving circuit, display device, and display driving method |
US9047830B2 (en) * | 2012-08-09 | 2015-06-02 | Pixtronix, Inc. | Circuits for controlling display apparatus |
US9653035B2 (en) | 2013-08-23 | 2017-05-16 | Sitronix Technology Corp. | Voltage calibration circuit and related liquid crystal display device |
TWI595299B (en) * | 2014-01-23 | 2017-08-11 | 元太科技工業股份有限公司 | Pixel array |
TWI707173B (en) * | 2019-01-15 | 2020-10-11 | 友達光電股份有限公司 | Display apparatus |
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JPH06113241A (en) * | 1992-09-30 | 1994-04-22 | Sony Corp | Driving circuit for liquid crystal display device |
JP2000267618A (en) * | 1999-03-17 | 2000-09-29 | Casio Comput Co Ltd | Liquid crystal display |
JP3835967B2 (en) * | 2000-03-03 | 2006-10-18 | アルパイン株式会社 | LCD display |
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- 2003-01-24 JP JP2003015808A patent/JP4062106B2/en not_active Expired - Fee Related
- 2003-12-24 KR KR1020057012627A patent/KR101008005B1/en active IP Right Grant
- 2003-12-24 WO PCT/JP2003/016604 patent/WO2004066258A1/en active Application Filing
- 2003-12-24 CN CNB200380109001XA patent/CN100416645C/en not_active Expired - Fee Related
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2004
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JPH11271707A (en) * | 1998-03-19 | 1999-10-08 | Toshiba Corp | Liquid crystal display device |
JP2000193941A (en) * | 1998-12-25 | 2000-07-14 | Toshiba Corp | Liquid crystal display device |
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JP2002189460A (en) * | 2000-10-13 | 2002-07-05 | Sharp Corp | Display device, method for driving the same, and method for driving liquid crystal display device |
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Also Published As
Publication number | Publication date |
---|---|
CN100416645C (en) | 2008-09-03 |
KR20050092731A (en) | 2005-09-22 |
TW200424999A (en) | 2004-11-16 |
TWI237223B (en) | 2005-08-01 |
CN1739136A (en) | 2006-02-22 |
KR101008005B1 (en) | 2011-01-14 |
JP2004226785A (en) | 2004-08-12 |
JP4062106B2 (en) | 2008-03-19 |
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