GB2447957A - DC-DC converter arrangement for a display driver and display - Google Patents

Abstract

A DC-DC converter arrangement is provided, for example for use in a display driver (4) of an active matrix liquid crystal display. The arrangement comprises a DC-DC converter (36) which has an input (CK1) for receiving an energising signal. A selecting circuit (40), which may be a multiplexer, selects between supplying a system clock signal (SCK) to the converter (36) when the system clock signal (SCK) is active and an output signal (OCSK) from an oscillator (38) when the system clock signal (SCK) is inactive. When the system clock signal (SCK) is active, the oscillator (38) is disabled. This saves power and prevents the need to have the system clock running all the time.

Description

DC-DC Converter Arrangement, Display Driver and Display The present

invention relates to a DC-DC converter arrangement, to a display driver including such an arrangement and to a display including such a display driver. Such arrangements may he used, ft)r example, in active niatrix displays for display drivers integrated on the display substrate using thin hIm transistors (TFTs). Examples of applications of such displays include srnall" displays for mobile applications where power consumption is important and system complexity should he rnininiised.

The increase in demand for Active Matrix Liquid Crystal Displays (AMLCD) has led to the development of on-panel Thin Film Transistor (TFT) display driving circuits. A typical AMLCD is shown in Figure 1. The Pixel matrix 12 is driven by source driver 2 and gate driver 4. Each pixel contains a TFT 6 to transfer a video voltage on to the liquid crystal (LC) 8. The gates of all TFTs within a row of pixels arc connected together to form a gate line. The sources of all TFTs within a colunin of pixels are connected together to form a source line. The pixel matrix 12 in Figure I has m pixel columns and n pixel rows. The TFT 6 shown in Figure 1 should be turned ON and OFF by the gate driver 4. It is coninion for the voltage swing on the top plate of the pixel capacitor to be Vpixelmax-Vpixelniin > VDD-VSS as shown in Figure 2. Vpixel is video voltage, VDD and VSS are supply voltages and ON margin and OFF margin are margin voltages required to turn ON and OFF the TFT 6 shown in Figure 1. Hence the level of gate driver 4 signal should be high enough to turn the TFT 6 ON and low enough to turn TFT 6 OFF. This may require extra supplies VDDH>VDD and/or VS SI-I <VS S In a typical display-driving scheme, the gate driver 4 in Figure 1 selects a row of pixels by driving a gate line high and keeping all other gate lines low as shown in Figure 3. A typical gate driver (see Figure 4) consists of a shift register 16, level shifters 18 and output buffers 20 to drive gale lines as shown in Figure 3. Typical level shifters 18 are shown in Figure 5. The voltage levels of the shift register output QO (see Figure 4), and the output buffer output GLO are shown in Figure 6.

A DC-to-DC converter is needed to generate the high supply voltages VDDH and VSSH (see Figure 5) used to drive level shifters 18 and output buIi'ers 20 shown in Figure 4. A typical DC-to-DC converter needs a clock to generate high voltage outputs.

An oscillator (electronic device used to generate clock signals) can generate this clock or a system clock used to drive the source driver 2 or the gate driver 4 shown in Figure I can be used to drive a DC-to-DC converter.

A DC-to-DC converter needs the clock to be supplied all the time to regulate the voltages to the required level. This is essential because leakage can occur in level shifters shown in Figure 5. Any leakage through transistors will draw power from VDDH/VSSH, even when there is no switching activity. This will affect the voltage level of VDDH/VSSH. Any drop in generated high supply voltages VDDH or VSSH by the DC-to-DC converter may cause poor image quality.

It is prelrable to stop the system clock SCK (sec Figure 7) in the blanking tinie (time between the end of one row or frame of video data and start of the next row or frame of video data) or in low power mode or low frame rate niode. The reason is to stop all the switching activities in low power mode. However, if the oscillator is used all the time, there is clock duplication on the panel and they consume more power if they are always

ON

US 2005/0073490 describes a gate driver with a DC-DC converter, which uses a system clock (Gale Driver clock). The converter is driven by CKV (see Figure 8) up to 176 clocks, which is the display period, and frequency is reduced from 177-300 clocks, which is the blanking period. The drawback is that the converter needs the system clock to be available even in the blanking penod of the display, which consumes power.

Likewise, other two types of waveform generators for DC-DC converters are disclosed in A 2.2 inch, narrmi' frame liquid crystal system display with low voltage intc?rtace circuitry", SID 2006 Digest PP /654-1657 (see Figure 9). This describes using a panel clock and a divider circuit in the conventional method. The panel clock needs to be available all the tin-ic and this consumes nîore power in blanking tinie and low power mode. Using a ring oscillator in method two (see Figure 10) consumes more power due to two clocks being active at the same time. Also the oscillators are very noisy circuits; S having the oscillators ON while the image is being written to the display can cause the display signals to be noisy and hence poor image quality.

US 5,712,778 describes a DC-DC converter using a polarity signal (see Figure I I) as a clock for a DCDC circuit. A polarity signal POL is a low frequency signal used to control the voltage applied to the LC. It typically inverts at the end of each row, so has a frequency of' order 10's of' KHL where as the DCDC converter requires clock waveforms in order of' 100's of' KHL to be very efficient. Also POL signal may stop or its frequency may be reduced in low power mode.

According to a first aspect of the invention, there is provided a DC-DC converter arrangement as defined in the appended claim 1.

According to a second aspect of' the invention, there is provided a display driver as defined in the appended claim 7.

According to a third aspect of the invention, there is provided a display as defined in the appended claim 12.

Embodiments of the invention are defined in the other appended claims.

It is thus possible to provide an arrangement which provides DC-DC conversion irrespective of whether a system clock is active but with reduced power consumption.

The oscillator is disabled for most or all of the time that a system clock is active but the system clock is not required to remain active when it is not otherwise needed. For example, the oscillator may be active only during display blanking periods and may be inactive when image data are being written to the display. The displayed signals are not substantially affected by oscillator noise so thai image quality is not compromised.

The invention will he tirther described, by way of example, with refirence to the accompanying drawings, in which: Figure 1 is' a block schematic diagram of a known type of active matrix liquid crystal display to which the invention may be applied; Figure 2 illustrates supply voltages required by the display of Figure 1; Figure 3 is a waveform diagram illustrating operation of a gate driver of the display of Figure 1: Figure 4 is a block schematic diagrani ofan example of the gate driver of Figure 1; FigureS is a circuit diagram illustrating Iwo known types of level shifting circuits of the gate driver olFigure 4; Figure 6 is a waveform diagram illustrating waveforms occurring in the gate driver of Figure 4; Figure 7 is a waveform diagram illustrating waveforms occurring during operation of the display of Figure 1; Figure 8 is a waveform diagram illustrating operation of a known type of gate driver including a DC-DC converter; Figure 9 is a block schematic diagrani ola known type of DC-DC converter; Figure 10 is a block schematic diagram of another known type of DC-DC converter; Figure II is a circuit diagram of a further known type of DC-DC converter; Figure 12 is a block schematic diagram of a DCDC converter arrangement constituting an embodiment of the invention and suitable for use in a gate driver of the type shown in Figure 4 and in a display of the type shown in Figure 1; Figure 13 is a block schematic diagram of a DC-DC converter arrangement constituting an embodiment of the invention, illustrating a possible modification of the arrangement shown in Figure 12; Figure 14 is a waveform diagram illustrating the derivation of an enable signal for use with the arrangement shown in Figure 13; 1 5 Figure 15 is a block schematic diagram illustrating an arrangement for generating the enable signal shown in Figure 14; Figure 16 is a circuit diagrani of an oscillator of the arrangement shown in Figure 12 or Figure 13; Figure 17 is a circuit diagram of a DC-DC converter of the arrangement shown in Figure 12; Figure 18 is a circuit diagram ol'a clock generator for generating non-overlapping clock signals; and Figure 19 is a liming diagram illustrating operation of the generator of' Figure 18.

A first embodiment is shown in Figure 1 2. The Inputs IN I and lN2 of' a multiplexer (MUX) 40 are connected to a system clock SCK and to the output of an oscillator 38 OSCK, respectively. The output of' the MUX 40 CKI is connected to a DCDC converter 36. The enable signal EN I is connected to the EN input of oscillator 38, and a second enable signal EN2 is connected to SEL input ofmultiplexer40. A multiplexer can be any conventional multiplexer made olconibinalional logic gates or switches.

The oscillator can he any known type of oscillator such as an RC oscillator or ring oscillator.

The signal EN2 is used as the select signal for the mux 40. When EN2 goes high JN2 is selected and OSCK drives the DCDC converter 36 and when EN2 goes low IN] is selected and SCK drives the DCDC converter 36. The EN] signal is used to start the oscillator. ENI signal can go high before EN2 in case oscillator needs start-up time to oscillate.

An oscillator clock OSCK is used to drive DCDC converter in absence of system clock SCK as shown in Figure 12. SCK can also be a clock made by dividing the system clock.

A second embodiment is shown in Figure 13. The same enable signal EN can be used for both the oscillator 38 and the select signal for the multiplexer 40.

Figure 14 illustrates how to generate the enable signal using display system signals. A typical Reset-set Flip-flop (RSFF) 42 shown in Figure 15 is used. The start pulse (SSP) is connected to the reset input R of RSFF 42. The last sampling pulse (SMPn) signal is connected to the set input S of RSFF 42. The output Q of the RSFF 42 is used as the enable signal to start the oscillator.

The SSP signal (see Figure 14) is the start up signal for sampling the video data. This' indicates the start of the system clock SCK. SMPn is the last sampling pulse, which indicates the stop of the systeni clock SCK.

The operation of the circuit is, when SMPn goes HIGH the RSFF 42 is set and Q goes HIGH. When SSP goes HIGH the RSFF 40 resets and the output Q goes LOW. This Q output signal of RSFF 42 is used as the enable signal for the oscillator 38 and mux 40 shown in Figure 12.

Figure 16 illustrates an example of the oscillator 38 in the form of an RC (resistor-capacitor) oscillator with an enable circuit. The oscillator comprises p-type TFT's 44,46,48,50, and 52, n-type TFT's 54,56 and 64, a resistor 60 and a capacitor 58. The sources of TFT's 44,52 and 46, are connected to high supply reference voltage VDD.

The gate of TFT 46 is connected to low supply reference voltage VSS. The sources of TFT's48 and So are connected to drain of TFT 46. The gates of TFT's 44,52 and 48 arc connected to drain of TFT 44 via switch 64 controlled by EN and to a terminal of resistor 60. The other terminal of resistor 60 is connected to VSS. The drain of TFT 52 is' connected to a top plate of capacitor 58, to the gate of TFT 50 and to the drain of TFT 64. The bottom plate of capacitor 58 is connected to VSS. The sources of TFT's 56,54 and 64 are connected to VSS. The gates of TFT's 56 and 54 are connected to drain of TFT 56 and drain of TFT 48. The drain of TFT 5Ois connected to drain of TFT 54 and to input IN of delay circuit 66. A delay circuit can be any known delay circuit or series of conventional inverters. The output OUT of delay circuit 66 is connected to gate of TFT 64. A switch 62 (controlled by!EN) is connected between VDD and gates of TFT's 44,52 and 48. Switches 62 and 64 can he complementary or p-type or n-type TFT's.

The circuit shown in Figure 16 is a typical current controlled RC oscillator. The TFT's 46, 48, 50, 54 and 56 form a conventional differential pair comparator. The current flowing in one arm of the input current mirror (formed by TFT's 44 and 52) is set by means of the resistor 60. The mirrored current is used to charge a capacitor 58. When the voltage across the capacitor is equal to the voltage across resistor 60, the comparator trips. The output of the comparatQr is delayed by delay circuit 66 and then used to reset the capacitor by TFT 64.

The switches 62 and 64 form the enable circuit for the oscillator. When EN is HIGH, the switch 64 is closed forming connection between resistor 60, the drain of p-type TFT 44 and the gale of p-type TFT's 52 and 48. When!EN is low, switch 62 is open. This Ibrms a current mirror circuit copying current through the resistor 60 to p-type TFT 52 via p-type TFT 44 and charges the capacitor 58 and hence the oscillator is turned ON.

When EN is LOW and!EN is HIGH switch 62 is closed and gale of p-type TFT's 44 and 52 are connected to supply voltage VDD turning TFT's 44 and 52 OFF. Since EN is LOW switch 64 is open and disconnects the current mirror, no current flows onto capacitor 58 and hence the oscillator is turned OFF.

The circuit of a typical DC-DC converter suitable for use as the converter 36 in Figure 12 is shown in Figure 17. II comprises n-type TFT's 68 and 70, p-type TFT's 72 and 74 and capacitors 76 and 78. The drains of the TFT's 68 and 70 arc connected to the high supply reference voltage VDD. The gale of the TFT 68 is connected to the source of the TFT 70, to the drain of the TFT 74, to the gate of the TFT 72 and to the top plate of the capacitor 78. The gate of the TFT 70 is connected to the source of the TFT 68, to the drain of the TFT 72, to the gate of the TFT 74 and to the top plate of the capacitor 76.

The sources of the TFTs 72 and 74 are connected to top plate of a tank capacitor 80.

CKI & CK2 are non-overlapping clocks which can be generated by any suitable circuit and a typical circuit is shown in Figure 1 8. Typically the delay block comprises a series of inverters. The timing diagram of the generated non overlapping clocks is shown in Figure 19. These generated non-overlapping clocks are applied to the bottom plate of the capacitors 76 and 78.

The circuit shown in Figure 17 is a positive DC-DC charge pump circuit. When CK I is high, node X is pulled to VDD and node Y to VDD-Vth (Vth is the threshold voltage of TFT 68). When CK2 rises, node Y is boosted to 2x VDD-Vth and, when CKI rises for a second time, X is boosted to 2x VDD. The transistors 72 and 74 connect the output node VOUT to the tank capacitor 80, which transfers the boosted voltage on node Y and node X to the tank capacitor 80 respectively.

Claims (14)

1. CLAIMS: 1. A DC-DC converter arrangement comprising a converter having

   an input for receiving an energising signal, an oscillator and a selecting circuit arranged: to disable the oscillator and to supply to the converter input a system clock signal or a signal derived therefrom when the system clock signal is active: and to enable the oscillator and to supp'y an output signal of the oscillator to the converter input when the system clock signal is inactive.
2. 2. An arrangement as claimed in claim I, in which the selecting circuit is arranged to stop the oscillator when the system clock signal is active.
3. 3. An arrangement as claimed in claim I or 2, in which the selecting circuit is arranged to enable the oscillator be!bre the system clock signal becomes inactive.
4. 4. An arrangement as claimed in any one of the preceding claims, in which the oscillator comprises a current mirror having an input connected to a resistor and an output connected to a capacitor, and a comparator arranged to discharge the capacitor afler the voltage thereacross reaches a predetermined value.
5. 5. An arrangement as claimed in claim 4, in which the selecting circuit is arranged to disable the current mirror when the system clock signal is active.
6. 6. An arrangement as claimed in any one of the preceding clainis, in which the selecting circuit comprises a multiplexer.
7. 7. A display driver comprising an arrangement as claimed in any one of the preceding claims.
8. 8. A driver as claimed in claim 7, in which the selecting circuit comprises a histable circuit arranged to he set into a first stale by each Irame refresh start pulse and to be set into a second state by each final scanning pulse of each frame.
9. 9. A driver as claimed in claim 8, in which the bistable circuit is a reset-set flip-flop.
10. 10. A driver as in any one of claims 7 to 9, in which the system clock signal is inactive during each frame blanking period.
11. 11. A driver as claimed in any one of claims 7 to 9, comprising an active matrix driver.
12. 12. A display comprising a driver as claimed in any one of claims 7 to II.
13. 13. A display as claimed in claim 12, in which the arrangement is formed on a substrate of the display.
14. 14. A display as claimed in claim 12 or 13, comprising a liquid crystal display.