JP2010145737A - Driver circuit, electrooptical apparatus, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably discharge facing electrodes when a panel is not operating. <P>SOLUTION: The drive circuit to supply the voltage to the electrodes facing each other has an internal power supply voltage generator circuit to generate the internal power supply voltage VLDO2 based on the external power supply voltage VDD2, a first discharging means (Tr3, R) to discharge the output line, a switching circuit 320 to alternately output the voltages VCOMH, VCOML based on the polarity flip signal, second discharging means (MV1, MV2) to discharge to make the voltage of the VCOM supply line 303 become the reference voltage VSS during the initial discharging period when moving to the sleep mode, and first reference voltage holding means (HV1, HV2, R1) maintaining the VCOM supply line voltage through at least from during the discharging period to the period after the discharging. The first discharging means delays the discharging so that the voltage supply line is discharged by the second discharging means during the discharging period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a drive circuit that drives a counter electrode such as a liquid crystal panel, an electro-optical device, and an electronic apparatus.

  A flat panel such as a liquid crystal panel has low power consumption and can be miniaturized, so that its use as a display device is expanding. As the application expands, the external power supply potential supplied from the outside to the drive circuit for driving the panel is also diversified.

  For example, in a product for mobile phones, the external power supply potential is about 3V, for example. However, in a vehicle-mounted product mounted on an automobile, the external power supply potential supplied from the vehicle battery is, for example, about 5V.

  Here, when the panel is not driven (for example, in a sleep state), the counter electrode potential supply line is discharged (for example, refer to claim 2 of Patent Document 1). Japanese Patent Application Laid-Open No. 2004-228561 discharges the electric charge of the counter electrode potential supply line when the panel is not driven, because of special driving in which the counter electrode is floated when the panel is driven.

However, particularly when the counter electrode potential is inverted based on the polarity inversion signal, a distorted image is displayed by setting the counter electrode to an unexpected potential due to residual charge immediately after the transition to non-drive. It is feared that Therefore, it is preferable to discharge the counter electrode potential supply line when the panel is not driven.
JP-A-8-263021

  When the external power supply potential is about 3V as in the product for mobile phones, the discharge transistor is supplied by supplying the external power supply potential as the ON potential to the gate of the discharge transistor immediately after the transition to the non-simultaneous drive mode of the panel. Can be reliably turned on. Thereby, the counter electrode can be reliably discharged.

  On the other hand, in a vehicle-mounted product, the external power supply potential is as high as 5V, for example. For example, in a discharge transistor in which a negative counter electrode potential line is connected to the source, if this external power supply potential is applied to the gate of a normal breakdown voltage discharge transistor, the breakdown voltage will be exceeded. Therefore, in this case, it is conceivable that an internal power supply potential is once generated by a regulator or the like based on the external power supply potential, and this internal power supply potential is supplied to the gate of the discharge transistor as an ON potential.

  However, since the internal power supply potential drops to 0 V when the panel is not driven, the on-operation of the discharge transistor cannot be continued.

  Accordingly, an object of some aspects of the present invention is to generate an internal power supply potential from an external power supply potential, and reliably discharge the counter electrode when the panel is not driven using the internal power supply potential and the external power supply potential. It is an object to provide a driving circuit, an electro-optical device, and an electronic apparatus that can perform the above-described operation.

One embodiment of the present invention provides:
In a drive circuit for supplying a counter electrode potential to a counter substrate, which is one substrate of a panel in which an electro-optic element is interposed between two substrates,
An internal power supply potential generating circuit for generating an internal power supply potential based on the external power supply potential;
First discharge means for discharging an output line of the internal power supply potential generation circuit;
A switching circuit that alternately switches a positive first counter electrode potential and a negative second counter electrode potential based on a polarity inversion signal and outputs the same to a counter electrode potential supply line;
In the initial discharge period of the transition from the driving mode for driving the panel to the non-driving mode for not driving the panel, the potential of the counter electrode potential supply line is equal to the reference potential between the first and second counter electrode potentials. Second discharge means for discharging the counter electrode potential supply line based on the internal power supply potential,
A first holding the potential of the counter electrode potential supply line set to the reference potential by the second discharge means at least during the non-drive of the panel and after the discharge period elapses. A reference potential holding means;
Have
The first discharge means relates to a drive circuit that delays discharge of the output line of the internal power supply potential generation circuit so that the counter electrode potential supply line is discharged by the second discharge means during the discharge period.

  According to one aspect of the present invention, the discharge operation of the counter electrode potential supply line is shared by the second discharge means and the first reference potential holding means. The second discharge means performs a discharge operation in the initial discharge period after shifting to the non-drive mode, and the first reference potential holding means operates in a period overlapping with the discharge period, and sets the reference potential even after the discharge period has elapsed. The potential of the counter electrode potential supply line is held. Thus, even if the output line of the internal power supply potential generation circuit is discharged by the first discharge means and the discharge operation by the second discharge means is completed, the potential of the counter electrode potential supply line is changed to the reference potential by the first reference potential holding means. Can be maintained.

  In one aspect of the present invention, the second discharge means is provided between the counter electrode potential supply line and a reference potential line in which the reference potential is set, and the internal power supply potential is applied to a gate to A first discharge transistor that is turned on during a discharge period and is turned off after the discharge period elapses as the internal power supply potential decreases can be included.

  The internal power supply potential is eventually lowered by the first discharge means, and the first discharge transistor is turned off, but the counter electrode potential supply line set to the reference potential by the first reference potential holding means before the off-drive operation. Can be maintained.

  In one aspect of the present invention, the first reference potential holding means applies the external power supply potential to the gate as an ON potential in the non-driving mode, and at the initial stage of the discharge period, the first reference potential holding means uses a reverse bias potential to the back gate. It may include a first potential holding transistor that is turned off when the value voltage is rising, and is turned on when the reverse bias potential is relaxed by shifting to the non-driving mode at least at the end of the discharge period.

  As described above, in the first potential holding transistor, the reverse bias potential to the back gate fluctuates with the shift to the non-driving mode, whereby the threshold voltage fluctuates to turn on / off the first potential holding transistor. Can be turned off. Thus, at least at the end of the discharge period in which the first discharge transistor or the like operates, the potential of the counter electrode potential supply line set to the reference potential can be held by turning on the first potential holding transistor. .

  In one aspect of the present invention, the first reference potential holding unit includes a first pull-down resistor connected between the counter electrode potential supply line and a reference potential line in which the reference potential is set. it can.

  Since the common electrode potential supply line and the standard potential supply line, both of which become the reference potential during the discharge period, are short-circuited by the first pull-down resistor, the potential of the common electrode potential supply line set to the reference potential is held. be able to. Further, if the first pull-down resistor is a high resistance, the current flowing through the first pull-down resistor can be almost ignored even when the panel is driven.

  In one aspect of the present invention, the second discharge means includes a first discharge transistor provided between the counter electrode potential supply line and a second counter electrode potential line that supplies the second counter electrode potential; A second discharge transistor provided between the second counter electrode potential supply line and a reference potential line in which the reference potential is set, and each of the first and second discharge transistors includes An internal power supply potential may be applied to the gate and driven on during the discharge period, and may be turned off after the discharge period elapses as the internal power supply potential decreases.

  In this way, since the second counter electrode potential supply line can be discharged in addition to the counter electrode potential supply line, it is possible to eliminate the problem that the charge of the second counter electrode potential supply line is supplied to the panel when not driven.

  In one aspect of the present invention, the first reference potential holding means includes a first potential holding transistor provided between the counter electrode potential supply line and the second counter electrode potential line, and the second counter electrode. A first potential holding transistor provided between a potential supply line and a reference potential line in which the reference potential is set, and each of the first and second potential holding transistors is not driven In the mode, the external power supply potential is applied to the gate as an ON potential, and at the beginning of the discharge period, the threshold voltage increases due to the reverse bias potential to the back gate, and the OFF operation is performed, and at least at the end of the discharge period The reverse bias potential may be relaxed and turned on by shifting to the non-driving mode.

  Even when the first and second discharge transistors are provided as the second discharge means, the first reference potential holding means is connected between the counter electrode potential supply line and the reference potential line. Pull-down resistor. The first pull-down resistor may be provided between the counter electrode potential supply line and the second counter electrode potential supply line and between the second counter electrode potential supply line and the reference potential line.

  In one aspect of the present invention, the internal power supply potential is inverted and boosted with reference to the reference potential, and the boosted potential is output to a storage capacitor connected between the boosted potential output line from which the boosted potential is output and the reference potential line A discharge circuit connected in parallel to the storage capacitor, a boosting circuit for charging a potential, a second counter electrode potential generating circuit for generating the second counter electrode potential based on the internal power supply potential and the boosted potential; In addition, third discharge means for discharging based on the internal power supply potential so that the potential of the counter electrode potential supply line becomes the reference potential, and connected in parallel to the storage capacitor, when the panel is not driven. Before the reference potential is set to the reference potential by the third discharge means at least from the discharge period to the end of the discharge period. A second reference potential holding means for holding the potential of the counter electrode voltage supply line may further comprise a.

  In this way, the output line of the booster circuit can be discharged by the third discharge means and the second reference potential holding means in the same manner as described above. For this reason, it is possible to prevent residual charges on the output line of the booster circuit from flowing into the second counter electrode supply line.

  In one aspect of the present invention, the third discharge means, like the second discharge means, is applied with the internal power supply potential applied to the gate and is turned on during the discharge period. A third discharge transistor that is turned off after the discharge period has elapsed may be included. Alternatively, similar to the first reference potential holding means, the second reference potential holding means applies the external power supply potential to the gate as an ON potential in the non-driving mode, and at the initial stage of the discharge period, A third potential holding transistor that is turned off when the threshold voltage is increased by the reverse bias potential and is turned off at least at the end of the discharge period, and the reverse bias potential is relaxed by the transition to the non-driving mode; Can be included. Alternatively, the second reference potential holding unit may include a second pull-down resistor connected in parallel to the holding capacitor, like the first reference potential holding unit.

  In one aspect of the present invention, the discharge operation start timing of the first discharge means can be set later than the discharge operation start timing of the second discharge means. Alternatively, the discharge operation start timing of the first discharge means and the discharge operation start timing of the second discharge means are substantially the same, and the discharge speed of the first discharge means is delayed in the first discharge means. A time constant may be set. In any case, the first discharge unit delays the discharge of the output line of the internal power supply potential generation circuit so that the counter electrode potential supply line is discharged by the second discharge unit during the discharge period. Can do.

  An electro-optical device according to another aspect of the present invention includes a panel including an electro-optical element driven by a plurality of scanning lines and a plurality of data signal lines, and a driving circuit according to one aspect of the present invention. Defined. Further, it is defined that an electronic apparatus according to still another aspect of the invention includes such an electro-optical device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

(Display unit)
FIG. 1A is a plan view of a vehicle-mounted display unit (an electro-optical device in a broad sense) according to this embodiment, and FIG. 1B is a schematic side view. The in-vehicle display unit 10 includes a panel 20 and a driver IC 100.

  The liquid crystal panel 20 is an amorphous Si-TFT liquid crystal panel having 320 × 320 pixels, for example, the number of pixels in the X direction = 320 and the number of pixels in the Y direction = 320. Each pixel of the liquid crystal panel 20 includes a thin film transistor (TFT) T having a gate connected to a scanning line (gate line) G and a source connected to a data signal line (source line) S, as shown in FIG. The storage capacitor C, the pixel electrode P, and the like are included. The liquid crystal panel 20 includes 320 scanning lines G extending along the X direction and equally spaced in the Y direction, and 320 scanning lines G extending along the Y direction and equally spaced in the X direction. Data signal line S. As shown in FIG. 1B, the liquid crystal panel 20 includes an active matrix substrate 21 on which scanning lines G, data signal lines S, thin film transistors T, pixel electrodes P, and the like are formed, and an opposing surface that faces all the pixel electrodes P. A liquid crystal 23, which is an electro-optical element, is sealed between the counter substrate 22 on which electrodes are formed.

  A driver IC 100 shown in FIG. 1 sets each pixel of the liquid crystal panel 20 to, for example, 2 gradations, 4 gradations, and 16 gradations based on a command from an MPU (Micro Processor Unit) (not shown), parameters or data following the command. This is a one-chip driver IC that can be driven in any BPP (Bit Per Pixel) mode. As shown in FIG. 1B, the driver IC 100 can have bumps corresponding to COG (Chip on Glass) that can be directly mounted on a wiring region on an active matrix substrate (glass substrate) 21, for example. Thus, a display module (also an electro-optical device) can be configured by the liquid crystal panel 20 and the driver IC 100. Alternatively, the driver IC 100 may be mounted on a flexible substrate connected to the active matrix substrate 21.

(Driver IC)
FIG. 3 is a block diagram of the driver IC 100. In FIG. 3, a system interface 102 is an interface for inputting and outputting signals to and from the MPU. The system interface 102 includes various power supply terminals, input / output terminals, control terminals, external terminals, and the like.

The control logic circuit 104 includes a decoder / register for a command / parameter from a data bus terminal or a serial data input terminal. The multi-time PROM 106, which is a non-volatile memory, is used to adjust the offset of the electronic volume for the voltage value VCOMH applied to the counter electrode, for example, as control data specific to the liquid crystal panel 20 to which the driver IC 100 is connected, such as image quality adjustment data. Control data and the like are stored. Thus, by storing control data unique to the liquid crystal panel 20 in the driver IC used as a set with the liquid crystal panel 20, image quality adjustment can be performed in units of display modules composed of the liquid crystal panel 20 and the driver IC 100. It becomes possible. The driver IC 100 or MPU is connected to a non-volatile memory having a capacity larger than that of the multi-time PROM 106, for example, E ² PROM, and can store control data other than control data unique to the liquid crystal panel 20. The multi-time PROM 106 can be electrically rewritten up to about 5 times, and can store user ID data and the like in addition to the image quality adjustment data described above. The oscillation circuit 108 generates a reference clock inside the driver IC 100.

  The driver IC 100 includes a display data RAM 110 that stores display data. In the present embodiment, in order to display each pixel of 320 × 320 with the maximum number of gradations 16 (4 BPP), the storage capacity is 320 × 320 × 4 bits. That is, the display data RAM 110 can store display data for at least one frame in the 4BPP mode. If the number of gradations per pixel decreases, the display data for one frame decreases, and the number of frames of display data that can be stored in the RAM 110 increases in inverse proportion to the number of bits of BPP (Bit Per Pixel). That is, in 2 BPP (4 gradations), one frame data is 320 × 320 × 2 bits, so that the display data RAM 110 can store display data for two frames. Similarly, in 1 BPP (2 gradations), one frame data is 320 × 320 × 1 bit, and therefore display data for four frames can be stored in the display data RAM 110.

  As peripheral circuits of the display data RAM 110, an I / O buffer 112, a display timing generation circuit 114, a page address circuit 116, a column address circuit 118, and a line address circuit 120 are provided. Data is input / output between the MPU and the display data RAM 110 via the system interface 102, the control logic 104, and the I / O buffer 112. The control logic 104 can include a write bus holder, a read bus holder, and the like in addition to various decoders and registers.

  As for the address of the display data RAM 110, a page address circuit 116 and a column address circuit 118 are used when inputting / outputting display data to / from the MPU, and a line address circuit 120 is used when driving the liquid crystal panel 20. Timing signals from the display timing generation circuit 114 are input to these address circuits 116-120.

  In order to drive the liquid crystal panel 20 based on the display data in the display data RAM 110, a display data latch circuit 122 and a source driver (driver circuit in a broad sense) 130 for driving 320 source lines S are provided.

  A power supply circuit 140 that supplies a potential to each part of the driver IC 100 is provided. The power supply circuit 140 generates and supplies a necessary potential to each part of the driver IC 100 based on a potential supplied from the outside. The power supply circuit 140 includes a gamma circuit 140D (see FIG. 4) for supplying a gradation voltage to a digital-analog conversion circuit (DAC) provided in the source driver 130. The driver IC 100 includes gate drivers 142A and 142B that drive 320 gate lines G.

(Overall layout of driver IC)
FIG. 4 shows an example of the overall layout of the driver IC 100. The regions divided into three in the longitudinal direction X of the driver IC are defined as a central first region 100A and left and right second and third regions 100B and 100C. In the present embodiment, the source driver 130 is disposed in the first region 100A, the gate driver 142A is disposed in the second region 100B, and the gate driver 142B is disposed in the third region 100C along one side of the driver IC 100. . The display data RAM 110 connected to the source driver 130 is arranged in the first area 100A. A system interface 102 including various pads is arranged along the other side of the driver IC 100 over the first to third regions 100A to 100B.

  The power supply circuit 140 is divided and arranged in the first region 100A, the second region 100B, and the third region 100C. In the first region 100A, a booster circuit 140A is disposed adjacent to the system interface 102. In the second region 100B, a main power supply circuit (first power supply circuit) 140B that generates an internal reference potential and various operating potentials is disposed adjacent to the system interface 102. In the third region 100C, a VCOM generation circuit (second power supply circuit) 140C for generating the counter electrode potential VCOM is provided adjacent to the system interface 102. Since the power supply circuit 140 is connected to the pad of the system interface 102, it is disposed adjacent to the system interface 102 in order to reduce impedance. Note that a gamma circuit 140D and a control logic circuit 104 are further arranged in the second region 100B. In the present embodiment, for example, a Vref potential or a VREG potential is supplied as an internal reference potential from the main power supply circuit 140B to the VCOM generation circuit 140C via the internal power supply wirings 141A and 141B. The internal power supply wirings 141A and 141B are formed as the uppermost layer of a multilayer wiring, for example, a five-layer wiring, and a shield layer can be disposed in a wiring layer (for example, four layers) immediately below the inner wiring. Further, the power supply wiring of the ground potential VSS can be arranged on both sides of the internal power supply wirings 141A and 141B to reduce the influence of noise. Further, the internal reference potential Vref is input to the third region 100C, and a VLDO1 regulator (internal power supply potential generation circuit) 140E and an VLDO2 regulator 14F (internal power supply) that generate internal power supply potentials VLDO1 and VLDO2 based on the external power supply potential VDD2. A potential circuit) is further provided.

(Power circuit)
FIG. 5 is a block diagram of the power supply circuit 140. 5, for example, a primary booster circuit 210, a secondary booster circuit 220, a tertiary booster circuit 230, and a fourth booster circuit 240 are provided as the booster circuit 140A disposed in the first region 100A of FIG. Other internal reference potential generation circuits except for the boost circuits 210 to 240 arranged in the first region 100A and the VCOM generation circuit 140C, VLDO1 regulator 140E and VLDO2 regulator 140F arranged in the third region of FIG. 200, various regulators 201-1 to 201-7, and a power supply control circuit 202 are arranged in the second region 100B. The power supply control circuit 202 includes a register, a timer, and the like.

  Here, in the present embodiment, the internal reference potential generation circuit 200 is provided only in the main power supply circuit arranged in the second region 100B, and the internal reference potential generation circuit 200 is not provided in the third region 100C. Therefore, the internal reference potential Vref is transmitted from the internal reference potential generation circuit 200 disposed in the second region 100B to the first internal power supply potential generation circuits 140E and 140F disposed in the third region 100C via the internal power supply wiring 141B. is doing. As described above, since the power supply circuit 140 is divided and the internal reference potential generation circuit 200 is provided in only one of them, it is not necessary to overlap the reference potential generation circuit in each divided region, and the chip area increases. do not do.

  FIG. 6 shows the relationship between various potentials generated by the internal reference potential generation circuit 200, the various regulators 201-1 to 201-7, and the booster circuits 210 to 240. In FIG. 6, the external power supply potential is VDD2 (for example, about 5V) and VSS (0V). The internal reference potential generated by the internal reference potential generation circuit 200 includes a VCOM generation reference potential Vref (for example, 1.5 V), a logic potential VDD (for example, 1.8 V), VREG, and the like.

  Based on these external potentials VDD2, VSS and internal reference potentials VLDO1, VLDO2, Vref, VDD, etc., operating voltages are generated by the various regulators 201-1 to 201-7 and booster circuits 210 to 240.

  The operation in the booster circuit 140A will be described. The primary booster circuit 210 boosts the primary boost reference potential VLDO1 by, for example, twice to generate a potential VOUT (eg, 6.1 V). The secondary booster circuit 220 multiplies the secondary boost reference potential VLDO2 by (−1) to generate a potential VOUTM (for example, −2.5 V) used for generating the second counter electrode potential VCOML. The tertiary booster circuit 230 multiplies the input voltage (VOFREG) by (−n) with respect to the potential VOUTM to generate a gate driver negative power supply potential VEE (for example, −15 V). The fourth booster circuit 240 generates the gate driver positive power supply potential VDDHG by multiplying the input voltage (VONREG-VEE) by 1 with respect to the potential VONREG. Each of these booster circuits 210, 220, 230, and 240 can be configured by a charge pump type DC / DC converter or the like.

(Circuit for generating counter electrode potential VCOM)
FIG. 7 shows an example of the VLDO2 regulator 140F, the secondary booster circuit 220, and the VCOM generation circuit 140C as circuits related to the generation of the common electrode potential VCOM.

  Based on the polarity inversion signal, the VCOM generation circuit 140C switches between a first counter electrode potential VCOMH (eg, + 4V) that is a positive potential and a second counter electrode potential VCOML (eg, −1V) that is a negative potential. Is. In the present embodiment, a line inversion driving method, a frame inversion driving method, or the like can be adopted as the polarity inversion driving method. The VCOM generation circuit 140C includes a VCOMH regulator 300, a VCOML regulator 310, and a switching circuit 320.

  The VCOMH regulator 300 is supplied with a VOUT potential and a VSS potential as power supply potentials. The first counter electrode potential VCOMH is added to a fixed value from the register by adding an offset value from the multi-time PROM 106 through an unillustrated register as necessary, and the value is input by an electronic volume. It is determined based on the adjusted value.

  The VCOML regulator 310 is supplied with the potential VLDO2 from the VLDO2 regulator 140F and the boosted potential VOUTM from the secondary booster circuit 220 as power supply potentials. The second counter electrode potential VCOML can be set to satisfy VCOMH− (2 × VCA) (the potential VCA is generated by the power supply circuit 140).

  The switching circuit 320 includes two transistors Tr1 and Tr2 that are connected in series between the VCOMH potential supply line 301 and the VCOML potential supply line 302 and are complementarily turned on / off based on a polarity inversion signal. When the transistor Tr1 is turned on, the first counter electrode potential VCOMH is supplied to the counter electrode of the panel 20 alternatively via the VCOM potential supply line 303, respectively, when the transistor Tr2 is turned on.

  The VLDO2 regulator (internal power supply potential generation circuit) 140F is supplied with the external power supply potential VDD2 and VSS as the power supply potential, receives the internal reference potential Vref (for example, 1.5V) from the internal reference potential generation circuit 200, and receives the internal power supply. A potential VLDO2 (for example, 2.5 V) is generated. Note that the VLDO2 potential output line 221 that is the output line of the VLDO2 regulator 140F is grounded via the resistor R and the discharge transistor Tr3. The discharge transistor Tr3 is turned on by the gate signal C when the panel 20 is not driven, for example, in the sleep mode, and the VLDO2 potential output line 221 is driven in accordance with the RC time constant of the resistor R and a capacitor C (not shown). The potential is 0V. The configuration for discharging the VLDO2 potential output line 221 corresponds to the first discharge means.

  The secondary booster circuit 220 includes four transistors Tr4 to Tr7 connected in series between a VLDO2 potential output line 221 that is an output line of the VLDO2 regulator 140F and a VOUTM potential output line (boost potential output line) 222. The capacitor C1 is connected to the source / drain connection point of the transistors Tr4 and Tr5 and the source / drain connection point of the transistors Tr6 and Tr7. The capacitor (retention capacitor) C2 is connected between the ground line 223 and the VOUTM potential output line 222.

  In the secondary booster circuit 220, when the transistors Tr4 and Tr6 are turned on and the transistors Tr5 and Tr7 are turned off, the capacitor C1 is connected to the VLDO2 potential output line 221 and the ground line 223, and the potential of the VLDO2 potential output line 221 is 2.5V. Is charged. After that, when the transistors Tr4 and Tr6 are turned off and the transistors Tr5 and Tr7 are turned on, the capacitor C2 is connected to the VOUTM potential output line 222 and the ground line 223, and the charge of the capacitor C1 moves to the capacitor C2 to the capacitor C2. Is charged with -2.5V. By repeating this, + 2.5V charge is continuously charged in the capacitor C1, and −2.5V charge is continuously charged in the capacitor C2, and the potential of the VOUTM potential output line 222 is inverted from that of the VLDO2 potential output line 221. The boosted voltage is held at -2.5V.

(Embodiment 1 of Discharge for VCOM Potential Output Line)
In the present embodiment, the potential of the common electrode potential (VCOM) supply line 303 is changed during the initial discharge period from the driving mode in which the panel 20 is driven to the non-driving mode in which the panel 20 is not driven (for example, sleep mode). 1. Second discharge means for discharging the reference potential VSS between the first and second counter electrode potentials VCOMH and VCOML (for example, 0 V), for example, first and second discharge transistors MV1 and MV2, and when the panel 20 is not driven. The first reference potential holding means for holding the potential of the VCOM potential supply line 303 set to the reference potential VSS by the second discharge means MV1 and MV2 at least after the discharge period T1 elapses, for example, the first and second potential holdings. Transistors HV1 and HV2 (see FIG. 7). ).

  The first discharge transistor MV1 and the first potential holding transistor HV1 are connected in parallel between the VCOM supply line 303 and the VCOML supply line 302. The second discharge transistor MV2 and the second potential holding transistor HV2 are connected in parallel between the VCOML supply line 302 and the ground line (reference potential line) 304.

  Here, in this embodiment, the driver IC 100 is formed using three types of transistors having different breakdown voltages. A low-breakdown-voltage transistor LV whose gate-on potential operates at the logic reference potential VDD (= 1.8V), and a medium-breakdown-voltage transistor (for example, whose internal potential operates at the internal power supply potential VLDO2 (= 2.5V)). There are three types: a transistor MV having a breakdown voltage of 6.2V, and a transistor HV having a high breakdown voltage (for example, a breakdown voltage of 30V) that operates at an external power supply potential VDD2 (= 5V).

  The high breakdown voltage transistor HV has a twin well structure as shown in FIG. That is, for example, a P-type well NWELL is formed in a P-type substrate Psub, and an N-type impurity layer serving as a source / drain is formed in the P-type well PWELL. The P-type substrate Psub and the P-type well NWELL are set to the potential VEE (= −15V). The high breakdown voltage transistor HV used in the present embodiment has a breakdown voltage of, for example, 30V.

  The medium voltage transistor MV has a triple well structure as shown in FIG. That is, for example, an N-type well NWELL is formed in a P-type substrate Psub, a P-type well PWELL is formed in the N-type well NWELL, and an N-type impurity layer serving as a source / drain is formed in the P-type well PWELL. Yes. Since the P-type substrate Psub is set to the potential VEE, the N-type well NWELL is provided to separate the potential of the P-well PWELL from the P-type substrate Psub. In the first and second discharge transistors MV1 and MV2, the potential of the P well PWELL is set to −1V, and the N-type well NWELL is set to + 3V. The medium withstand voltage transistor MV used in this embodiment has a withstand voltage of, for example, 6.2V.

  Here, for a mobile phone, the external power supply potential VDD2 was 3.1 V at the maximum. Therefore, when the discharge transistor MV is used, VOUTM (maximum -3.1V) and VDD2 (maximum + 3.1V) are used as the gate voltages so that the breakdown voltage of the discharge transistor MV is within the range of 6.2V. I was able to stop.

  However, since the external power supply potential VDD2 is a maximum of 5.5V for in-vehicle use, the discharge transistor MV having the external power supply potential VDD2 as a gate potential cannot be used in terms of withstand voltage. Therefore, in this embodiment, the external power supply potential VDD2 is not used as the gate potential of the discharge transistor MV.

  FIG. 10 is a timing chart of the discharge operation of the counter electrode potential supply line. The signal A is a signal supplied to the gates of the first and second discharge transistors MV1 and MV2, and the ON potential is the VLDO2 potential and the OFF potential is the VOUTM potential. The signal B is a signal supplied to the gates of the first and second potential holding transistors HV1 and HV2, and the on potential is the VDD2 potential and the off potential is the VEE potential. The signal C is a signal supplied to the gate of the discharge transistor Tr3, and the ON potential is VDD2 potential and the OFF potential is VSS potential.

  FIG. 11 shows a circuit for generating signals A, B, and C. The power control circuit 202 is connected to the first to third level shifters 330 to 332. A signal A is output from the first level shifter 330, a signal B is output from the second level shifter 331, and a signal C is output from the third level shifter 332. Whether the signals A to C are turned on or off is determined based on the control signals CONT1 and CONT2 from the power supply control circuit 202. The first control signal CONT1 is input to the first and second level shifters 330 and 331, and the second control signal CONT2 is input to the third level shifter 332.

  In FIG. 10, before a non-driving mode signal such as a sleep signal is input, the signal A is the VOUTM potential, the signal B is the potential VEE, and the first and second discharge transistors MV1 and MV2 and the potential holding transistors HV1 and HV2 Are all off. The discharge transistor Tr3 for discharging the VLDO2 output line 221 is also turned off. Therefore, before the sleep signal is input, the first counter electrode potential VCOMH or the second counter electrode potential VCOML is output from the VCOM supply line 303 by the operation of the switching circuit 320 based on the polarity inversion signal.

  When the sleep signal is input, the signal A changes to the on potential VLDO2 and the signal B changes to the on potential VDD2 based on the first control signal CONT1 in FIG. 11 (see FIG. 10). However, the signal C shown in FIG. 10 rises later than the signals A and B on the basis of the second control signal CONT2 of FIG. 11 set by the setting of the timer or the like in the power supply control circuit 202. That is, in this embodiment, the discharge of the output potential VLDO2 of the VLDO2 regulator 140F is delayed.

  Here, since the ON potential VLDO2 of the signal A is the output potential of the VLDO2 regulator 140F that is an internal power supply circuit, it is preferably discharged during sleep. However, since the output potential VLDO2 is the ON potential of the first and second discharge transistors MV1 and MV2, the output potential VLDO2 is the threshold voltage of the first and second discharge transistors MV1 and MV2 in the initial stage of the sleep mode. If the value is lower than 1, the ON operation of the first and second discharge transistors MV1 and MV2 becomes very short, and the VCOM supply line 303 cannot be discharged.

  Therefore, in this embodiment, the discharge timing of the output potential VLDO2 of the VLDO2 regulator 140F, that is, the rising timing time t2 of the signal C is delayed. Therefore, the ON operation of the first and second discharge transistors MV1 and MV2 continues during the discharge period T1 from the time t0 to the time t2 when the sleep signal is input, and during that time, the VCOM supply line 303 is discharged. be able to.

  In the present embodiment, the first and second potential holding transistors HV1 and HV2 are turned on at time t1 before time t2, which is the end of the discharge period T1.

  Here, as shown in FIG. 8, the reverse bias potential VEE is applied to the first and second potential holding transistors HV1 and HV2 as the back gate, so the threshold voltage is high, and the on potential VDD2 Is applied to the gate, the first and second potential holding transistors HV1 and HV2 are not turned on.

  The reverse bias potential VEE is generated by the tertiary booster circuit 230. The operation of all booster circuits 140A including the tertiary booster circuit 230 is stopped when the panel is not driven such as in a sleep state. Here, if the tertiary booster circuit 230 is a charge pump type DC / DC converter or the like, similar to the secondary booster circuit 220 shown in FIG. 7, the transistor drive is stopped and the storage capacitor in the final stage is charged. The charge corresponding to the potential VEE is gradually discharged without being replenished.

  Therefore, as shown in FIG. 10, the potential VEE is gradually discharged after the sleep signal is input, and eventually reaches VSS (= 0 V). Therefore, in FIG. 9, since the reverse bias potential VEE to the back gates of the first and second potential holding transistors HV1 and HV2 gradually becomes 0V, the threshold voltage decreases accordingly, and at time t1, the reverse bias potential VEE decreases. 1, the second potential holding transistors HV1 and HV2 are turned on. If this time t1 is before the final time t1 of the discharge period T1, the discharge state of the VCOM supply line 303 can be maintained over the sleep period.

(Embodiment 2 of Discharge for VCOM Potential Output Line)
FIG. 12 is a timing chart of another discharge operation of the counter electrode potential supply line, and FIG. 13 is a diagram showing another gate signal generation circuit of the discharge transistor and the potential holding transistor.

  12 differs from FIG. 10 in that the rising timings of the signals A, B, and C are simultaneously set. For this purpose, as shown in FIG. 13, the first control signal CONT1 is input to the first, second, and third level shifters 330 to 332 together.

  In FIG. 12, the discharge transistor Tr3 shown in FIG. 7 is turned on by the gate signal C when the panel 20 is in the sleep mode, but at the time of RC between the resistor R and the capacitor C (not shown) (not shown). The fact that it takes time to discharge the potential of the VLDO2 potential output line 221 due to the constant is utilized. That is, the RC time constant that could be ignored in FIG. 10 is set large in FIG.

  Thus, as shown in FIG. 12, even when the timing signal C rises and the discharge transistor Tr3 shown in FIG. 7 is turned on, the potential of the VLDO2 potential output line 221 gradually decreases.

  Therefore, the first and second discharge transistors MV1 and MV2 continue to be turned on until time t2 when the VLDO2 potential of the VLDO2 potential output line 221 falls below the threshold voltage of the first and second discharge transistors MV1 and MV2. become. Therefore, the VCOM supply line 303 can be discharged by the first and second discharge transistors MV1 and MV2 from time t0 to t2.

  Also in FIG. 12, as in FIG. 10, the first and second potential holding transistors HV1 and HV2 are turned on at time t1. If this time t1 is before the final time t1 of the discharge period T1, the discharge state of the VCOM supply line 303 can be maintained over the sleep period.

(Embodiment 3 of Discharge for VCOM Potential Output Line)
FIG. 14 shows a modification of the second discharge means and the first reference potential holding means. In FIG. 14, the second discharge means includes a first discharge transistor MV1 provided between the VCOM supply line 303 and the ground line 304. That is, it is not always necessary to provide the first and second discharge transistors MV1 and MV2 as shown in FIG. Even in the example of FIG. 14, the first discharge transistor MV1 can be turned on and the VCOM supply line 303 can be discharged over the discharge period T1 by the control signals A and C of FIG. 10 or FIG.

  Similarly, a first potential holding transistor HV1 connected between the VCOM supply line 303 and the ground line 304 may be provided as the first reference potential holding means. That is, the first and second potential holding transistors HV1 and HV2 are not necessarily provided as shown in FIG. Even in the example of FIG. 14, the first potential holding transistor HV1 is turned on by the control signal B and the potential VEE shown in FIG. 10 or 12 before the discharge period T1 and after the discharge period T1. The VCOM supply line 303 can be discharged over a period.

(Embodiment 4 of Discharge for VCOM Potential Output Line)
FIG. 15 shows another modification of the second discharge means and the first reference potential holding means. FIG. 15 is the same as FIG. 14 in that the second discharge means includes a first discharge transistor MV provided between the VCOM supply line 303 and the ground line 304. However, unlike FIG. 13, the first potential holding means is configured by a pull-down resistor R <b> 1 connected between the VCOM supply line 303 and the ground line 304.

  As shown in FIG. 10 or FIG. 12, if the VCOM supply line 303 is discharged to 0 V within the discharge period T1, then the VCOM supply line 303 and the ground line 304 having the same potential are connected to the pull-down resistor R1. Therefore, the VCOM supply line 303 can be discharged over the sleep period.

  However, since the VCOM supply line is set to one of the first and second counter electrode potentials VCOMH and VCOML during driving, the pull-down resistor R1 needs to be a high resistance that allows a current of about several μA in a steady state.

  Also in the embodiment of FIG. 7, the first pull-down resistor R1 may be arranged between the VCOM supply line 303 and the ground line 304 instead of the first and second potential holding transistors HV1 and HV2. Alternatively, both the first and second potential holding transistors HV1 and HV2 may be replaced with the first pull-down resistor R1 in FIG.

(Secondary booster circuit discharge)
The secondary booster circuit 220 can be provided with third discharge means and second reference potential holding means. As shown in FIG. 7, the third discharge means is connected in parallel to the holding capacitor C2 of the secondary booster circuit 220, and in the discharge period T1, the internal power supply is set so that the potential of the VOUTM output line 222 becomes the reference potential. Discharging is performed based on the potential VLDO2. The second reference potential holding means is connected in parallel to the holding capacitor C2 and is set to the reference potential by the third discharge means when the panel 20 is not driven and at least from the discharge period T1 to after the discharge period T1 has elapsed. The potential of the output VOUTM output line 222 is maintained.

  In FIG. 7, the third discharge means includes a third discharge transistor MV3 to which the VLDO2 potential is applied as the on potential and the VSS potential is applied as the off potential. The second reference potential holding means includes a third potential holding transistor HV3 to which the external power supply potential VDD2 is applied as the on potential and the VEE potential is applied as the off potential.

  In this way, the potential of the VOUTM output line 222 can be discharged to the reference potential VSS (= 0V) as in FIG. 10 or FIG. This eliminates the fear that the residual charge of the VOUTM output line 222 flows to the VCOML supply line 302 via the VCOML regulator 310, and the display of the panel 20 is disturbed when the panel 20 is not driven by the residual charge of the VOUTM output line 222. Can be prevented.

  Here, the second reference potential holding means may be a second pull-down resistor R2 connected in parallel to the holding capacitor C2, as shown in FIG. The second pull-down resistor R2 is also a high resistance like the first pull-down resistor R1.

  Although the present embodiment has been described in detail as described above, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described together with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

  For example, in the sleep mode as the non-drive mode, for example, one frame after the sleep signal is input may be a black display image. In this case, the time t0 in FIG. 10 or 12 can be the timing after the end of one frame displayed in black. This is because it is necessary to supply the counter electrode potential VCOM to the panel 20 based on the polarity inversion signal during the one frame.

  The present invention is not necessarily limited to TFT liquid crystal, and can be widely applied to panel driver ICs using electro-optical elements including other various liquid crystals.

  Further, the electronic device is suitable as a display device or other device that is applied to a vehicle-mounted product or the like in which the external power supply potential VDD2 and the output of the secondary booster circuit VOUTM exceed the withstand voltage of the MV transistor.

FIG. 1A is a schematic plan view of a liquid crystal panel driven by a driver IC according to an embodiment of the present invention, and FIG. 1B is a schematic side view thereof. It is a figure which shows one pixel of a liquid crystal panel. 1 is a block diagram of a driver IC according to an embodiment of the present invention. It is a plane layout view of a driver IC. It is a block diagram of a power supply circuit. It is a figure for demonstrating the relationship of the various electric potential used in this embodiment. It is a circuit diagram showing an example of a circuit related to generation of counter electrode potential VCOM. It is sectional drawing of a high voltage | pressure-resistant transistor. It is sectional drawing of a medium voltage transistor. It is a timing chart of the discharge operation of the counter electrode potential supply line. It is a figure which shows the gate signal generation circuit of a discharge transistor and a potential holding transistor. 10 is a timing chart of another discharge operation of the counter electrode potential supply line. It is a figure which shows the other gate signal generation circuit of a discharge transistor and a potential holding transistor. It is a figure which shows the modification of a 2nd discharge means and a 1st electric potential holding means. It is a figure which shows the further another modification of a 2nd discharge means and a 1st electric potential holding means. It is a figure which shows the modification of a 3rd discharge means and a 2nd electric potential holding means.

Explanation of symbols

10 display unit, 20 liquid crystal panel, 100 driver IC, 100A first area, 100B second area, 100C third area, 102 system interface,
104 control logic, 106 multi-time PROM, 108 oscillation circuit,
110 display data RAM, 112 I / O buffer,
114 display timing generation circuit, 116 page address circuit,
118 column address circuit, 120 line address circuit,
120A BPP setting register, 120B display line counter,
120C display line address converter, 120C1 frame address generation circuit,
120C2 adder, 120D data selector control signal generator,
122 display data latch circuit, 130 source driver (driver circuit),
140 power supply circuit, 140A booster circuit, 140B main power supply circuit (first power supply circuit),
140C VCOM generation circuit (second power supply circuit), 140D gamma circuit,
140E VLDO1 regulator, 140F VLDO2 regulator,
142A, 142B gate driver, 200 internal reference potential generation circuit,
201-1 to 201-7 regulator, 202 power supply control circuit,
210 primary booster circuit, 220 secondary booster circuit, 221 VLDO2 potential output line,
222 VOUTM output line, 223 ground line, 230 tertiary booster circuit,
240 fourth-order voltage booster circuit, 300 VCOMH regulator, 301 VCOMH supply line,
302 VCOML supply line, 303 VCOM supply line,
310 VCOML regulator, 320 switching circuit,
330 to 332 first to third level shifters,
MV1 to MV2 First to second discharge transistors (second discharge means), MV3 Third discharge transistor (third discharge means), HV1 to HV2 First to second potential holding transistors (first reference potential holding means) ), HV3 third potential holding transistor (second reference potential holding means), R1 first pull-down resistor, R2 second pull-down resistor, Tr1, R first discharge means, VCOM counter electrode potential, VCOMH first counter electrode potential, VCOML Second counter electrode potential

Claims (15)

In a drive circuit for supplying a counter electrode potential to a counter substrate, which is one substrate of a panel in which an electro-optic element is interposed between two substrates,
An internal power supply potential generating circuit for generating an internal power supply potential based on the external power supply potential;
First discharge means for discharging an output line of the internal power supply potential generation circuit;
A switching circuit that alternately switches a positive first counter electrode potential and a negative second counter electrode potential based on a polarity inversion signal and outputs the same to a counter electrode potential supply line;
In the initial discharge period of the transition from the driving mode for driving the panel to the non-driving mode for not driving the panel, the potential of the counter electrode potential supply line is equal to the reference potential between the first and second counter electrode potentials. Second discharge means for discharging the counter electrode potential supply line based on the internal power supply potential,
A first holding the potential of the counter electrode potential supply line set to the reference potential by the second discharge means at least during the non-drive of the panel and after the discharge period elapses. A reference potential holding means;
Have
The first discharge means delays the discharge of the output line of the internal power supply potential generation circuit so that the counter electrode potential supply line is discharged by the second discharge means during the discharge period. . In claim 1,
The second discharge means is provided between the counter electrode potential supply line and a reference potential line in which the reference potential is set, and the internal power supply potential is applied to a gate and is turned on in the discharge period. A drive circuit comprising: a first discharge transistor that is turned off after the discharge period elapses as the internal power supply potential decreases. In claim 1 or 2,
In the first reference potential holding means, the external power supply potential is applied to the gate as an ON potential in the non-driving mode, and the threshold voltage is increased by the reverse bias potential to the back gate at the beginning of the discharge period. A drive circuit comprising a first potential holding transistor that is turned off and is turned on when the reverse bias potential is relaxed by shifting to the non-drive mode at least at the end of the discharge period. In claim 1 or 2,
The drive circuit according to claim 1, wherein the first reference potential holding means includes a first pull-down resistor connected between the counter electrode potential supply line and a reference potential line in which the reference potential is set. In claim 1,
The second discharge means includes
A first discharge transistor provided between the counter electrode potential supply line and a second counter electrode potential line for supplying the second counter electrode potential;
A second discharge transistor provided between the second counter electrode potential supply line and a reference potential line in which the reference potential is set;
Including
Each of the first and second discharge transistors is turned on during the discharge period when the internal power supply potential is applied to the gate, and is turned off after the discharge period elapses as the internal power supply potential decreases. Drive circuit. In claim 5,
The first reference potential holding means is
A first potential holding transistor provided between the counter electrode potential supply line and the second counter electrode potential line;
A first potential holding transistor provided between the second counter electrode potential supply line and a reference potential line in which the reference potential is set;
Including
In each of the first and second potential holding transistors, the external power supply potential is applied to the gate as an ON potential in the non-driving mode, and a threshold voltage is applied by a reverse bias potential to the back gate at the beginning of the discharge period. The driving circuit is characterized in that it is turned off and is turned off, and at least at the end of the discharge period, the reverse bias potential is relaxed and turned on by shifting to the non-driving mode. In claim 5,
The driving circuit according to claim 1, wherein the first reference potential holding means includes a first pull-down resistor connected between the counter electrode potential supply line and the reference potential line. In any one of Claims 2 thru | or 7,
A booster circuit that inverts and boosts the internal power supply potential with reference to the reference potential, and charges the boosted potential to a storage capacitor connected between the boosted potential output line from which the boosted potential is output and the reference potential line; ,
A second counter electrode potential generating circuit for generating the second counter electrode potential based on the internal power supply potential and the boosted potential;
A third discharge means connected in parallel to the storage capacitor and discharging based on the internal power supply potential so that the potential of the counter electrode potential supply line becomes the reference potential during the discharge period;
The counter electrode potential supply which is connected in parallel to the storage capacitor and is set to the reference potential by the third discharge means at least during the discharge period and after the discharge period has elapsed, when the panel is not driven. Second reference potential holding means for holding the potential of the line;
A drive circuit further comprising: In claim 8,
The third discharge means includes a third discharge transistor that is turned on during the discharge period when the internal power supply potential is applied to the gate and is turned off after the discharge period elapses as the internal power supply potential decreases. A drive circuit characterized. In claim 8 or 9,
In the second reference potential holding means, the external power supply potential is applied to the gate as an ON potential in the non-driving mode, and the threshold voltage is increased by the reverse bias potential to the back gate at the beginning of the discharge period. A drive circuit comprising: a third potential holding transistor which is turned off and turned on when the reverse bias potential is relaxed by shifting to the non-drive mode at least at the end of the discharge period. In claim 8 or 9,
The drive circuit according to claim 2, wherein the second reference potential holding means includes a second pull-down resistor connected in parallel to the holding capacitor. In any one of Claims 1 thru | or 11,
The drive circuit according to claim 1, wherein a discharge operation start timing of the first discharge means is set later than a discharge operation start timing of the second discharge means. In any one of Claims 1 thru | or 11,
The discharge operation start timing of the first discharge means and the discharge operation start timing of the second discharge means are substantially the same,
The drive circuit according to claim 1, wherein a time constant for delaying a discharge speed of the first discharge means is set in the first discharge means. A panel including an electro-optic element driven by a plurality of scanning lines and a plurality of data signal lines;
A drive circuit according to any one of claims 1 to 13,
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 14.

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