TW200408005A - Semiconductor device fabrication method - Google Patents

Semiconductor device fabrication method Download PDF

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Publication number
TW200408005A
TW200408005A TW092116648A TW92116648A TW200408005A TW 200408005 A TW200408005 A TW 200408005A TW 092116648 A TW092116648 A TW 092116648A TW 92116648 A TW92116648 A TW 92116648A TW 200408005 A TW200408005 A TW 200408005A
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Taiwan
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film
oxide film
item
metal oxide
semiconductor device
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TW092116648A
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English (en)
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TWI233648B (en
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Hiroshi Shinriki
Kazumi Kubo
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Tokyo Electron Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Description

200408005 五、發明說明（l) 、【發明所屬之技術領域】 八雪^ ^明大體係關於半導體製造裝置，尤有關於具有高 二1 i駚&或所謂的high—κ(高介電率）介電質膜之超精細 化+導體裝置之製造方法。 X :之超向速半導體裝置除了製程更精細化外，閘極 1又二4漸可達到0 · 1 A m以下。一般說來，隨著半導體裝 【t ί細化，其動作速度會提高，但這般非常精細化之 二V -衣置中，伴隨精細化所導致之閘極長度之縮短，必 ，依據比例去則（scallng ，減少閘極絕緣膜之膜 厚。 •但閘極長度在〇 · 1 // m以下時，閘極絕緣膜若使用 度λ設定在1〜2nm、甚至是低於1〜2nm;閘極 極之漏電勺田r日”穿隧電流會增加’而發生無法避免閘 極之漏電流增加之情形。 提宰針ί土ϊϊγ，以往有將以下材料用於閘極絕緣膜之 厚，但換算成sl〇2膜之膜厚後會較薄 I雖相虽 ，h-K介電質材料，即使是閉極長度在〇1二 本短之超高速半導體裝置，亦可使用10nm左右之物理 =極絕緣膜，可抑制穿随效果所導致之間極之漏電流： 於將該high-K介電質膜做為閘極絕緣膜之 中，將hlgh-K介電質膜直接形成於石夕基板上時，
第6頁 200408005 五、發明說明（2) --- 換算為sa之絕緣膜之實際膜厚方面雖然是一較理想之方 式，但將high-K介電質膜直接形成於矽基板上時，金屬元 素會由hi gh-K介電質膜處擴散至矽基板中，導致穿隧區域 中有載體散亂之問題。 從提咼牙隧區域中之載體可動性（μ〇μ丨丨t幻之觀點 看，high-κ介電質閘極氧化膜與矽基板間最好配置有inm 以下、甚至是0.8⑽以下之非常薄之底層氧化膜。該底層 氧化膜必須是非常薄，若是較厚之氧化膜，將Mgh_K介電 質膜做為閘極絕緣膜時之效果會被抵銷。 二、【先前技術】 閘 圖1A〜1C顯示的是先前祐掉安 工引板徒業之具有high-K介電質 極絕緣膜之半導體裝置之製造步驟。 、 如圖1A所示，矽基板11上有一 下之膜厚之S i 〇2所構成之底層氧化 使用例如紫外光激發氧自由基（Rad 理所形成；而圖1 B之步驟中，該底 Z r 〇2專金屬氧化膜1 3是利用原子層 化學氣相沉積（M0CVD)法所形成。9 非常薄、最好是1 nm以 膜12，此氧化膜12是由 ical)之自由基氧化處 層氧化膜12上之Hf〇2、 沉積（ALD)法或有機金屬 圖1 A步驟中，該自ά |备儿占 目由基乳化處理可使用例如特開 2 0 0 2- 1 0 0 62 7號公報所々恭々十、t ^ 行開 激發自由基氧化處理可安^ a $/ 土极又|外光 於2〜3層分子層之膜展夕十 # 相田 、 之底層氧化膜。另外使用該牲戸弓 200 2- 1 0 0 62 7號公報所々恭夕士 4 士力丨= 邊特開 视π。己载之方法時，可將氮原子導入以 200408005
此方法形成之非常薄之石夕氧化膜中 可使用矽酸氮化膜。 而該底層氧化膜1 2亦 之沉積可使用特開 或M0CVD法° 介電質膜，為發現該 功此’需要的是結晶 ’如圖1 C所示般，以 熱處理，進行將金屬 化膜1 3被形成於非晶 會成為由微結晶之集 屬氧化膜1 3被使用為 絕緣膜。 圖1 B之步驟中，該金屬氧化膜1 3 2 0 0 2- 1 5 1 48 9號公報所記載iALD法、 该金屬氧化膜1 3是被當做high-κ 金屬氧化膜13做為high-K介電質膜之 化、而非S i 〇2膜般之非晶質膜。因此 往是將以圖1 B步驟所獲得之構造進行 氧化膜1 3結晶化之步驟。由於金屬氧 質之底層氧化膜1 2上，當其結晶化時 合所構成之多結晶體，該結晶化之金 高速半導體裝置之h i gh-K介電質閘極 誠如前述，形成於該hi gh-K介電質閘極絕緣膜丨3與石夕 基板11之交界之底層氧化膜12被要求越薄越好。該底層氧 化膜1 2之膜厚增加時，使用h i gh - K介電質閘極絕緣膜1 3之 效果會被抵銷。 另外，圖1 B之金屬氧化膜1 3之沉積步驟中，特別是使 用M0CVD法時，由於是於氧氣中進行處理，沉積時之基板 溫度較高時，該底層氧化膜1 2之膜厚會因為基板之氧化而 有增加之可能性。該底層氧化膜1 2之膜厚於圖1 C之結晶化 熱處理時亦會增加。 圖1 C之結晶化步驟中，除了金屬氧化膜1 3之氧化外， 該金屬氧化膜1 3中之微結晶之結晶粒會成長，當氧化膜1 3 中之結晶粒成長時，其與下方之底層氧化膜1 2之交界處會
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導致閘極漏電流之增加等問題。 五、發明說明（4) 變得不規則或不安定， 三、【發明内容】 為解決上述問題，本發明之概括性課題為提供一新 穎、有效之半導體裝置之製造方法。 本發明更具體之課題是··於具有high-K介電質閘極絕 緣膜之半導體裝置之製造中’提供一於該high-K介電質閉 極絕緣膜之結晶化時讦避免底層氧化膜膜厚增加之製造方 法0 極 絕 膜 膜 質 包 有 驟 裝 該 絕 緣 中 之 閘 含 機 等 置 金 化膜 另外， 緣膜之 膜結晶 之金屬 本發明 半導體 極絕緣 本發明 矽與氧 金屬原 半導體 之製造 屬氧化 藉由本 於沉積 本發明 半導體 化時， 氧化物 其次之 製造裝 膜之膜 其次之 之絕緣 料之化 裝置之 方法： 膜於沉 發明， 剛結束 六另11丄g II - IV 1|、冤買閘 5二亡製造中，當該high-κ介電質閘極 =2可抑制該high_K介電質閘極絕緣 如文結晶之^ έ士曰 課題S ·、、°晶粒成長之製造方法。 置中疋提：ΐ有hig"介電質閘極絕緣 制、—可有效控制該h i gh - K介電 子 < 衣込方法。 :於包含（1)於碎基板上形成 學氣μ積(:)進於該全絕屈緣膜上藉由使用 製造方法仃金屬氧化膜之沉積步 該金屬氧彳卜，提供一特徵如下之半導體 積剛結積步驟之實行方式是， μ . h . 狀悲下會成為結晶質。 傳成high人不& 時…“；電質問極絕緣膜之金屬氧 、、工疋結晶質之狀態，本發明抑制
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該金屬氧化膜之处曰& 屬氧化物結晶之:Γ 成*，即使是結晶化步驟後，金 金屬氧化膜之沉積仫亦不會超過10nm。其次，即使進行該 加。特別是本笋明二底層氧化膜之膜厚亦不會有實質之增 原料時，該金屬复ΐ使用含有酷氨（Amide)基之有機金屬 界之氮被認4:;中之氮會偏析至晶[該偏析至晶 、 △ 1」抑制原子沿著晶界移動。 細之：：爹照圖示針對本發明之其他課題及特徵進行更詳 四、【實施方式】 本發明之最佳實施型態 [第1實施例] ^ 圖2顯示的是本發明所使用之M〇CVD設備2〇之構成。 如，2。所示，M0CVD裝置2〇具備以泵（puMp)2i進行排氣 之反應容器22 ’該反應容器22中設置有保持被處理基板w 之保持台22A。 …圖2之M0CVD裝置20設置有將氧氣供給至該反應容器22 之管線（LINE)22a，並設置有將被保存於起泡器 2 3 A之H f [ N (Hs \ L等液體有機金屬原料透過氣相原料控制 器22b及管線22c供給至該反應容器22之原料供給系統j 。 其次’該M0CVD裝置20設置有一將被保存於瓶筒23β之Hf[N (C2 H5 )2 ]4等液體有機金屬原料透過液體流量控制器2 2 d及氣 化器22e供給至該反應容器22之原料供給系統n。該原料 供給系統I與原料供給系統Π間是以切換活門（v a L V E) 1及
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活門2之方式進行切換。 統1之氣相原料控制器2 2 b 圖3顯示的是該原料供給系 之構成。 ” 氣圖Λ所Λ’該氣相原料控制器22b包含有負責供㈣ ”肢貝里*里控制器（以下簡稱為MFC)31、32，兮MFC31 將該Ar氣體當做載氣（Carrier Gas )供給至 ^ 屬原料之起泡器23A。 仔η亥有故至 該起泡器2 3 Α會形成有機金屬原料之蒸氣，該有機金 屬原料蒸氣與該MFC32所提供之紅載氣一起被供仏声 感應器3 3處。 口 又 、孩》辰，感應器33針對被提供之Ar載氣之有機金屬原料 濃度進行量測，並將結果之輸出訊號供給至控制器34。另 外，ό亥控制為3 4依據規定之軟體形成對應該濃度感應器3 3 輸出訊號之第1及第2控制訊號，並分別將之供給至^ ^ MFC31及MFC32兩處。藉此可將該濃度感應器33中之載氣與 有機金屬原料之〉辰度比控制在規定值内。有機金屬原料之 濃度比被控制在規定範圍内之氣相原料氣體經由壓力計3 5 及活門36設定為規定之壓力後，再透過該管線22c供給至 反應容器2 2。 圖4顯示的是，圖2之M0CVD裝置20中，以Hf[N(C2H5)2]4 為原料，在4 8 Q C之基板溫度下將H f 02膜沉積於石夕基板上 時，於使用圖2所示之原料供給系統I及原料供給系統n 之情形下之沉積速度之比較。 如圖4所示，使用原料供給系統Π時，沉積時之基板
第11頁 200408005 五、發明說明（7) 溫度越高、沉積速度越快；以4 8 0 °C之基板溫度進行沉積 時，可獲得每分鐘1 〇 Onm之高量級（order )之沉積速度。以 該非常高速之沉積速度來說，要以高精度形成膜厚為數十 nm之金屬氧化膜是非常困難的。 相對地，若系統為使用起泡器2 3 A之原料供給系統 I ，即使沉積時之基板溫度為480 T：，亦可獲得每分鐘lnm 之量級之沉積速度，可高精度地形成非常薄之金屬氧化 膜。 圖5顯示的是，於圖2之M0CVD裝置中，使用原料供給 系統I時，透過管線22C被供給至該反應容器22之氣相原 料中之H f [ N (Hs & L分壓及基板上之沉積速度兩者之關 係。但圖5之關係係將基板溫度設定在480 t時之情形。 如圖5所示，使用圖2之原料供給系統I時，基板上之 H f 〇2膜之沉積速度會伴隨η f [ N (C2 H5 )2 ]4分壓之降低而減緩， 但利用圖3所示之氣相原料控制器2 2 b控制 H f [ N ( C2 Hs八h分壓後，可控制被處理基板w上之H f %膜之沉 積速度。 圖6顯示的是，於沉積剛結束（as —dep〇sited)之狀態 下以上述方式开> 成之H f 〇2膜之繞射型態（p a 11 e r η)之結 果。同時圖6亦是，於氮氣中以5〇〇〜7〇 〇之溫度範圍内針 =以上述方式所形成之H f 〇2膜進行各種不同溫度之熱處理 時之X射線之繞射型態之結果。但圖6之實驗係於以HF洗淨 後之石夕基板表面上，以前述之特開2 〇 〇 2 —丨〇 〇 6 2 7號公報所 記載之方法形成08nm左右之由Si〇2膜或Si〇N膜所構成之底
第12頁 200408005 五、發明說明（8) "
層氧化膜，再於以該方法形成之底層氧化膜上進行H f h膜 之沉積。此時’誠如前述，H f 〇2膜之沉積a以H f「( r if、1 為原料，沉積時之基板溫度設定在48〇t ( 2HsU 如圖6所示’即使是沉積剛結束後之狀態，Hf %膜仍顯 示H f (111)之繞射峰部（p e a k )，處於結晶化之狀態。 對應前述之圖1 (C)之步驟，針對利用上述方u式形成之 Hf〇2膜進行熱處理時，Hf(m)之繞射峰部稍微升高、並屏 開結晶化，但繞射峰部之強度變化並不顯著，即使針對、 H f 〇2膜之彳政構造進行熱處理，亦無太大變化。實際針對 中之Hf〇2結晶之粒徑分布進行量測之結果顯示，以、 行沉積後不久之狀態下，其平均粒徑約為47nm，而進 5 0 0 °C進行熱處理後之狀態下約為85nm，以6〇〇。〇進 處理後約為7.5_，以70 0 t進行熱處理 …、 將誤差考慮進來，〇2膜中幾乎沒有因為？處:為 徑超過10nm之粒子之情形。 、、 產生粒 圖7 A及圖7 B分別顯示的是，以穿秀 沉積Hf〇2膜不久後之樣本之剖面之结果，"、电子顯，鏡觀察 式電子顯微鏡觀察將Hf 02膜於氮氣中°以7=及=以穿透 之剖面之結果。但圖7Α、是以相π 仃”、、處理時 示。石夕基板中每個石夕原子均被解比例尺⑻仏）表 如圖7A所示，Hf02膜形成後不 ^ 約是1· 3nm之膜厚，與初期膜厚f 1 2底層氧化膜大 0· 5ηιη。 · 8nm)比較膜厚增加約 相對地，以圖7B來說，s i 〇泛a " 之膜 〇2底層氧化膜約為0.9nm
200408005 五、發明說明（9) 厚’與圖7 A之狀態比較，膜厚約增加了 〇 , 1 nm。 另外’圖7C顯示的是，於膜厚約為〇· 8ηιη之“⑽底層 氧化膜上以4 8 0 °C形成H f Ο?膜，再將之於氮氣中以5 〇 〇它進 行熱處理時之樣品之剖面之情況，可確認的是，此時之 SiON底層氧化膜之膜厚幾乎沒有增加。 藉由本發明，利用以Hf[N(C2H5)2]4為原料之M〇CVI)法、 以48 0 °C基板溫度進行Hf〇2膜之沉積時，即使是沉積剛結束 時亦可獲得結晶化之Hf〇2膜，且將該方式獲得之Hf〇2膜進 行熱處理後’ H f 〇2結晶並無實質之結晶粒之成長，且其下 方之底層氧化膜之膜厚實質上亦無增加。 ^ 可以獲得上述效果的理由目前尚不明瞭，可能與原料 中之氮原子於H f 〇2膜中被偏析至晶界，而牽制（p丨叩丨叫）沿 著結晶晶界移動之氧原子或Hf原子有關。此氮原子之量約 為0.5〜5原子％ 。 圖8顯示的是，使用以該方式在48〇下進行沉積後獲 得之Hf〇2膜形成電容，並測量c_v特性之結果。為進行比又 較，圖8中亦顯示有以3 5 0 t：進行沉積之Hf〇2膜之c — v特性。 以480 °C進行該Hf〇2膜之沉積時，氧濃度設定為87% ，'而以 3 5 0 °C進行該Hf〇2膜之沉積時，氧濃度則設定為56% 。 /如圖8所示，於基板溫度48〇t、氧濃度87%之條件下 所形成之H f Ο?膜之漏電流較少、c — v特性較佳，而以基板溫 度3 5 0 °C、氧濃度56%之條件所形成之η%膜之漏電^較 多、特性較佳，這是因為兩者於膜中含有之不純物元素之 濃度不同之故。 '
200408005 五、發明說明（ίο) 圖9顯示的是以3 5 0〜4 8 0 °C之範圍内以種種基板溫度進 行沉積之H f 02膜之膜中碳濃度之結果。 如圖9所示，以56%氧濃度之條件所沉積之H f02膜當中 之石炭濃度在任何基板溫度下’其膜中之破濃度均超過1 X 103/ cm3 ;而84 %氧濃度之條件下所沉積之Hf〇2膜中，特別 是以48 0 °C之基板溫度進行沉積時，其膜中碳濃度在1 χ 1 02 / cm3以下’因為其對圖8之C-V特性有貢獻。圖8之C-V特 性反映以下情況··以Hf[N(C2H5)2]4為原料進行Hf〇2膜之沉積 時’藉由於南溫、高氧濃度之條件下沉積，可降低膜中殘 留之碳濃度量。 ' 圖10顯示的是，於3 5 0〜480 °c範圍内之各種基板溫度 所沉積之Hf〇2膜之膜中氮濃度之結果。 如圖10所示，以氧濃度56 %之條件所沉積之Hf〇2膜 中，在任何基板溫度下，其膜中氮濃度均超過^ X 1 Μ / —; 而84%氧濃度之條件下所沉積之Η%膜中，特別是以48〇它 之基板溫度進行沉積時，其膜中碳濃度在1χ 1〇v⑽3以下。 這反映以下兩件事：（1)因為熱而使得具有以下社構式之 ΗΠΝ^Η5)2]4原料中之Hf-N之鍵結容易被切 &
(C2H5)2]4原料中不含有氧。 ^ h L
第15頁 200408005 五、發明說明（11) 誠如上述，本發明當中’特別是以含有H f [ N (C2 H5 )2 ]4 般酰胺基之有機金屬化合物為原料時，即使在膜之沉積是 於結晶化之狀態下進行之條件下進行金屬氧化膜之沉積 時，金屬氧化膜下方之底層氧化膜膜厚之增加在（一）金属 氧化膜之沉積時及（二）針對沉積後之金屬氧化膜進行熱處 理時等兩種情況下均可被有效控制。另外，針對金屬氧化 膜進行熱處理時，膜中之結晶粒之成長會被控制，與細薄 之底層氧化膜之界面之狀態（Morphology)會安定化。其 次’以南溫、南氧濃度之條件進行沉積時，可將膜中所含 有之不純物濃度降至最低限度。 [第2實施例] 圖1 1 A〜1 1 E顯示的是本發明第2實施例之半導體裝置之 製造步驟。 如圖11 A所示，使用例如紫外光激發氧自由基 (Radical)之自由基氧化處理，或繼上述自由基氧化處理 後進行電漿自由基氮化處理時，矽基板4 1上會形成由丨nm 以下之Si〇2膜或SiON膜所構成之底層氧化膜42 ;圖1B之步 驟中，利用含有 Hf[N(C2H5)2]4、Hf[N(CH3)2]4、Zr[Na2IU2] 4、21*[~((：113)2]4等、最好是含有酰胺基之有機金屬原料之 有機金屬化學氣相沉積（M0CVD)法，在4〇〇〜6〇(rc之基板溫 度、8 0 %以上之氧濃度之條件下，類似上述之金屬氧化膜 43於結晶質狀態下沉積之型態般，Hf %膜或Zr〇2等金屬氧
第16頁 200408005 五、發明說明（12) 化膜會被沉積於該底層氧化膜42上。 其次，圖11C之步驟中，以上述方式所獲得之構造於 氮氣中、5 0 0〜700 °C之溫度下接受熱處理後，該金屬氧化 膜43會被充$地結晶化。此時，該金屬氧化膜㈡於沉 結束時已經是結晶化之狀態，原料中之氮原子會被偏析 晶^，金屬氧，膜中之結晶粒之成長會被抑制，該底 ，膜42之殘留氧所導致之膜厚增加之情形會被抑制。 是以Si 0N膜形成該底層氧化膜42之情形，可實際避圖 11B、11C步驟中之底層氧化膜之膜厚增加之情形。 其次，圖11D之步驟中，該金屬氧化膜“上沉積有 晶矽膜44，將之於圖11E之步驟中進行圖型化 、 (^TTERMIMG)後1極電極4U會被形成。將該閘極電極 44“乂將離子（lQn)注人至光罩之方式處理後，該碎基板ο 之泫，極電，44A兩側會形成擴散領域4U、41β。 “稭由本實施％，可對應閘極長度之縮短而減少底層氧 化膜？及金屬，化膜43所構成之閘極絕緣膜之膜厚：可實 現一能以非常高速進行動作之半導體裝置。 、，以上針對本發明之較佳實施型態進行了說明，但本發 月並不侷限於上述貫施型態，而是可於本發明之要點内進 行各種變形、變更。 產業上利用性 ” 2由本發明可達到以下效果：構成high_K介電質閘極 巴、.彖膜之至屬氧化膜係以該金屬氧化膜剛結束沉積時已經
200408005
第18頁
200408005 圖式簡單說明 五、【圖式簡單說明】 圖1 A〜1 C為顯示以往之高介電係數之閘極絕緣膜之形 成步驟的圖式。 圖2為顯示於本發明第1實施例中使用2M〇CV])裝置之 構成的圖式。 圖3為將圖2之M0CVD裝置中之一部分詳細顯示的圖 式。 某板^ 顯示依本發明第1實施例之以％膜之沉積速度與 暴板/皿度之關係的圖式。 Θ 5為顯不依+ 氣相原料分壓之關係X的月圖弟^貫把例中Hf〇2膜之沉積速度與 圖6為顯示依本於^ — 繞射型態的圖式。 弟1貫施例所獲得之Hf〇2膜之X射線 ΒΙ7Α-7Γ % - 膜的樣本< M ，含依本發明第1實施例所獲得之Hf 〇2 尽之剖面TEM影像的圖式。 因8為顯示依本於日日货—
特性的圖式。 ^月第1貫施型態所獲得之Hf〇2膜之C-V
碳濃度的圖式、本明第1實施蜜態所獲得之Hf〇2膜中之 圖 1 0 為县§ + 4«* A φ夕备、曲"、貝不依本發明第1實施塑態所獲得之Hf02膜之膜 甲之虱滚度的圖式。 圖 llA 〜ik 之 制泮+ _ 1 L马說明依本發明第2實施例之半導體裝置 衣仏步驟的圖式。
第19頁 200408005 圖式簡單說明 元件符號說明： 11 矽基板 12 氧化膜 13 金屬氧化膜 20 M0CVD裝置 21 泵 22 反應容器 22A 保持台 22a 管線 22b 氣相原料控制 器 22c 管線 22d 液體流量控制 器 22e 氣4匕器 23A 起泡器 23B 瓶筒 3卜32 質量流量控制 器 33 濃度感應器 34 •控制器 35 壓力計 36 活門 41 矽基板 42 底層氧化膜 43 金屬氧化膜 44 多晶碎Jfe
第20頁
200408005 圖式簡單說明 4 4 A 閘極電極
第21頁 1··

Claims (1)

  1. 200408005 六、申請專利範圍 1. 一種半導體裝置之製造方法，包含如下步驟： 於矽基板上形成包含矽與氧之絕緣膜之步驟；及 藉由使用有機金屬原料之化學氣相沉積法於該絕緣膜 上沉積金屬氧化膜之步驟； 其特徵為： 該金屬氧化膜沉積步驟係以該金屬氧化膜在剛結束沉 積之狀態下成為結晶質之方式進行之。 2. 如申請專利範圍第1項之半導體裝置製造方法，其中該 金屬氧化膜包含Hf或Zr之其中之一元素。 3. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該金屬氧化膜之沉積步驟係在4 0 0〜6 0 0 °C之基板 溫度進行。 4. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該有機金屬原料包含酰胺（Amide)基。 5. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該有機金屬原料係選自於由H f [ N (C2 H5 )2 ]4、H f [ N (CH3)2 ]4、Zr [N(C2H5)2 ]4、Zr [N(CH3)2 ]4 等所構成之群組。 6. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該有機金屬原料係由保存液體原料之起泡所供
    第22頁 200408005 六、申請專利範圍 給0 7. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該金屬氧化膜沉積步驟係於含氧之環境中進行。 8. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該金屬膜沉積步驟係於氧濃度超過8 0 %之環境中 進行。 9. 如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該金屬氧化膜係由於沉積剛結束後之狀態下為 1 0 n m以下粒徑之微結晶所構成。 1 0.如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中，更包含將所沉積之該金屬氧化膜施以熱處理之 步驟，該金屬氧化膜係由於熱處理後之狀態下成1 0nm以下 粒徑之微結晶所構成。 11.如申請專利範圍第1項或第2項之半導體裝置之製造方 法，其中該金屬氧化膜含有5原子％以下範圍之氮。
    第23頁
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