TW200408001A - Method of manufacturing semiconductor devices - Google Patents

Method of manufacturing semiconductor devices Download PDF

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Publication number
TW200408001A
TW200408001A TW091133038A TW91133038A TW200408001A TW 200408001 A TW200408001 A TW 200408001A TW 091133038 A TW091133038 A TW 091133038A TW 91133038 A TW91133038 A TW 91133038A TW 200408001 A TW200408001 A TW 200408001A
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Taiwan
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oxide film
insulating film
teos oxide
forming
film
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TW091133038A
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English (en)
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Kyong-Sik Yoo
Sung-Ki Park
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Hynix Semiconductor Inc
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Publication of TW200408001A publication Critical patent/TW200408001A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Description

0) 0)200408001 玖、發明說明 (發明說日聽敘明：發_狀技術領域、歧麟、岐、實施方式及圖式簡單說明) 背景 發明領域 揭示製造半導體裝置之方法，且更特別地揭示製造具有 氧化物薄膜在其中堆疊之内層絕緣膜的半導體裝置之方 法。 相關技藝之描述 一般地，半導體記憶體裝置包括具有複數個記憶體單元 之記憶體單元陣列和用以在該記憶體單元上儲存資訊或讀 取该儲存貧訊之週邊電路。 在製造該半導體裝置之方法中，該記憶體單元陣列和週 邊電路在不同區域之半導體基材上形成。然而當裝置之整 合度增加，因為在記憶體單元區域和週邊電路區域之間之 地形差異會發生許多瑕疵。 圖1A至1C係為解釋製造011八]^方法之傳統半導體裝置之 剖面檢視圖。 現在參考圖1A，形成堆疊結構之閘極氧化物膜2和閘極電 極3在半導體基材丨上形成。接合區域4在半導體基材1在該 閘極電極3之兩側邊上形成，因此完成一電晶體。在半導體 基材1中在記憶體單元區域c和週邊電路區域p同時執行製 造電晶體之方法。 & 接下來，一第一絕緣膜5在整個結構上形成且圖案化該第 一絕緣膜5使得在一部分之接合區域4可被暴露。之後，一 位元線6在該第一絕緣膜5上形成使得該位元線6可被連接 (2) (2)200408001 至違暴露接合區域4。接菩 稷者一第二絕緣膜7在整個結構上 形成且之後該第二和第一終 弟、吧、味犋7和5循序地圖案化使得在 其他部分之接合區域4 + 飞了破暴路，因此形成一接觸洞。之後 ，一插塞8在該接觸洞中形成。 ”現在參考圖1B，一第三絕緣膜9在該包括該插塞8之第二 :、水膜7上形成。之後’圖案化該第三絕緣膜$以暴露該插 基接者電容器之_下層電極1()在該第三絕緣膜9上形成 使付訂層電極1()可被連接至該插塞8。在此時，該第三絕 緣膜9由PE-TEOS氧化物膜所製造。 >考圖1C，一介電膜丨丨和一上層電極12在包括該下層電 極10之第三絕緣膜9上循序地形成且之後被圖案化以完成 該電容器。在此時，當PE-TE〇S氧化物膜9之濕蝕刻速率緩 k日可，在週邊電路中之該第三絕緣膜9遺留。所以，在單元 區域C和週邊電路區域p之間之地形差異需要被減少。 之後，一第四絕緣膜13在整個結構上形成。之後，該第 四、第一和第一絕緣膜丨3、9、7和5循序地圖案化以形成 一接觸洞1 4使得在週邊電路區域p中之該閘極電極3之給 疋。卩伤可被暴露。接著，一金屬線（未顯示）在該第四絕緣 膜13上形成使得該金屬線可經由接觸洞14被連接至閘極 電極3。此時，該第四絕緣膜13也是由！>卜丁£〇3氧化物膜 所製造。 然而’在上述傳統方法中，因為在電容器中之上層電極 12之高度，在記憶體單元區域c和週邊電路區域p之邊界之 地形角度變成約45度。所以當地形差異在由PE-TEOS氧化 (3) 408001
2所製造之第四絕緣膜13之表面上反應時，在微影方法 j d方法中’其用以形成當形成為與隨後金屬線連接之 插塞之金屬’會遺留導電材料或發生瑕庇。因&，產 接等等，可能導致在金屬線之間之接觸和在線中之瑕庇: 進步地，當在週邊電路區域Ρ中以第三絕緣膜9形成之 上層電極12暴露時，該第三絕緣膜9之表面狀態經過許多方 法（微影方法、姓刻方法等等）變得粗糙時，因此降低盘第四 絕緣膜13之介面特性。所以，在該接觸洞Η形成之後執行 之潔淨方法中，蝕刻代理穿透至第三和第四絕緣膜9和" 之介面，使得形成不想要環狀之蝕刻部分Α。結果，因為顯 不在A之缺陷之結果，在接觸洞14中之障礙金屬層 (Τι/ΤιΝ)之橋接或不良階梯涵蓋率，連接至鄰近接觸洞 困難。 、 同時，在形成該第四絕緣膜13之後，以8〇〇t溫度執行 用以啟動上層電極12之快速熱退火（RTA)或管退火。然而 ，對於在PE-TEOS氧化物膜表面之地形差異之減少或在 PE-TEOS氧化物膜之間之黏附力之增加並沒有實質的效 果。 、' 發明摘要 為了解決上述問題，揭示一種製造半導體裝置之方法， 其中具有類流動性質和黏附力之OrTEOS氧化物膜在由 PE-TEOS氧化物膜所製造之絕緣膜上形成。 一揭示之方法其特徵為該方法包括下列步驟：在半導體 基材上形成一絕緣膜、在該絕緣膜上形成一導電層圖案以 (4) (4)200408001 及在包括該導電層圖案和該絕緣膜之整個結構上形成 o3-teos氧化物膜。 參考圖2A，形成堆疊結構之閘極氧化物膜22和閘極電極 23在半導體基材21上形成。接合區域24在該閘極電極^兩 邊之半導體基材21中形成，因此完成一電晶體。在半導體 基材2 1中在έ己憶體單元區域C和週邊電路區域p同時執行製 造電晶體之方法。 接下來，一第一絕緣膜25在整個結構上形成且圖案化該 第一絕緣膜25使得在一部分之接合區域24可被暴露。之後 ，一位元線26在該第一絕緣膜25上形成使得該位元線26可 被連接至該暴露接合區域24。接著，一第二絕緣膜27在整 個結構上形成且之後該第二和第一絕緣膜27和25循序地圖 案化使得在其他部分之接合區域24可被暴露，因此形成一 接觸洞。之後，一插塞28在該接觸洞中形成。 現在參考圖2Β，一第三絕緣膜29在該包括該插塞28之第 二絕緣膜27上形成。之後，圖案化該第三絕緣膜29以暴露 該插塞28。接著電容器之一下層電極30在該第三絕緣膜29 上形成使得該下層電極30可被連接至該插塞28。在此時， 該第三絕緣膜29由PE-TEOS氧化物膜所製造。 參考圖2C，一介電膜31和一上層電極32在包括該下層電 極30之第三絕緣膜29上循序地形成且之後被圖案化以完成 該電容器。此時，當PE-TEOS氧化物膜之濕蝕刻速率緩慢 時’在週邊電路Ρ中之該第三絕緣膜29遺留。所以，在單元 區域C和週邊電路區域ρ之間之地形差異可被減少。 200408001
之傻，一第四絕緣膜33在整個結構上形成。之後，該第 四、第二和第一絕緣膜33、29、27和25循序地圖案化以形 成一接觸洞34使得在週邊電路區域p中之該閘極電極23之 給定部份可被暴露。接著，一金屬線（未顯示）在該第四絕緣 膜33上形成使得該金屬線可經由接觸洞34被連接至閘極電 極23。此時，該第四絕緣膜33較佳是由〇3-TEOS氧化物膜 所製造。 具有良好特有類流動性質之〇3-TE〇s氧化物膜以大於約 2500埃之厚度，較佳範圍從2500至5000埃，在溫度範圍從 500至約550°C而沉積使得可防止對底下膜之依賴。進一步 地’在沉積上，控制〇3之密度大於約135克/立方公尺，較 佳從約135至約180克/立方公尺。 如上’因為該第四絕緣膜33由03-TE0S氧化物膜所製造 ’所以在記憶體單元區域C和週邊電路區域p之邊界的地形 差異因為良好類流動性質而減少。進一步地，與傳統技術 比較起來該地形角度被減少至約35度。此外，因為〇3-TEOS 氧化物膜之沉積溫度係為高，所以與第三絕緣膜29之介面 接觸變得良好。所以，在該接觸洞34形成之後執行之潔淨 方法中’並沒有產生環狀之蝕刻部份。 並且，在〇3-TEOS形成之後，包含在o3-teos氧化物膜 之不純物可藉由執行用以範圍從約750至約1000 °c之溫度 啟動上層電極32之快速熱退火（RTA)或管退火範圍從約20 秒至約30分鐘而移除。歸因於此，可獲得穩定之膜結構。 表1顯示本發明應用在製造具有0.16埃線寬之半導體裝 200408001
⑹ 置之方法之情況下，良好與缺陷比例。確認使用PE-TEOS 氧化物膜和03-TE0S氧化物膜本方法可獲得比傳統方法還 好之結果，因為分析瑕疵項目之結果可由因為橋接產生在 金屬線之間之接觸而產生。 表1 絕緣膜 可修護之 漏電流 操作電流 靜待電流 瑕庇比例 晶圓(REP) (LKG) (ICC) (ICC2) ea/wf %/wf ea/wf %/wf ea/wf %/wf ea/wf %/wf ea/wf %/wf PE-TEOS 1 1.2 1.4 1.7 34.2 41.7 32.9 40.1 4.1 5.0 (15 張） OrTE〇S 6 7.3 1.5 1.8 27.5 33.5 26.5 32.3 3.3 4.0 (4張） 在表1中，該可修護晶片（REP)指示雖然該晶片因為錯誤 方法而不能操作但是經由電路之改變而可操作。此時，漏 電流（LKG)指示流向基材之電流，操作電流（ICC)指示當電 路被驅動時流入金屬線之電流，而靜待電流（ICC2)指示在 · 電路被驅動之前流入金屬線之電流。 雖然流入基材和金屬線之電流被限制，但是不想要之電 流可能因為例如線之橋接之製程問題流入金屬線。雖然可 能有許多製程問題，但是對於本揭示方法提供在03-TE0S 氧化物膜形成之後之金屬線方法係為明顯的。 假如03-TE0S氧化物膜沒有特有類流動性質或其之表面 不平坦，在隨後之金屬線蝕刻方法中可能產生短路，使得 過度操作電流或靜待電流流動。所以，當測量有多少瑕疵 -11- 408001
⑺ 曰曰圓之結果’已經決定本揭示之方法具有改進之效果，如 可從表1所看到。換句話說，當因為〇^丁£〇3使用而減少地 $角度時’可有效地防止在金屬線之間之微小短路。 如上所述’本揭示方法包括使用具有良好類流動性質和 黏附力之O^TEOS氧化物膜在由pE-TE〇s氧化物膜所製造 之絕緣膜上形成一絕緣膜。所以，本揭示之方法可獲得下 列優點： 首先’當在記憶體單元區域和週邊電路區域邊界之地形 差異被減少時’可容易地執行隨後方法且可防止瑕疵。 第二’當〇3_TEOS氧化物膜在對底下膜之依賴為低之情 況下沉積以增加黏附力時，與PE_TE0S氧化物膜之介面接 觸，该膜之表面係為不良。因此，當潔淨接觸洞時蝕刻物 之穿入該介面可被防止。 第三，當包含在〇3_TEOS氧化物膜之不純物藉由隨後方 法移除時，可獲得一穩定膜結構以改進該膜之電氣特性。 第四，因為〇3_TEOS氧化物膜之沉積速度比使用之 PE-TEOS氧化物膜之沉積速度還快，所以可改進良率。 第五，需要專屬之沉積設備以沉積PE_TE〇s氧化物膜。 然而，當〇3-TEOS氧化物膜可藉由既存〇3-BPSG沉積設備 所沉積，可減少額外成本。 該揭不方法和其之許多變異已經參考特別具體實施例一 起與特別應用而描述。普通熟悉此技藝的人士和接觸到本 發明之教詢:將承認在其範圍内之額外修改和應用。所以， 本增附申請專利範圍的企圖係為涵蓋在本發明範圍内之任 -12- (8) 200408001 何及全部這樣之應用、修改、和具體實施例。 圖式簡述 在 本揭示方法之4述觀點和其他特點一起與隨附圖式 以上描述中解釋，其中： 圖1A至1C係為用以解釋製造半導體裝置之傳統方法 傳統半導體裝置之剖面檢視圖；以及 之 圖2 A至2 C係為用以解釋製造該半導體裝置之揭 之半導體裝置之剖面檢視圖。 法 季父佳具體實施例之詳細描述 圖2A至2C传炎03 半導體裝置 解釋包括製造DRAM2方法之製造該 旦、之揭示方法之半導體裝置之剖面檢視圖。 3、23 5、25 4、24 7、27 8、28 9、29 10 、 30 、 2〇 13、33 12、32 14、34 1、21 圖式代表符號說明 閘極氧化物膜 閘極電極 第一絕緣膜 接合區域 第二絕緣膜 插塞 第三絕緣膜 較低電極 第四絕緣膜 較上電極 接觸洞 半導體基材 -13- 200408001 (9) 6 ^ 26 位元線 31 介電膜
-14-

Claims (1)

  1. 拾、申請專利範圍 1. 一種製造半導體裝置之方法，其包括： 在半導體基材上形成一絕緣膜； 在該絕緣膜上形成一導電層圖案；以及 在該導電層圖案和該絕緣膜上形成〇3-TE〇s氧化物 膜。 2 ·如申請專利範圍第1項之方法，其中該絕緣膜係為 PE-TEOS氧化物膜。 3·如申請專利範圍第1項之方法，其中該〇3-TE〇s在範圍從 2500至5000埃之厚度，在範圍從5〇〇至約55〇。〇之溫度而 沉積。 4.如申请專利範圍第3項之方法，其中在該〇3_TE〇s氧化物 膜沉積期間，該〇3之密度範圍從約i 3 5至約1 8〇克/立方公 尺。 5·如申凊專利範圍第}項之方法，尚包括在形成該〇3_te〇s 氧化物膜之步驟之後執行一退火方法。 6. 如申請專利範圍第5項之方法，其中該退火方法在範圍從 750至約l〇〇〇°C之溫度執行。 7. 一種製造半導體裝置之方法，其包括： 在電晶體和位元線形成其中之半導體基材上形成一 PE-TEOS氧化物膜，在單元區域中和周邊電路區域中形 成電晶體； 在單疋區域之PE-TEOS氧化物膜上形成電容器；以及 在包括該電容器和PE-TE〇s氧化物膜之整個結構上 200408001
    形成〇3-TE〇S氧化物膜。 8_如申請專利範圍第7項之方法，其中該〇3•丁E〇s在範圍從 2500至5000埃之厚度，在範圍從5〇〇至約55〇。〇之溫度而 沉積。 9.如申凊專利範圍第8項之方法，其中在該丁E〇s氧化物 膜沉積期間，該〇3之密度範圍從約135至約1 80克/立方公 10·如申請專利範圍第7項之方法，尚包括在形成該〇3-TEOS 氧化物膜之步驟之後執行一退火方法。 11 ·如申請專利範圍第1 〇項之方法，其中該退火方法在範圍 從7 50至約i〇〇〇°c之溫度執行。
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