TW451290B - Method for making a metal capacitor - Google Patents

Abstract

The present invention provides a method for making a metal capacitor on the dielectric layer on the surface of the semiconductor wafer. The method first forms a bottom plate groove on the surface of the dielectric layer, and then forms a metal bottom plate in the bottom plate groove. Next, the method forms an insulation layer on the surface of the metal bottom plate, and forms a via hole in the insulation layer. Then, the method forms a first metal layer on the surface of the insulation layer and simultaneously fills the via hole to form a contact plug. Finally, the method forms a metal top plate on the surface of the insulation layer and forms a metal line on top of the surface of the contact plug.

Description

451290 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing a metal capacitor on the surface of a semiconductor wafer, particularly a metal layer, an insulating layer, and a metal-insulator-metal (MIM) Manufacturing method of the constructed metal capacitor. ~ Background In the semiconductor manufacturing process, metal capacitors made up of metal layer, insulation layer, and metal layer (MIM) composite structures have been widely used in the design of semi-I conductor elements. Because this metal capacitor has a lower electrical array! * J | value (resistance) and small parasitic capacitance (parasitic Γ I t capacitance), and there is no problem of induced voltage deviation in the empty region (induced image j voltage), Therefore, the MIM structure is currently used as the main structure of gold capacitors. Α & Guide & Please refer to FIG. 1 and FIG. 2 ′ FIG. 1 and FIG. 2 are schematic diagrams of a method for manufacturing a metal capacitor 26 on a ten-half sheet 10. As shown in the figure, the surface of the conductor chip 10 includes a substrate (not shown), and ′ 介 _ * ,, 土 12 are provided on the substrate. A conventional method is to first use a chemical vapor deposition (CVD) method to uniformly deposit a metal layer on the surface of the dielectric layer 12 of the gj γ electrode of the abundant conductor, and then define a metal plate After the pattern of l 4, it was removed by face engraving.

Page 4 i 451290 _____________ V. Description of the invention (2) • A metal layer of 14 parts to form a metal lower electrode 14. Next, an insulating layer and another gold chip layer are sequentially deposited on the surface of the lower metal electrode 14 and the pattern of the upper metal electrode 18 is similarly defined using a lithography process to remove excess metal and insulating layers An inter-metal insulator (IMI) 16 and an upper metal electrode 18 'are formed to complete the fabrication of the metal capacitor 26. As shown in FIG. 2, the metal capacitor 26 is covered with an inter-metal dielectric (IMD) 20 and is chemically and mechanically polished (chem i ca 1 mechan i ca 1 1 i sh i ng, CMP) process to grind the surface of the GuangMei metal dielectric layer 20 to a flat surface, and then coat (coating) a photoresist layer (not shown) on the surface of the inner metal dielectric layer 20, and use a yellow light j裎 to define the position of the via hole 28. Next, the excess photoresist layer is removed, and a dry etching process is performed using the remaining photoresist layer as a mask, and the metal dielectric layer 20 inside the uncovered portion is etched downward to form a contact hole 2 t Finally strip the remaining photoresist layer ^ 1;]: i Then fill the contact hole 28 with a metal layer (not shown) by sputtering, and then use the etch-back process to etch the metal layer It is approximately aligned with the surface of the inner metal dielectric layer 20 to form the contact plug 22. Next, a metal layer (not shown) is uniformly deposited on the surface of the metal dielectric layer 20, and a metal wire 24 is formed on the top surface of the contact plug 22 using etch. The contact plug 2 2 is mainly used to electrically connect the metal wire 24 and the metal capacitor 26.

Page 5 J451290 V. Description of the invention ¢ 3) The conventional method is to form a low-resistance, low-resistance conductor chip with an area of 10 and a metal capacitor of 26 and degrees, which are electrically connected to the inner metal wire 24. In the conventional method, if a part of the wafer 10 is to be vacant in the conventional method, the semiconductor crystal dielectric layer 20 is used for connection. In this way, the advantages and space of generating capacitors are used to make the resistance of the metal wire 24. The resistance value of the conventional method requires the plug 22 to cause the connection area and area of the production area. A metal capacitor 26 is made on the chip 10, and a plurality of contact plugs 22 are used to contact the metal. Although the metal capacitor 2 6 can be used, a large area and a half of a large number of contact plugs 22 are required to reduce the resistance and increase the current transfer. In order to reduce the waste of the area of most of the chip 10 in the metal capacitor 26 and the metal dielectric layer 20 in gold, and the metal layer, it needs to consume another. The width is getting smaller and smaller, how to improve the semiconductor wafer! 〇The production density of various components in order to reduce the area of B chip consumption and further increase the production capacity has become the most important issue in the semiconductor industry. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for fabricating a metal capacitor on the surface of a semiconductor wafer, so as to improve the integration degree of components on the semiconductor wafer. In a preferred embodiment of the present invention, the surface of the semiconductor wafer includes a dielectric layer. The method is to form an electrode recess on the surface of the dielectric layer first.

Page 6 45 ί 2 9 〇 V. Description of the invention (4) '... ——... " —— slot ' and a gold eyebrow lower electrode is formed in the lower electrode groove. Next, an insulating layer is formed on the surface of the lower metal electrode, and a contact hole is formed in the insulating layer. Then, a first metal layer is formed on the surface of the insulating layer and the contact hole is filled at the same time to form a contact plug. Finally, a metal upper electrode is formed on the surface of the insulating layer and a metal wire is formed on the top surface of the contact plug. «The present invention uses a damascene method to bury the metal lower electrode in the metal capacitor in the inner metal dielectric layer, and simultaneously manufacture the metal wire and the metal upper electrode '. Therefore, it does not need to consume too much semiconductor chip area and can effectively save the metal capacitor The space needed for the production of the wafers used to increase the production density of various components on the semiconductor wafer 9; 〇 For detailed description of the invention, please refer to Figures 3 to 5, Figures 3 to 5 show the invention on a semiconductor 1 wafer 30 Method of metal capacitor 50. As shown in FIG. 3, the surface of the semiconductor wafer 30 includes a substrate (not shown), and a dielectric layer 32 is disposed on the substrate. A dielectric layer 32 is provided on the dielectric layer 32 for making a local connect. The area connection metal layer 34 is manufactured by first depositing a metal layer (not shown, _,) 'uniformly on the surface of the dielectric layer 32, and then using a yellow light process to define the pattern of the area connection wires— (pattern), and finally using A dry etching process removes parts other than the mask protection: partly, the area connecting metal layer 34 is formed as shown in FIG. 3.

451 2 9 0 ·-— —-V. Description of the invention (5) ~. The method of the present invention is prior to the dielectric layer on the semiconductor wafer 30; the surface of the domain connection metal layer 34 is uniformly deposited with an inner metal dielectric &Quot; β 丨-and then coating a photoresist to display on the surface of the inner metal dielectric layer 36 'and using a yellow light process to define the lower electrode groove 3? And then removing the excess light The 'resistive layer' is then subjected to a dry etching process using the residual light as a fruit curtain to remove the metal dielectric within the portion not covered by the mask, and the layer 36 is formed to form a lower electrode groove 37. Finally, the residual light is stripped. Resistance, layer. Then, a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method is used to form a metal layer on the surface of the inner metal dielectric layer 36 and the surface in the lower electrode groove 37. Then, a planarization process is performed on the metal layer.!: Part of the metal layer is removed by etch back or a chemical mechanical polishing (CMP) process is used to smooth it to approximately the surface of the inner metal dielectric layer 36. Cut it so that a metal lower electrode 38 is formed in the lower electrode four groove 37.

I \: As shown in FIG. 4, an inner metal insulation layer (IMI) 40 is deposited on the surface of the lower metal electrode 38. Next, a yellow light process is used to define the position of the contact hole 42 and a dry etch or a wet etch method is used to form a via hole 42 ° in the insulating edge layer 40 with contact The fabrication of the hole 42 can also be integrated with contact holes made in other regions on the semiconductor wafer 30, and can be fabricated in the same etching step. : Then as shown in FIG. 5 ′, a metal layer is formed on the surface of the insulating layer 40 (not;

Page 8 (5) Description of the invention (6)) and simultaneously filling the contact hole 42 to form a contact 'Via plug 44 »Then, a photoresist layer is coated on the surface of the metal layer, and a yellow light is applied. The process is to define the pattern of the metal upper electrode 48 and the metal wire 46. Subsequently, the excess photoresist layer is removed, and the remaining photoresist layer is used as a mask to perform a dry etching process to remove the metal layer not covered by the mask to form a metal upper electrode 48 and a metal wire 46. . Finally, the remaining photoresist layer is peeled off. In the preferred embodiment of the present invention, the metal layer used to form the metal upper electrode 48 is simultaneously filled into the contact hole 42 to directly form the contact plug 44, so the process step β can be simplified. In addition, if process integration is considered Above: 〇 Need C. For example, other areas on the semiconductor wafer 30 also need to make contact plugs) 'contact plug 4 4 and metal upper electrode 48 or metal wire 4 6 can also be made separately in different steps. " For example, the contact hole 42 is filled with a metal layer by sputtering, and then the contact plug 44 is formed by etch back, and then a metal layer is uniformly deposited on the surface of the insulating layer 40. After the pattern is defined, an etching process is performed. A metal upper electrode 48 is formed, and a metal wire 46 is formed on the top surface of the contact plug 44. 〇—As shown in FIG. 5, the present invention first embeds the metal lower electrode 38 in the metal electrical device 50 in the inner metal dielectric layer 36 by using a mosaic method, and then according to the surface of the metal lower electrode 38. The inner metal insulating layer 40 and a metal upper electrode 48 are fabricated in sequence, and the other end of the metal lower electrode 38 is electrically connected to the metal wire 46. Therefore, the present invention can not only use metal capacitors

j 4512 9c V. Description of the invention (7) · Advantages of resistance, low parasitic capacitance 'and does not need to consume too much area and space of the semiconductor wafer 30 to make the metal lower electrode 38 and the contact plug 44.丨 Therefore, compared with the conventionally-made metal capacitor 26 (as shown in Fig. 2), the space saved under the metal capacitor 50 can be used to make the metal layer 34 for area connection. On the other hand, the contact plugs 4 and 4 can be fabricated at the same time when forming the metal wires required for the metal wires 46 and the metal upper electrode 46, further reducing the process steps and costs. Compared with the conventional method of manufacturing the metal capacitor 26, the contact plug 22 needs to be made with more space to form an electrical connection with the metal wire 24. In the method of the present invention, the metal lower electrode in the metal capacitor 50 is inlaid. 38 is embedded in the inner metal dielectric layer 36, and the metal wire 46 and the metal upper electrode 48 are produced at the same time, so it can effectively save the space of the wafer consumed by the metal capacitor 50, which improves the various components on the semiconductor wafer 30. Production density, thereby increasing productivity and reducing costs.丨 j Only the preferred embodiments of the present invention described above are equal variations and modifications made in accordance with the patentable scope of the present invention, which should be covered by the patent of the present invention.丨

i 1290, eJ single description, Figure 1 and Figure 2 are schematic diagrams of the conventional method for making metal capacitors on a half-conductor wafer. 3 to 5 are schematic diagrams of a method for fabricating a metal capacitor on a semiconductor wafer according to the present invention. Symbols shown in the figure 10, 30 Semiconductor wafer 12, 32 Dielectric layer 14 '38 Metal lower electrode 16, 40 Insulating layer 18' 48 Metal upper electrode 20, 36 Inner metal dielectric layer 22, 44 Contact plug 24, 46 Metal wires 26, 50 Metal capacitors 28, 42 Contact holes 34 Areas are connected to the metal layer.

Claims (1)

i 45 VI. Patent scope 1. A method for making a metal capacitor on the surface of a semiconductor wafer, the surface of the semiconductor wafer includes a dielectric layer, the method includes the following steps: forming a surface on the surface of the dielectric layer An electrode (bottom plate) groove; forming a metal lower electrode in the lower electrode groove; forming an insulating layer on the surface of the metal lower electrode; forming a contact hole (viah ο 1 e) in the insulating layer: in the A contact plug is formed in the contact hole; a metal upper electrode is formed on the surface of the insulating layer; and a metal wire is formed on the top surface of the contact plug. 2. The method of claim 1, wherein the method of forming the lower electrode groove includes the following steps: forming a first photoresist layer on the surface of the dielectric layer; performing a lithograph y process, Define the pattern of the SJ groove of the lower electrode; remove the excess first photoresist layer; use the remaining first photoresist layer as a mask to perform a dry etching process to remove the parts not covered by the mask Part of the dielectric layer to form the lower electrode groove; and removing the remaining first photoresist layer. 3. For the method of applying for the first item of the patent scope, wherein the metal is powered off, 451290 6. The method for applying the patent scope electrode further includes the following steps: forming a first on the surface of the dielectric layer and the surface of the lower electrode groove; A metal layer; and performing a planarization process to remove a portion of the first metal layer to be approximately aligned with the dielectric layer to form the metal lower electrode. 4. The method of claim 3, wherein the planarization process is a chemical mechanical polishing (CMP) process. 5. The method of claim 1, wherein the method of forming the contact plug further comprises the following steps: forming a metal layer on the surface of the insulating layer and filling the contact hole; During the etching process, the excess second metal layer is removed to be approximately aligned with the insulating layer to form the contact plug. 6. The method of claim 1, wherein the method of forming the metal upper electrode further comprises the following steps: forming a third metal layer on the surface of the insulating layer and the top surface of the contact plug; and on the third metal Forming a second photoresist layer on the surface of the layer; performing a yellow light process to define the pattern of the metal upper electrode and the metal wire: removing the excess second photoresist layer; Page 13 j 451 2 9 0 6. The scope of the patent application is a dry etching process using the remaining second photoresist layer as a mask to remove the third metal layer that is not covered by the mask to form the metal upper electrode and The metal wire; and removing the remaining second photoresist layer. 7. The method according to item 1 of the patent application, wherein the semiconductor wafer further includes a substrate, and a local connect metal layer is provided on the substrate, and the dielectric layer covers the area to connect the metal. Above the layer. 8. A method for making a metal capacitor on the surface of a semiconductor wafer; a method comprising: forming a dielectric layer on the surface of the semiconductor wafer; the method comprising the following steps: forming a lower electrode groove on the surface of the dielectric layer; i A metal lower electrode is formed in the lower electrode groove. 1 An insulating layer is formed on the surface of the metal lower electrode: ί I forms a contact hole in the insulating layer; ί forms a first metal layer on the surface of the insulating layer and simultaneously Filling up the contact hole to form a contact plug; and forming a metal upper electrode on the surface of the insulating layer and forming a metal wire on the top surface of the contact plug. 9. The method according to item 8 of the patent application, wherein the lower electrode recess is formed; the method of the groove includes the following steps: Page 14 4 451 2gg 6. Scope of patent application-forming a first photoresist layer on the surface of the dielectric layer; performing a yellow light process to define the pattern of the lower electrode groove; removing the first part of the excess light A resist layer; performing a dry etching process using the remaining first photoresist layer as a mask to remove a dielectric layer not covered by the mask to form the lower electrode groove; and removing the remaining first photoresist layer. 10. The method according to item 8 of the patent application, wherein the method of forming the metal lower electrode further comprises the following steps: | forming a second metal I layer on the surface of the dielectric layer and the groove surface of the lower electrode; and C i Perform a planarization process to remove a portion of the second metal layer to be approximately aligned with the dielectric layer to form the metal lower electrode. Π. The method of claim 10, wherein the planarization process is: a chemical mechanical polishing (CMP) process.丨 | I 12. The method according to item 8 of the scope of patent application, wherein the method of forming the metal power-on electrode and the metal wire includes the following steps: forming a second photoresist layer on the surface of the first metal layer; A yellow light process to define the 丨 〇;-! Pattern of the metal upper electrode and the metal wire; 丨 remove the excess second photoresist layer; | dry etch with the remaining second photoresist layer as a mask Process' removal is not rampant Page 15 4512 90 VI. Scope of patent application The first metal layer of the covering part of the mask to form the metal upper electrode and the metal wire; and remove the remaining second photoresist layer β 13. As the scope of patent application No. 8 The method of claim 1, wherein the semiconductor wafer further comprises a substrate, and a local connect metal layer is disposed on the substrate *, and the dielectric layer covers the area connection metal layer. 〇 · Page 16