本 成間隙壁的方法，田、，#,+ 特別疋有關於 一種形 因為閘 隨 件的數 地縮小 間仍必 質。這 i solat 成隔離 隔離物 件。 毛明係有關於一種半導體製造 極上介電在形成間隙壁的過程令 #主二ΐ層 造成的漏電流現象。 體電路製造技術的發展，晶片中所含元 里不斷i日加，凡件的尺寸也 。無論元件尺寸如行二μ，集度的楗幵而不斷 項右七#I 細小化，在晶片中各個元件之 或隔離，方可得到良好的元件性 的技術一般稱為元件隔離技術（devi ce ^以1101085^)，其主要目的係在各元件之間形 If! Ϊ且在確保良好隔離效果的情況下，儘量縮小 、品/，以空出更多的晶片面積來容納更多的元 淺溝槽隔離區（shallow trench is〇lati〇n)製程是近 積（CVD)^序形成一介電層以填入基底的溝槽中，但隨 積體電路密度不斷提高而元件尺寸日漸縮小的發展，上述 沈積技術並不易將介電層完全填滿溝槽，導致元件 效果受到影響。 間隙壁（spacer)是一種以絕緣材料形成在閘極周圍之 基底上以用來避免閘極與源/汲極導通而造成漏電流的絕 緣層裝置’間隙壁的高度與閘極的高度相同是一種較佳的 設計，可有效避免閘極與源/汲極導通。 但疋因為不平整的基底’例如因為製造隔離區時所形 成之溝槽，此溝槽因為未被沉積介電層時所填滿而造成的This method of forming a gap wall, Tian ,, #, + is particularly concerned about a shape because the number of gates is still small. This isolat into a piece of isolator. Mao Ming is concerned with the leakage current caused by the #main two-layer layer in the process of forming a barrier wall by a dielectric on a semiconductor manufacturing electrode. With the development of the manufacturing technology of the body circuit, the elements contained in the chip are continuously increased, and the size of each piece is also increased. Regardless of the size of the element, such as two μ, the density of the continuum is continuously reduced to 7 # I, and the individual components in the chip are isolated. The technology that can obtain good component properties is generally called the component isolation technology (devi ce ^ To 1101085 ^), the main purpose of which is to shape an If! Between the components, and to ensure a good isolation effect, try to reduce the size of the product as much as possible, and free up more chip area to accommodate more yuan The trench isolation region is a CVD process. A dielectric layer is formed in order to fill the trenches in the substrate. However, as the density of the integrated circuit continues to increase, the component size is gradually shrinking. Development, the above-mentioned deposition technology is not easy to completely fill the trench with the dielectric layer, and the effect of the element is affected. A spacer is an insulating device that is formed on the substrate around the gate with an insulating material to prevent the gate and source / drain from conducting and causing leakage current. The height of the spacer is the same as the height of the gate. A better design can effectively prevent the gate and source / drain from being conducted. But because of the uneven substrate ’, for example, because of the trench formed during the manufacture of the isolation region, the trench was not filled because the dielectric layer was deposited.
506060 五、發明說明（2) 凹陷㈣，在介電層上形成絕緣層時，絕緣層一會 凹陷區域中。如第1(a)圖所示，在基底"上依序形成 極。、墊層13，例如氧化層，及絕緣層14，例如氮： 乳化矽·，基底11具有因為形成隔離區10所造成之凹陷^ 當在基底丨丨上及閘極12上依序形成墊層13及絕 時’因為基底11具有凹陷區lla，所以整層13及 θ 會填入凹陷區11a中。 θ 4 藉著對形成有絕緣層14之基底η及閘極12進行 以形成間隙壁14a，而因為具有用作隔離區之凹陷區Ua^ 絕緣層14會填入因隔離區所造成之凹陷區内，而 殘留絕緣層Ub，如第1(b)圖所示。因此，在乾_ = 層14以形成間’14c時’為了將溝槽内之殘留絕 徹底清除，必須對絕緣層14進行過蝕刻（〇ver etch)，如 第1(c)圖所示。而過蝕刻會破壞形成在閘極12上之墊戶 部13a，容易使得於進行後續自我對準金屬矽化物製程%、 ，閘極12與形成在基底11内之源/汲極（未顯示）短路而有 漏電流（leakage current)產生，這會嚴重地影響產品 可靠度（reliability)。 有鑑於此’本發明之目的在於提供一種形成間隙 方法，可有效避免閘極與源/汲極短路而產生漏電流，並 徹底清除隔離區溝槽内殘留之絕緣層。 U w 根據上述目的，本發明提供一種形成間隙壁的方法， 適用於一形成有隔離區之半導體基底，包括下列步驟：於506060 V. Description of the invention (2) Depression: When the insulating layer is formed on the dielectric layer, the insulating layer will be in the depressed area for a while. As shown in Fig. 1 (a), electrodes are sequentially formed on the substrate ". 3. A cushion layer 13, such as an oxide layer, and an insulating layer 14, such as nitrogen: emulsified silicon. The substrate 11 has depressions caused by the formation of the isolation region 10. When a cushion layer is sequentially formed on the substrate and the gate 12, 13 and absolute time 'Because the substrate 11 has a recessed area 11a, the entire layer 13 and θ will be filled into the recessed area 11a. θ 4 forms the partition wall 14a by performing the substrate η and the gate electrode 12 on which the insulating layer 14 is formed, and because the recessed region Ua serving as the isolation region is provided, the insulating layer 14 will fill the recessed region caused by the isolation region Inside, and the insulating layer Ub remains, as shown in FIG. 1 (b). Therefore, in order to completely remove the residue in the trench when the layer 14 is formed to form the interval '14c', the insulating layer 14 must be over-etched, as shown in Fig. 1 (c). Over-etching will destroy the pad portion 13a formed on the gate electrode 12 and easily make the subsequent self-aligned metal silicide process. The gate electrode 12 and the source / drain electrode (not shown) formed in the substrate 11 Leakage current is generated due to short circuit, which will seriously affect the reliability of the product. In view of this, the object of the present invention is to provide a method for forming a gap, which can effectively avoid the leakage current caused by the short circuit between the gate and the source / drain, and completely remove the remaining insulating layer in the trench of the isolation region. U w According to the above objective, the present invention provides a method for forming a spacer, which is suitable for a semiconductor substrate having an isolation region formed, and includes the following steps:
506060 五、發明說明（3) 半導體基底上形成一閘極、 導體基底上依序形成一墊層 緣層至完全清除沉積於該隔 形成一第一間隙壁；形成一 壁上；及餃刻第二絕緣層至 第二絕緣層，以形成一頂角 第一間隙壁與第二間隙壁構 為了讓本發明之上述和 顯易懂，下文特舉出較佳實 如下： 一汲極及一源極；在閘極及半 及一第一絕緣層；蝕刻第一絕 離區邊緣之該第一絕緣層，以 第二絕緣層於墊層及第一間隙 完全清除沉積於隔離區邊緣之 間隙壁及一第二間隙壁，其中 成一雙層間隙壁。 其他目的、特徵及優點能更明 施例’並配合圖式作詳細說明 圖式簡單說明： 之形成間隙壁的方法之剖面示 第1 (a) -1 (c)圖係習知 意圖。506060 V. Description of the invention (3) A gate electrode is formed on a semiconductor substrate, and a cushion edge layer is sequentially formed on the conductor substrate to be completely removed and deposited on the partition to form a first gap wall; a wall is formed; Two insulating layers to a second insulating layer to form a top corner. The first and second spacers are structured in order to make the above and the present invention easy to understand. The following are particularly preferred as follows: a drain and a source The first insulating layer at the gate and half and a first insulating layer; etching the first insulating layer at the edge of the first isolation region, and completely removing the gap wall deposited at the edge of the isolation region with the second insulating layer on the pad layer and the first gap And a second partition wall, which forms a double-layer partition wall. Other objects, features, and advantages can be more clearly explained in the embodiment 'and illustrated in detail with the drawings. The drawings are briefly explained: The cross-sectional view of the method for forming the partition wall is shown in Section 1 (a) -1 (c).
第2(a) - 2(d)圖係本潑 示意圖。 X 符號說明： 10〜隔離區； 11 a〜溝槽； 1 3〜塾層； 1 4 a〜絕緣層； 1 4 c〜絕緣層； 21a〜溝槽； 2 3〜塾層； 2 4〜第一絕緣層； 明之形成間隙壁的方法 11〜基底； 1 2〜閘極； 1 3 a〜墊層頂部； 1 4 b〜殘留之絕緣層； 21〜基底； 2 2〜閘極； 2 3 a〜墊層頂部； 24a〜第一間隙壁； 之剖面Figures 2 (a)-2 (d) are schematic diagrams of this splash. Explanation of X symbols: 10 ~ isolated area; 11a ~ trench; 1 3 ~ 塾 layer; 1 4a ~ insulating layer; 1 4c ~ insulating layer; 21a ~ trench; 2 3 ~ 塾 layer; 2 4 ~ An insulating layer; a method of forming a partition wall 11 ~ base; 1 2 ~ gate; 1 3a ~ top of the pad; 1 4b ~ remaining insulating layer; 21 ~ base; 2 2 ~ gate; 2 3 a ~ The top of the cushion; 24a ~ the first gap wall; section
506060 五、發明說明（4) 2 5〜第二絕緣層； 25b〜第二間隙壁 實施例： 請參考第2 (a)圖 墊層2 3，例如氧化層 25a〜頂角間隙壁 在基底2 1上依序形成有閘極2 2、 ^ 及第一絕緣層2 4，例如氮化矽或氮 2化石夕；基底21具有因為形成隔離區所造成之溝槽21a。 s在基底21上及閘極22上依序形成墊層23及第一絕緣層24 時，因為基底21具有溝槽21a，所以墊層23及第一絕緣層 24會填入溝槽2ia中。 請參考第2⑻圖，對形成有第—絕緣層24之閘極22及 二=21上進行過蝕刻（over etch)，以徹底去除形成在溝 :a中之第-絕緣層24 ’並形成第一間隙壁24a。墊層頂 會因為過餘刻的關係而受到傷害，同時第—間隙壁 24a也會較塾層頂部…與閑極㈡之高度要來的低，如此一 來田間極22會容易與源/沒極（未顯示）短路而產生漏電流 ’因此另外再製作一間隙壁。 之門第2⑷圖’在基底21、形成具有墊層頂部… 給ΐ 1, 成一第二絕緣層25，第二絕 緣層25之材料例如二氧化矽、 ，第二絕緣層25會填人因為或氮氧切。同樣地 中。 馬化成隔離區所造成之溝槽21a 請參考第2 (d )圖，對形虏女# 第一間隙壁24a及閘極22上進;、ft弟一絕緣層25之基底21、 底去除形成在溝槽21a中之第_丁^蝕刻（〇Ver etch)，以徹 乐一絕緣層2 5，並形成頂角間506060 V. Description of the invention (4) 2 5 ~ Second insulation layer; 25b ~ Second spacer example: Please refer to Fig. 2 (a) cushion layer 2 3, for example, oxide layer 25a ~ top corner spacer on substrate 2 Gates 2 2 ^ and a first insulating layer 2 4 are sequentially formed on 1, such as silicon nitride or nitrogen 2 fossils; the substrate 21 has a trench 21 a caused by forming an isolation region. When the pad layer 23 and the first insulating layer 24 are sequentially formed on the substrate 21 and the gate electrode 22, because the substrate 21 has the groove 21a, the pad layer 23 and the first insulating layer 24 will fill the groove 2ia. Referring to the second figure, over etch is performed on the gate electrodes 22 and the second insulating layer 24 where the first insulating layer 24 is formed to completely remove the first insulating layer 24 ′ formed in the trench: a and form the first insulating layer 24 ′. A gap wall 24a. The top of the cushion layer will be damaged because of the excessive time. At the same time, the first-partition wall 24a will be lower than the top of the concrete layer ... and the height of the free pole will be lower. In this way, the field pole 22 will be easily connected with the source / battery. The pole (not shown) is short-circuited to cause leakage current ', so another gap wall is made. The second picture of the gate 'on the substrate 21, the top with a cushion layer is formed ... to 1, to form a second insulating layer 25, the material of the second insulating layer 25 such as silicon dioxide, the second insulating layer 25 will be filled because of or Nitrogen cutting. The same. The groove 21a caused by the Ma Huacheng isolation area is referred to FIG. 2 (d), and the shape of the first gap wall 24a and the gate electrode 22 of the Xingluo girl #, the base 21 and the bottom of the insulating layer 25 are removed and formed. The first etch in the trench 21a (0 Ver etch) to form an insulation layer 2 5 and form a vertex angle
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