TW200405122A - Novel planarization method for multi-layer lithography processing - Google Patents

Novel planarization method for multi-layer lithography processing Download PDF

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Publication number
TW200405122A
TW200405122A TW092104210A TW92104210A TW200405122A TW 200405122 A TW200405122 A TW 200405122A TW 092104210 A TW092104210 A TW 092104210A TW 92104210 A TW92104210 A TW 92104210A TW 200405122 A TW200405122 A TW 200405122A
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TW
Taiwan
Prior art keywords
layer
substrate
scope
patent application
planarization layer
Prior art date
Application number
TW092104210A
Other languages
Chinese (zh)
Other versions
TWI320874B (en
Inventor
Wu-Sheng Shih
James E Lamb Iii
Mark Daffron
Juliet Ann Minzey Snook
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Brewer Science Inc
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Publication of TW200405122A publication Critical patent/TW200405122A/en
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Publication of TWI320874B publication Critical patent/TWI320874B/en

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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094Multilayer resist systems, e.g. planarising layers
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24851Intermediate layer is discontinuous or differential

Abstract

The present invention is directed towards contact planarization methods that can be used to planarize substrate surfaces having a wide range of topographic feature densities for lithography applications. These processes use thermally curable, photo-curable, or thermoplastic materials to provide globally planarized surfaces over topographic substrate surfaces for lithography applications. Additional coating(s) with global planarity and uniform thickness can be obtained on the planarized surfaces. These inventive methods can be utilized with single-layer, bilayer, or multi-layer processing involving bottom anti-reflective coatings, photoresists, hardmasks, and other organic and inorganic polymers in an appropriate coating sequence as required by the particular application. More specifically, this invention produces globally planar surfaces for use in dual damascene and bilayer processes with greatly improved photolithography process latitude. The invention further provides globally planar surfaces to transfer patterns using imprint lithography, nano-imprint lithography, hot-embossing lithography and stamping pattern transfer techniques.

Description

200405122 玖、發明說明: 聯邦贊助研究/發展計劃 本發日月彳苳、, 吴國政府在先進技術計劃#70NANBIH3019下所 支持白勺,^ X _ 、 ”田王國標準和技術機構(NIST)所授予。美國政 府具有在本發明中之特定權利。 相關申請案 本申μ案請求2〇〇2年2月27日所提出之第6〇/36〇,374號之 ^ _為多層微影製程之新穎平面化方法之申請案之優先 權,其之全文在此併入本文中。 【發明所屬之技術領域】 本發月廣 &lt; 地指向新的接觸平面化方法,其利用熱塑, 二尤、固化和可光固化之平面化材料以製造微電子,光子, 光私光子,微電機系統(MEMS),生物晶片和感測器裝置 以及其他在其中需要微影製程之程序。 【先前技術】 一 、:私私子裝置具有幸父小實體外形之市場需求已驅使了對 將較小的微結構建造至费罢士、+丄 、 泛i主裝置中&lt;需求。另外,這樣的裝置 被預期為更有能源效率且特徵為更有強大的減,同時更 有成本效率地建以。為貫現這些目標’在積體電路(1C)晶片 上找到的特徵尺寸必須變彳琴括 又仔持,地更小。因此,必須將具 有諸如線,槽,穿礼、、P1 一 $, 、,、 價牙孔和洞&lt;更小的微結構之互連之多層形 成樣式至裝置基板上。 則’使用微影來將這些微結構建 造於裝置基板上。以一單亦 先阻層來正常地完成此程序。興 起的微影技術,諸如壓印料男 *,^ i丨认〜,奈米壓印微影,熱凸微影, 83889 200405122 以及打印樣式轉移已被提出。這些技術使用形成樣式之禱 模來將樣式轉移至基板表面上,來取代依㈣影形成樣式。 為了建造更小的微結構,已在微影製程中使用了較短波 長之曝光光線(例如從248 _至193譲至!” _至極紫外 、.泉(EUV)和更短)。、结果,焦點深度變得更窄,如此造 成-較小的微影製程寬容度。因此,基板表面地貌和厚度 及£用土奴形成樣式(表面之塗覆之厚度一致性成為在製 造具有所要之特徵尺寸之微結構中之關鍵因素。當曝光光 線之波長變得更短時,基板表面地貌之容忍度變得更窄。 另和欲形成樣式之薄膜需要足狗地薄以在微影製程之謹 X基板表面①美地平面的話。當建造更乡互連層時, 表面地貌變得更為嚴峻,使得其超出了微影製程之應 二ΓΓ制《外。因此’無法將細微的特徵尺寸形成樣式 至基板表面上。 另外由表面地貌所引起之 二 塗覆傾向以非—致的厚度具有二應用於表面上之薄膜 較不嚴格之方式被複製。在凹入區域中之薄 連同表面拓樸,藉.由造2 Γ薄膜厚度之非一致性, 在微影製程中之焦 万切曝露區域和藉由造成 題。因此,Α法:現在J D0F範圍外)之區域而產生問 維度(CD)控制。這些因素防 〜冓(“要的關鍵 當DOF變有時,=Λ見所要的微結構特徵尺寸。 來符合樣式形成”职。“具有十分受限之能力 成而求,因為基板表面之地貌和光阻之厚度 83889 200405122 和厚度-致性之故。因此’已提出和進行了多層塗覆製程。 首先將-厚層的平面化材料塗覆至基板表面上以提供—更 平面的表面,在其上可應用額外的塗覆層。最上層受到微 影樣式形成作用。然後以諸如非等向性電聚餘刻之適4 序,透過所有應用至基板上的層來將在最上層上形成。 《表面被向下轉移至基板。此技術稱為—上方表面成二呈 序。此上方表面成像程序可能牽涉到在應 將之形成樣式之前,應用二,三,或甚層並 板表面上。 戈甚土更多層塗覆至基 ^ 1⑷-⑷說明了一先前技藝程序。如圖i⑷中所示的, 層建構至一裝置基板10之表面上時,由層所產 ί=12變得無法接受。在這些情況下,-單層光阻程 上將所要的結㈣成樣式於這樣—個地貌表面 已進行一雙層製程來改進微影程序窗。此雔声 製程牽涉到旋轉塗覆一平面化㈣14 又層 區域’諸如穿孔和槽16,之後為—熱回流程序上:::= 材料可為-抗反射塗覆’ 一光阻,或一類似的材料。然而 旋轉塗覆的層傾向具有下方層之表面拓樸之輪靡(參看圖 :二:熱重力回流程序允許塗覆之材料流入凹入區域中(; 稍緩和表面之地貌,如圖響所示:( 要的話’此塗覆材料可於回流程序期間或之 :聯社。彳言Ρ /法 以,典乂互 %、,„ 4供—更平面的表面 型上為-光阻之一上方層18被應用在平面層。典 圖1⑷中所示的。此光阻層於微影製程期間形成樣二如 83889 200405122 薄膜厚度,厚度-致性和表面影像被形成樣式至上方層i8 中,基板表面受到-電衆蚀刻程序之作用。藉由在光阻層 中蝕刻未受保護之打開區域來將影像轉移至底部層,且若 必要的話至基板。因為當塗覆地貌基板表面時,底部平面 化材料14之厚度並非一致的,且可能較上方層18者厚,所 以每一層之電漿蝕刻率是關鍵的。最好上方層“會具有較 底部層低得多的電漿#刻率。然後上方層18可在樣式轉移 程序期間,即,電漿蝕刻程序期間作用如一蝕刻光罩。因 此,底部和上方層之電漿蝕刻選擇性對於將形成樣式之影 像從上方層轉移底部層和至下方基板是關鍵的。 為了放寬蝕刻選擇需求並防止底部和光阻層間之交互作 用,已提出在底部層和光阻層之間應用一種十分薄之硬光 罩層。此硬光罩層會具有所需的電漿蝕刻性質且會作用來 分離底部和光阻層。已新程序已被稱為一三層程序。硬光 罩層未改進平面化層之表面平面性,因為硬光罩十分薄且 符合平面化表面。因此,其未改進微影程序寬容度,如此 對二層程序來說仍需一平面化底部層。需要一特定的電漿 蝕刻私序將樣式轉移至硬光罩層,並使用一額外的電漿蝕 刻程序將樣式進一步轉移至底部平面化層。在雙層和三層 私序中 而要一平面化底部層來提供一平面表面,在其上 可應用額外的塗覆層。 雙波紋(DD)程序,在先進1C製程中廣泛使用之技術使得 2一金屬沈積步驟中能做二金屬層之沈積。將介電層蚀刻 一次或二次(或甚至多次,視DD程序之方案而定)來在介電 83889 200405122 :中建構二層樣式。若在- DD程序應用中牽涉到超過二介 =層,則可能以一作用如一蝕刻停止障礙層之薄硬光罩層 ::離介電層。一旦形成DD樣式,則將一金屬互連材料: 、、土褕式中。在一 DD程序方法中,將一層介電材料(或光阻) 輯塗覆至—基板2〇之表面上(圖2(糊。使用微影照相 來建互微結構(穿孔/槽22),其具有所需的外觀比,連同層 中又不同的特徵密度區域,如圖2(a)中所示的。基板2〇具^ 區域24 ’其具有隔離的結構,以及一區域26 ,其具有稠 达、分布的特徵。如此,特徵密度在晶圓中以及橫跨基板表 面而變化。當第—平面化層28被塗覆至此形成樣式之表面 t時’地貌盡可能地深,因為特徵密度在決定最終的薄膜 厚^扮演了關鍵的角色’如圖2(b)中所示的。在結構頂端 上的缚膜厚度在區域26中稠密特徵上比在包含隔離結構之 區域24上的薄膜厚度薄得多。結果,在一具有相同特徵穷 度之區域中實現了局部平面化。然而,因為在高特徵密〜: ,域上的較薄薄膜厚度而產生凹入區域。最壞的情況中, 右塗覆的薄膜不夠厚’則在稠密特徵密度區域中之高外觀 :匕結構(諸如穿孔和槽)可能被部份填滿,同時在較不稠密特 徵區域中可能被第一平面化材料層28完全填滿。因此,全 域平面化在晶圓中和橫跨基板表面上不存在。 然後將-第二層30塗覆至平面化層28上,其缺乏全域平 面性。此第二層可為感光光阻層(供雙層程序用)或一薄硬光 罩材料(供三層程序用)。如圖2(c)中所示的,第二層3〇賴向 於具有下方層28之地貌之輪廓’且薄膜層在區域26上較厚。 83889 -11 - 200405122 使頂袖層薄膜厚度非一致性最小化和改進全域平面性之一 方法係應用一相當厚的(厚至幾微米或甚至更厚)下方平面化 層,其將提供—更好的局部和全域表面平面性,在農上可 應用額外的層。厚的平面化層結果造成一更長的電裝㈣ 時間,且需要更高的電漿姓刻選擇性。平面化層之電裝银 刻速率需要甚高於頂端成像層者。這些性質造成對=之 處理量和材料相容性之考慮。其他方法為使仿製結構建造 至具有較低的特徵密度之區域,以提供晶圓内和橫跨基板 表面《較小:交并《特徵密度,以減輕特徵密度效應。因此, 可在平面化層表面上貫現一較佳的全域平面性。炊 由使用仿製結構,設計和電路佈局更複雜。該方:了立精 加所需之晶圓尺寸,其是不想要的。 曰 做為微影照相程岸夕立 ^ 其他選擇,在建立微結構中已接屮 和仗事幾個新興的微等j枯种_、也』口 影,教凸出”:技術,諸如壓印微影,奈米壓印微 微打印樣式轉移等。壓印微影,奈米壓印 '…、、凸出微影利用一模鑄將樣 至 上,在其上塗霜一笼认 丞板表面 户u_的,可流動的模铸材料。可在周園浪 度或提鬲溫度上勃弁、士 + &lt; 、 仏d国鐵 觸時,在壓印或凸出#序°當模舞表面與模鐸材料接 成钕式之模鑄表面符合。 且/、形 料加以硬化。握心 ’·、、後以先或熱万法來將模鑄材 ^轉移至模轉材料。以要㈣,==〈負樣 夠的參數和順序來兩牌&amp; 成‘式又表面以足 微影技術不依賴透:Γ以將樣式轉移至下方層。這些 賴透過载有樣式之光罩(或分劃旬之光曝光來 83889 -12- 200405122 :樣式轉移至光阻層。因此,d〇f並非一問題。炊 覆的可流動模鑄材料需二 矣;&gt; + i、、, 致的厗度,橫跨基板 吴《全域平面性。推論模鑄是堅固的且要被 ==構是十分微小的。模料面需絲持 =《表面完美平行的。在模铸材料層中之任何地貌和ΐ ;,性具有對被轉移至基板表面之最終樣式之災難性200405122 发明 Description of the invention: The federally sponsored research / development plan is issued today, and is supported by the Wu government under the Advanced Technology Plan # 70NANBIH3019, ^ X _, "Tian Kingdom Standards and Technology Agency (NIST) Institute Granted. The U.S. government has certain rights in the present invention. Related Applications This application μ requests No. 60 / 36〇, 374 of February 27, 2002 ^ _ is a multi-layer lithography process The priority of the application of the novel planarization method is incorporated herein by reference in its entirety. [Technical Field to which the Invention belongs] The present invention points to a new contact planarization method that uses thermoplastics, two Special, curing, and photo-curable planarization materials to make microelectronics, photons, light photons, micro-electromechanical systems (MEMS), biochips and sensor devices, and other processes in which lithographic processes are required. [Previous technology [1]: The market demand for a private child device with the shape of a lucky father small entity has driven the need for building smaller microstructures into a Fei Shishi, + 丄, Pan i main device. In addition, such a device Be It is expected to be more energy-efficient and characterized by more powerful reductions, and at the same time be more cost-effective. In order to achieve these goals, the feature sizes found on integrated circuit (1C) chips must be changed. The ground is smaller. Therefore, it is necessary to pattern the multilayer formation of interconnections with smaller microstructures such as wires, grooves, dressing, P1, $, ,, and pores and holes &lt; smaller microstructures onto the device substrate Then 'use lithography to build these microstructures on the device substrate. This process is normally completed with a single layer and first barrier layer. The emerging lithography technology, such as embossing material male *, ^ i 丨 recognize ~, Nano-imprint lithography, thermal convex lithography, 83889 200405122, and print style transfer have been proposed. These technologies use the pattern forming pattern to transfer the style to the substrate surface, instead of relying on the shadow formation pattern. In order to build more Small microstructures have been used in the lithography process for shorter wavelengths of exposure light (for example from 248 _ to 193 譲 to! "_ To extreme ultraviolet, .spring (EUV) and shorter). As a result, the depth of focus becomes narrower, which results in a smaller lithography process tolerance. Therefore, the topography and thickness of the substrate surface and the pattern formed with tuno (the consistency of the thickness of the coating on the surface become key factors in manufacturing microstructures with the desired feature size. When the wavelength of the exposure light becomes shorter, the substrate The tolerance of the surface geomorphology becomes narrower. In addition, the film to be patterned needs to be thin enough on the surface of the lithography process X substrate surface to be beautiful. When the interconnection layer is built, the surface geomorphology changes. It is even more severe, which makes it beyond the requirements of the lithography process. It is therefore impossible to pattern subtle feature sizes onto the substrate surface. In addition, the second coating tendency caused by surface topography is non-uniform. The thickness of the film is reproduced in a less rigorous way. The thin film in the recessed area together with the surface topography is used to create a 2 Γ film thickness inconsistency in the lithography process. Wanqian exposed the area and caused the problem. Therefore, the A method: now the area outside the J D0F range) produces the problem dimension (CD) control. These factors prevent ~ 冓 ("The key point is when the DOF changes sometimes, = Λ see the desired microstructure feature size. To meet the pattern formation" job. "It has a very limited ability to achieve, because of the topography and light of the substrate surface The thickness of the resistance is 83889 200405122 and the thickness is consistent. Therefore, a multi-layer coating process has been proposed and carried out. First, a thick layer of planarizing material is applied to the surface of the substrate to provide a more planar surface, in which An additional coating layer can be applied on top. The uppermost layer is affected by lithographic pattern formation. Then in an appropriate order such as anisotropic electropolymerization, all layers applied to the substrate will be formed on the uppermost layer. "The surface is transferred down to the substrate. This technique is called-the upper surface is in two order. This upper surface imaging procedure may involve applying two, three, or even layers to the surface before it should be patterned. Geshetu applied more layers to the substrate ^ 1⑷-⑷ illustrates a prior art procedure. As shown in FIG. I⑷, when a layer is constructed on the surface of a device substrate 10, the layer produced by the layer = 12 becomes Unacceptable. In In some cases, a single layer of photoresist is patterned in such a way that a geomorphic surface has been subjected to a two-layer process to improve the lithographic process window. This whispering process involves spin coating and planarization. 14 Another layer area 'such as perforations and grooves 16, followed by-on the thermal reflow process ::: = material can be-anti-reflective coating'-a photoresist, or a similar material. However, spin-coated layers tend to have underlying layers The topography of the surface is popular (see Figure 2: The thermal gravity reflow process allows the coated material to flow into the recessed area (; slightly alleviate the topography of the surface, as shown in the ring: (If necessary, this coating material can be During the reflow process or: Associated Press. / P. Method / Code, %% ,, "4%-for a flatter surface type-photoresist one of the upper layer 18 is applied to the plane layer. As shown in 1⑷. This photoresist layer is formed during the lithography process such as 83889 200405122. The film thickness, thickness-consistency, and surface image are patterned into the upper layer i8, and the substrate surface is affected by the electrical etching process. By etching the unprotected film in the photoresist layer Area to transfer the image to the bottom layer and, if necessary, to the substrate. Because the thickness of the bottom planarizing material 14 is not uniform when coating the surface of the landform substrate, and may be thicker than the upper layer 18, the electrical power of each layer The plasma etch rate is critical. It is best that the upper layer "will have a plasma #etch rate that is much lower than the bottom layer. The upper layer 18 may then act as an etch mask during the pattern transfer process, ie, during the plasma etch process. Therefore, the plasma etching selectivity of the bottom and upper layers is critical for transferring the patterned image from the upper layer to the lower substrate and to the underlying substrate. In order to relax the need for etching selection and prevent the interaction between the bottom and photoresist layers, A very thin hard mask layer is applied between the bottom layer and the photoresist layer. This hard mask layer will have the required plasma etching properties and will work to separate the bottom and photoresist layers. The new procedure has been called a three-tier procedure. The hard mask layer does not improve the surface planarity of the planarization layer because the hard mask is very thin and conforms to the planarized surface. Therefore, it does not improve the tolerance of the lithography process, so a flat bottom layer is still required for the two-layer process. A specific plasma etching sequence is required to transfer the pattern to the hard mask layer, and an additional plasma etching process is used to further transfer the pattern to the bottom planarization layer. In the two- and three-layer private sequences, a planarized bottom layer is required to provide a planar surface on which additional coatings can be applied. The double ripple (DD) process, a technique widely used in advanced 1C processes, enables two metal layers to be deposited in a two metal deposition step. The dielectric layer is etched once or twice (or even multiple times, depending on the scheme of the DD procedure) to construct a two-layer pattern in dielectric 83889 200405122 :. If more than two dielectric layers are involved in the -DD program application, it may be possible to act as a thin hard mask layer :: isolating dielectric layer for an etch stop barrier layer. Once the DD pattern is formed, a metal interconnect material is used: In a DD process method, a layer of dielectric material (or photoresist) is applied to the surface of the substrate 20 (Fig. 2 (paste. Photolithography is used to build the inter-microstructure (perforation / groove 22), It has the required appearance ratio, together with the different characteristic density regions in the layer, as shown in Figure 2 (a). The substrate 20 has a region 24 ′ which has an isolated structure, and a region 26 which has Dense, distributed features. In this way, feature density varies across the wafer and across the substrate surface. When the first planarization layer 28 is applied to the patterned surface t, the landform is as deep as possible because of the feature density It plays a key role in determining the final film thickness ^ as shown in Figure 2 (b). The film thickness at the top of the structure is denser in region 26 than the film in region 24 containing the isolation structure. The thickness is much thinner. As a result, local planarization is achieved in an area with the same feature poverty. However, a recessed area is generated due to the thinner film thickness on the high feature density ~:, worst case Middle, right coated film is not thick enough High appearance in dense feature density regions: Dagger structures (such as perforations and grooves) may be partially filled, while in less dense feature regions may be completely filled by the first planarizing material layer 28. Therefore, global planarization Does not exist in the wafer and across the substrate surface. The second layer 30 is then applied to the planarization layer 28, which lacks global planarity. This second layer can be a photoresist layer (for a two-layer process) For) or a thin hard mask material (for three-layer procedures). As shown in Figure 2 (c), the second layer 30 depends on the contour of the landform with the lower layer 28 and the film layer is in the area Thicker on 26. 83889 -11-200405122 One of the methods to minimize the inconsistency of the thickness of the top sleeve layer film and improve the global planarity is to apply a relatively thick (up to a few microns or even thicker) underlying planarization layer, It will provide—better local and global surface planarity, and additional layers can be applied in agriculture. The thick planarization layer results in a longer electrical decoration time, and requires higher plasma engraving selectivity. .The electrical engraving rate of the electrical layer of the planarization layer needs to be much higher than the top Imaging layer. These properties lead to consideration of the throughput and material compatibility. Other methods are to make the imitation structure into a region with a lower characteristic density to provide the wafer and across the substrate surface. : The feature density is combined to reduce the feature density effect. Therefore, a better global planarity can be realized on the surface of the planarization layer. The design and circuit layout are more complicated by using imitation structure. The side: 立 立Adding the required wafer size is undesired. As a photolithographic camera Cheng Xili ^ Other options, several emerging micro-classes have been accepted and battled in the establishment of microstructures. Also "oral shadows, teach protruding": technology, such as imprint lithography, nano imprint micro print style transfer, etc. Imprint lithography, nano imprint '... ,, embossed lithography uses a die casting to The sample is supreme, and a layer of frosted, castable material on the surface of the fascia board is painted on it. It can be embossed on Zhouyuan's latitude or temperature. When the national railway is in contact, it can be stamped or embossed. # When the dance surface and the mold material are connected to form a neodymium-type mold. Surface fit. And /, the material is hardened. Hold the heart ‘·’, and then transfer the moulded material to the moulded material first or by heat. With the necessary parameters, == <negative samples, and the order of the two cards &amp; to form a ‘style and surface suffices. Lithography technology does not rely on transparency: Γ to transfer the style to the lower layer. These depend on the pattern-carrying mask (or the exposure of the light of a quarter to 83889 -12- 200405122: the pattern is transferred to the photoresist layer. Therefore, dof is not a problem. The flowable casting material for cooking coating requires two & &Gt; + i ,,,, and the degree of cross-substrate Wu "Global planarity. It is inferred that the die casting is strong and the structure is very small. The mold surface needs silk holding =" Perfect surface Parallel. Any landforms and ridges in the layer of die-casting material are catastrophic to the final pattern transferred to the substrate surface

&quot;^可能性。非—致性模鑄材料厚度會造成不完全 的樣式轉移。%,較厚的薄膜區域將被不足地㈣,同時 較薄的區域將被過度兹刻。因此,需要一全域平面基板表 面’在其上可獲得—可流動之模鑄材料層之-致厚度和全 j平面表面以供樣式轉移程序之用。當將細微結構打印至 一裝置表面上時,亦需要一全域平面表面。 【發明内容】 本=明廣泛地關於新的接觸平面化方法及由那些方法形 成之$導結構,其提供微影照相,壓印,奈米壓印,和▲&quot; ^ Possibility. Non-consistent mold material thickness can cause incomplete pattern transfer. %, The thicker film area will be insufficiently scratched, while the thinner area will be over-etched. Therefore, there is a need for a global planar substrate surface &apos; on which the thickness of the flowable mold casting material layer and the full j-plane surface are available for the pattern transfer process. When printing microstructures onto a device surface, a global planar surface is also required. [Summary of the Invention] The present invention is widely related to new contact planarization methods and $ guide structures formed by those methods, which provide photolithography, embossing, nano-imprinting, and ▲

^出微影以及打印樣式轉移程序用之全域平面表面,如此 禁止或防止先前技藝之問題。 更詳細地說,藉由首先應用(諸如藉由旋轉塗覆,噴濺塗 覆,澆鑄,攪製,噴式塗覆等)一平面化層至一具有地貌特 徵於其表面上之微電子基板來形成前導。對大部份的應用 來巩,此層(在如下面所討論之固化和接觸平面化之後)一般 將從約0.1_l〇V m厚,最好從約〇 m,從約0.U V m更 好,且從約0.1-0.5 // m會更好。*MEMS應用來說,平面化 層厚度一般將在從約1-1000 //111之範圍中,且從約1_5〇〇//111 83889 -13- 200405122 更好。 典型的微電子基板之範例包括矽晶圓,合成半導體晶圓, 絕緣體上矽(SOI)晶圓,玻璃基板,石英基板,有機聚合物 基板,合成材料基板,介電基板,金屬基板,合金基板, 碳化珍基板,氮化石夕基板,藍寶石基板,陶製基板,以及 由财火材料所構成之基板。 平面化層可為一抗反射材料或光阻材料,或其可由一包 含一從由可光固化或可熱固化聚合物,單體,寡聚物,和 其之混合物以及熱塑材料所構成之群組中所選出之組成部 份之材料所形成。在材料中之單體,聚合物,和/或寡聚物 之總重量應為至少約1 %,最好從約5-1 00%,且最好從約1 0-8 0%,以平面化材料之總重取100%為基礎。適當的單體, 寡聚體和聚合物之範例包括下列之單體,寡聚體和聚合物: 諸如ϊ分酸環氧化物之環氧化物,諸如驗酸環氧化物壓克力 鹽之壓克力鹽,諸如酚醛環氧化物乙烯乙醚之乙烯乙醚, 聚酯,多硫亞氨,有機和無機單體/寡聚物/聚合物,以及含 有乙烯之有機和無機單體/寡聚物/聚合物,以及前述之混合 物。 材料最好進一步包含一最好存在重量從約0-99%大小之溶 劑,從重量約0-95%最好,且重量從約5-85%更好,以材料 之總重量取1 00%為基礎。適當的溶劑包括乙醚甲基乙二醇 丙烯(PGME),醋酸乙醚曱基乙二醇丙烯(PGMEA),乳酸乙 基,以及前述之混合物。亦可使用會在固化或硬化程序期 間與單體,寡聚物和聚合物作用之作用溶劑。這樣的溶劑 83889 -14- 200405122 之例包括甘油醚,乙醚乙烯,乙醚烯丙,壓克力鹽以及 竣酸丙缔。 材料最好進一步包含一從由酸,酸產生物(例如熱酸產生 物’光酸產生物)構成之群組中所選擇之組成部份,光起發^ Generate global planar surfaces for lithography and print style transfer procedures, thus prohibiting or preventing problems with previous techniques. In more detail, by first applying (such as by spin coating, spray coating, casting, stirring, spray coating, etc.) a planarization layer to a microelectronic substrate having topographic features on its surface, Leading. For most applications, this layer (after curing and contact planarization as discussed below) will generally be from about 0.1-10 m thick, preferably from about 0 m, from about 0. UV m Well, and from about 0.1-0.5 // m would be better. * For MEMS applications, the thickness of the planarization layer will generally be in the range from about 1-1000 // 111, and more preferably from about 1-500 // 111 83889 -13- 200405122. Examples of typical microelectronic substrates include silicon wafers, synthetic semiconductor wafers, silicon-on-insulator (SOI) wafers, glass substrates, quartz substrates, organic polymer substrates, synthetic material substrates, dielectric substrates, metal substrates, and alloy substrates. , Carbonite substrate, nitrided stone substrate, sapphire substrate, ceramic substrate, and substrate made of fire and fire materials. The planarization layer may be an anti-reflective material or a photoresist material, or it may be composed of a material consisting of a photo-curable or thermo-curable polymer, monomer, oligomer, and mixtures thereof, and a thermoplastic material. Formed from selected constituent materials of the group. The total weight of monomers, polymers, and / or oligomers in the material should be at least about 1%, preferably from about 5 to 100%, and preferably from about 10 to 80%, in a flat plane. The total weight of chemical materials is based on 100%. Examples of suitable monomers, oligomers, and polymers include the following monomers, oligomers, and polymers: epoxides such as tritiated acid epoxides, such as acrylic acid epoxide pressure acrylic salt Acrylic salts, such as vinyl ethers of phenolic epoxide ethylene ether, polyesters, polythioimines, organic and inorganic monomers / oligomers / polymers, and organic and inorganic monomers / oligomers containing ethylene / Polymers, and mixtures of the foregoing. The material preferably further comprises a solvent which is preferably present in a size of from about 0-99% by weight, preferably from about 0-95% by weight, and more preferably from about 5-85% by weight, based on the total weight of the material taken as 100% As the basis. Suitable solvents include diethyl methyl glycol propylene (PGME), diethyl ether ethyl acetate ethylene glycol propylene (PGMEA), ethyl lactate, and mixtures of the foregoing. Solvents that interact with monomers, oligomers, and polymers during the curing or hardening process can also be used. Examples of such a solvent 83889 -14- 200405122 include glyceryl ether, ethyl ether, ethyl allyl, acrylic salt, and acrylic acid. The material preferably further comprises a component selected from the group consisting of an acid, an acid generator (e.g., a thermal acid generator &apos;

劑’熱起發劑以及界面话性劑。當存在一酸或酸產生物時, 其最好存在從重量約01-10%之大小,且最好從重量約〇5-5% ’以材料之總重重量取1⑻。/q為基礎。適當的酸或酸產生 物I範例包括從由三苯基硫磺六氟磷酸,三苯基硫磺六氟 砷酸,二苯基碘六氟磷酸,二苯基碘六氟銻酸,二苯碘六 氟坤酸,三苯硫羰六氟磷酸,羥氧硫羰六氟磷酸,四氨 inflate,聚合硫酸酯,二壬萘硫酯和甲苯硫酸所構成之群 組中所選擇者。亦可以鹼或鹼產生物來取代酸或酸產生物。 备一光起發劑或熱起發劑存在時,其最好個別存在為重 量從約0.1-10%之大小,且最好重量從約〇·5_5%,以材料之Agent's thermal hair growth agent and interfacial speech agent. When an acid or acid generator is present, it is preferably present in a size from about 01 to 10% by weight, and most preferably from 1 to 5% by weight based on the total weight of the material. / q based. Examples of suitable acids or acid generators I include triphenylsulfohexafluorophosphoric acid, triphenylsulfohexafluoroarsenic acid, diphenyliodohexafluorophosphoric acid, diphenyliodohexafluoroantimonic acid, diphenyliodohexafluoro This is selected from the group consisting of fluconic acid, triphenylthiocarbonyl hexafluorophosphate, hydroxythiocarbonyl hexafluorophosphate, tetraammonium inflate, polymeric sulfate, dinonaphalylthiolate and toluenesulfuric acid. It is also possible to replace the acid or acid generator with a base or a base generator. When a light hair or thermal hair agent is present, it is preferably present individually as a weight of from about 0.1-10%, and preferably from about 0.5-5% by weight.

重ΐ取100%為基礎。適當的光起發劑或熱起發劑之範例I 括從由羥基銅,氫氧,,有機過氧化物,含氮合成物,以 及Uiflic酸之胺鹽所構成之群組中所選擇的那些。 無論包括在平面化材料中之組成部份為何,在壓製期間, 平面化材料應具有-從約1G_5M⑻ep之黏性,且最好從約 10 5,000 CP如at匕,材料能夠填滿在從約〇 ㈤及更大之 尺寸,且最好從約(Μ·5(),_心之範圍中之缺口。 在應用平面化材料之後,若必要的話,其可被加熱至約 5 0 _ 2 5 0 C達約5 _ 6 0 〇秒以聽私矛丨从、、 移除剩餘落劑。或者,剩餘溶劑可 藉由使塗覆物體受到—直六作 具工作用達約5至600秒之方式加以 83889 -15- 200405122 移除。然後材料與一平坦物體接觸達足夠的時間和壓力以 將物體之平坦表面轉移至平面化層,且允許塗覆過的材料 流至凹入區域中。平坦物體可由石英,矽,玻璃,金屬, 合金,陶,聚合物等構成。接觸或壓製步驟一般將包含從 約1-1,〇〇〇1^之應用壓力,最好從約5_25〇1^,且從約1〇·〗: psi更好,達一從約丨秒至約12〇分鐘之時間,最好從約3秒至 約10分鐘,且從約10秒至約5分鐘更好。 此程序可在一被排空至少於周圍氣壓之腔室中執行,但 周圍狀況,提高的壓力,以及一人工氣壓亦適當。應了解 一光平坦或一些等效裝置可用來應用此氣壓,以及必須選 擇應用所選擇壓力之裝置來適應特定程序(例如若要利用一 UV固化程序的話一 uv透明光平坦是必要的)。可在大氣壓, 一鈍氣壓(包含諸如氮,氬等之氣體),或一特定氣壓(包含 諸如有機溶劑蒸汽,含有矽之蒸汽,水蒸汽,氧等物體)中 處理壓製程序。 4 接觸步驟一般在從約周圍溫度至約350t之溫度上執行。 對可光固化平面材料來說,應將壓製溫度控制在約周圍溫 度至約250°c之範圍中,最好在約周圍溫度至約1〇(rc之範 圍中’且在約周圍溫度至約50°C之範圍中是更好的。對可 熱固化平面材料來說’應將壓製溫度控制在約周圍溫度至 約350°C之範圍中,最好從約50-25(rc,且從約5〇_2〇〇它是 更好的。 對熱塑平面材料來說,應將壓製溫度控制在從約周圍溫 度至約材料之熔點以上50°C之範圍中,最好從約材料之2 83889 -16 - 200405122 璃轉化溫度(Tg)以下20°C至約材料之熔點以上l〇°C。在接觸 步·驟之後,將基板冷卻至約其 ' 以下,且最好約Tg以下2〇 t:或約50°C或至少約其Tg下20°C (視哪一個較低而定)。若合 成物為熱塑,且允許其如上面所討論般藉由冷卻來硬化或 固化。 在光學平面物體與基板維持接觸之同時(及/或在接觸之 後),以傳統方式來硬化或固化平面化材料。例如,若合成 物為可光固化的,則其受到UV光線作用(以適於該特定合成 物之波長)以固化該層。同樣地,若合成物為可熱固化的, 則藉由加熱(例如透過-熱板,透過-烤爐,透過IR加熱,輻 射加熱等)’之後冷卻至小於Tg來將其固化,且最好冷卻至 小於其Tg以下約50°C或至少約20°C (視何者較低決定)。若合 成物為熱塑,則允許其如上面所討論般藉由冷卻來硬化或 固化。 - 播論所使用的材料為何,一旦已硬化或固化平面材料, 則基板與該平坦物體分離。如此將平坦物體表面之平面性 轉移至基板表面以提供全域平面性。然後可將一具有一致 薄膜厚度和全域平面性之第二塗覆層(諸如一成像層)應用至 平面化表面上。適當的成像層包括光阻層,壓製層,以及 打印的樣式。再者,在應用成像層之前可應用一或多個選 項性的中間層(例如光罩層,位障層,抗反射層)。在一實施 例中,中間層基本上是沒有金屬的(即包含少於約重 量之金屬,且最好約〇%重量之金屬)。 然後在成像層中根據已知的程序建立一樣式,並將之轉 83889 -17- 200405122 移至下方層。例如若成像層為—光阻1層被選擇性地曝 光至UV光線,且以-傳統的光阻生成器來生成以形成樣 式。將體會到此生成步驟亦將選擇性地移除(視樣式而定^ 何中間層’以及基板下方之平面化層,同時留下至少一部 份的原始基板地貌原封不動。若成像層為一壓印層,則一 具有所要的樣式之負像將壓印層壓製以在其中形朗要的 樣式。然後透過壓印層,中間層,以及平面化層來姓刻樣 式以轉移樣^。類似地,若樣式為_打印樣式,則㈣樣 式被触刻以透過平面化層來轉移樣式。^重覆上面的步驟 以在刖導上形成一第二“堆疊”,或可使前導受到進一步已 知的處理作用。 【實施方式】 參考圖3⑷,顯示基板32。基板32在包括一在其上具有結 構或特徵34之表面。這些結構或特徵34將具有變化的地貌 和特徵尺寸’視前導之最終預定用途而定。當在此使用時二 地貌”意指一結構之高度或深度,同時“特徵尺寸,,意指一 結構之寬度和長度。若寬度和長度不@,則傳統上稱較小 數為特徵尺寸。 使用-傳統程序(參看圖3(b))將一平面化材料%應用至基 板32。在先前所描述之程序狀況下將一諸如在一光平坦(未 顯示)之者之平坦表面與材料36接觸,在平坦表面之固化/硬 化和與材料36分離之後,結果在材料%上產生—全域平面 表面38如此王域平面表面38準備好供隨後層之應用之 用;者如光阻層40,其可以一致的方式加以應用(圖3⑷)。 83889 -18- 200405122 參考圖4(a),顯示基板42。基板42包括一具有形成於其中 之結構或特徵44之表面。基板42具有一區域46,其具有隔 離的結構,以及一具有稠密特徵之區域48。這已避免了如 先別时論之先前技藝方法之問題。 使用一傳統程序將一平面化材料50應用至基板42(參看圖 4(b))。將諸如一光平坦(未顯示)上之平坦表面與材料5〇於 先前所描述的程序狀況下接觸,在平坦表面之固化/硬化和 與材料50之分離(參看圖4(c》之後,結果在材料5〇上產生一 全域平面表面52。如此,如圖4⑷中所示的,全域平面表面 52準備好供應用隨後的層之用,諸如光阻層54,其可以一 致的方式加以應用。 當在此使用時,一全域平面表面預定為指稱一厚度“丁”(參 看圖4⑷)變化少於約1()%之層,且最好在約^刚^之距 離上小於約5%。本發明之方法結果產生一這樣的全域平尹 性(亦稱為薄膜厚度變異)。再者’根據本發明所形成之固忘 的或硬化的平面化層在任何個別的地貌特徵或結構會具有 一少於約250 A之地貌,且最好小於約15〇 A。最後,所笋 明的固化或硬化平面化層會具有一小於約6〇〇入之地貌,‘ 好小於約500 A,且最好在一约1 、 取灯在約m之距離上(基板表 面長度)小於約400 A,其中在此距離上至少存在二個不同 的特徵密度區域。 範例 方法。然而,應了解到 ’且其中内容不應被認 下列範例提出根據本發明之較佳 這些範例係以說明之方式所提供的Re-take 100% as the basis. Examples of suitable light or thermal hair-up agents include those selected from the group consisting of copper hydroxy, hydroxide, organic peroxides, nitrogen-containing compounds, and amine salts of Uiflic acid. . Regardless of the components included in the planarization material, during the pressing, the planarization material should have a viscosity of from about 1G_5M⑻ep, and preferably from about 10 5,000 CP such as at, the material can be filled in from about 0. ㈤ and larger sizes, and preferably a gap in the range of about (M · 5 (), _heart. After applying the planarizing material, it can be heated to about 5 0 _ 2 5 0 if necessary C for about 5 _ 600 seconds to listen to the private spear 丨 remove the remaining agent from ,,, or the remaining solvent can be subject to the coating object-Zhi Liu tool work for about 5 to 600 seconds Add 83889 -15- 200405122 to remove. Then the material is in contact with a flat object for enough time and pressure to transfer the flat surface of the object to the planarization layer and allow the coated material to flow into the recessed area. Flat object It may be composed of quartz, silicon, glass, metal, alloy, ceramic, polymer, etc. The contacting or pressing step will generally include an applied pressure from about 1-1, 000, 1 ^, and preferably from about 5-25, 0 ^, and From about 10 ·〗: psi is better, from about 1 second to about 12 minutes , Preferably from about 3 seconds to about 10 minutes, and more preferably from about 10 seconds to about 5 minutes. This procedure can be performed in a chamber that is evacuated to at least the surrounding air pressure, but the surrounding conditions, increased pressure, And an artificial air pressure is also appropriate. It should be understood that a light flat or some equivalent device can be used to apply this air pressure, and a device that applies the selected pressure must be selected to adapt to a specific process (for example, a UV curing light is used if a UV curing process is to be used). Flatness is necessary). It can be processed under atmospheric pressure, an inert pressure (containing gases such as nitrogen, argon, etc.), or a specific pressure (including organic solvent vapors, silicon-containing vapors, water vapor, oxygen, etc.) Procedure. 4 The contacting step is generally performed at a temperature from about ambient temperature to about 350t. For photocurable flat materials, the pressing temperature should be controlled in a range from about ambient temperature to about 250 ° c, preferably about Ambient temperature to about 10 (in the range of rc ') and better in the range of about ambient temperature to about 50 ° C. For heat-curable planar materials,' pressing temperature should be controlled at about In the range of ambient temperature to about 350 ° C, it is more preferably from about 50-25 ° C, and from about 50-20 ° C. For thermoplastic planar materials, the pressing temperature should be controlled at From about ambient temperature to about 50 ° C above the melting point of the material, it is preferably from about 2 83889 -16-200405122 below the glass transition temperature (Tg) to about 10 ° C above the melting point of the material. After the contacting step, the substrate is cooled to about 0 ° or less, and preferably about 20t below Tg: or about 50 ° C or at least about 20 ° C (depending on which one is lower). If the composition is thermoplastic, and allowed to harden or solidify by cooling, as discussed above. While the optical planar object maintains contact with the substrate (and / or after contact), the planarization material is hardened or cured in a conventional manner. For example, if the composition is photocurable, it is exposed to UV light (at a wavelength suitable for that particular composition) to cure the layer. Similarly, if the composition is heat-curable, it is cured by heating (eg, through-hot plate, through-oven, IR heating, radiation heating, etc.) and then cooled to less than Tg, and it is best Cool to about 50 ° C or at least about 20 ° C below its Tg (whichever is lower). If the composition is thermoplastic, it is allowed to harden or solidify by cooling, as discussed above. -What is the material used? Once the flat material has been hardened or cured, the substrate is separated from the flat object. In this way, the planarity of the flat object surface is transferred to the substrate surface to provide global planarity. A second coating layer, such as an imaging layer, having a uniform film thickness and global planarity can then be applied to the planarized surface. Suitable imaging layers include photoresist layers, pressed layers, and print styles. Furthermore, one or more optional intermediate layers (such as photomask layers, barrier layers, anti-reflection layers) can be applied before applying the imaging layer. In one embodiment, the intermediate layer is substantially metal-free (i.e., contains less than about a weight metal, and preferably about 0% by weight metal). Then create a pattern in the imaging layer according to a known procedure, and transfer it to 83889 -17- 200405122 to the lower layer. For example, if the imaging layer is-the photoresist 1 layer is selectively exposed to UV light, and is generated by a conventional photoresist generator to form a pattern. You will realize that this generation step will also be selectively removed (depending on the style ^ any intermediate layer 'and the planarization layer under the substrate, while leaving at least a part of the original substrate landform intact. If the imaging layer is a Embossing layer, a negative image with the desired style, embossing the embossing layer to form the desired style in it. Then embossing the style through the embossing layer, the middle layer, and the planarization layer to transfer the shape ^. Similar Ground, if the style is a _print style, the ㈣ style is engraved to transfer the style through the planarization layer. ^ Repeat the above steps to form a second "stack" on the guide, or make the leader further [Embodiment] Referring to FIG. 3 (a), a substrate 32 is shown. The substrate 32 includes a surface having structures or features 34 thereon. These structures or features 34 will have varying landforms and feature sizes. It depends on the final intended use. When used here, “landscape” means the height or depth of a structure, and “feature size” means the width and length of a structure. If the width and length are not @, then pass Collectively, the smaller number is referred to as the feature size. A conventional material (see Fig. 3 (b)) is used to apply a planarizing material% to the substrate 32. In the previously described procedure, a material such as The flat surface of one of them is in contact with the material 36. After the flat surface is cured / hardened and separated from the material 36, the result is produced on the material%. The global plane surface 38 is such that the king plane surface 38 is ready for subsequent layers. For example, the photoresist layer 40 can be applied in a consistent manner (Fig. 3⑷). 83889 -18- 200405122 Referring to Fig. 4 (a), a display substrate 42 is shown. The substrate 42 includes a structure or feature formed therein. 44. The substrate 42 has a region 46 with an isolated structure, and a region 48 with dense features. This has avoided the problems of previous techniques as previously discussed. Use a conventional procedure to planarize a The material 50 is applied to the substrate 42 (see FIG. 4 (b)). A flat surface such as a light flat surface (not shown) is brought into contact with the material 50 under the previously described process conditions to cure / harden the flat surface Separation from the material 50 (see FIG. 4 (c), the result is a global planar surface 52 on the material 50. Thus, as shown in FIG. 4 (a), the global planar surface 52 is ready to be used for subsequent layers , Such as photoresist layer 54, which can be applied in a consistent manner. When used herein, a global planar surface is intended to refer to a layer with a thickness "D" (see Fig. 4) that varies by less than about 1 ()%, and It is preferably less than about 5% at a distance of about ^ Gang. The method of the present invention results in such a global flatness (also known as film thickness variation). Furthermore, the 'forgotten or The hardened planarization layer will have a landform of less than about 250 A, and preferably less than about 150 A, in any individual topographic feature or structure. In the end, the solidified or hardened planarization layer will have a landform of less than about 600, which is less than about 500 A, and preferably at a distance of about 1, and a lamp at a distance of about m (the surface of the substrate Length) is less than about 400 A, where there are at least two different characteristic density regions at this distance. Example method. However, it should be understood that ′ and its content should not be recognized. The following examples suggest the best according to the present invention. These examples are provided by way of illustration.

83889 -19-83889 -19-

UJ1ZZ 為限制本發明之總體範圍 在一穿孔晶圓上之可#α 丁 乏了忐固化平面材料 精由在頁光實驗室中完 曰 35 王此a 2〇 §之環氧化物(D.E.R. 心4LV,D0W Chemical c , 士 PGME(Aldrich)以及 1.2 2 《sarcat KI_85(一可由 Sart〇mer ” 一 设侍產生物)來製備 了光固化之材料。然後以— Μ、 ’、 · β m過濾器來過濾材料並 將 &lt; 儲存於一乾淨的褐瓶中。 穿孔H曰曰圓來做為基板。石夕晶圓首先被塗 4以具有約1 # m之厚度之-黃仆於落〃 、 予反之一乳化矽潯膜。一具有不同特 徵途、度且具有直炉〇 7 ^ ^ 二· 穿孔之區域之樣式被形成於 一虱化矽薄膜中。穿孔深度為約l#m。 、 益:一具有約。一之厚度之可光固化平面材料之薄膜旋 、、塗覆至具有不同樣式特徵密度區域之穿孔晶圓上。晶圓 被轉移:一壓製工具腔室且被放置在一基板臺上。平面材 7义頂端表面被定位來面對一光透明光平坦物體表面。壓 ^工具腔至盍子被料,且腔室被淨空至少於Μ陶爾。腔 至壓力保持在少於2G陶爾達約3〇秒以移除剩餘的溶劑。基 板®被提鬲以允許基板表面以一約68 psi之力量與光平坦表 面接觸達3G秒。在基板表面於一 68㈣之壓力與光平坦表面 維持接觸之同時,一脈衝紫外線(uv)光線透過光平坦表面 被月?、射以固化平面材料。uv光線之脈衝猶環為工秒開和$秒 關,總曝光時間3秒。在曝光之後,壓製工具腔室從少於2〇 陶爾排放(執行整個壓製程序之腔室壓力)至大氣壓力。降低 83889 -20 - 200405122 基板臺’且打開腔室盍子。基板與光平坦表面分離且從腔 室移除以供特性化之用。 使用除了壓製步騾之外的相同處理狀況來將其他穿孔晶 圓塗覆以相同的材料。亦製備此額外的晶圓並加以特性化 且用來做為一參考晶圓。 以一 Tencor Alphastep輪廓形成器來特性化平面化過的穿 孔晶圓表面。獲得一在平面化結構上以及橫跨相鄰特徵密 度區域之小於200 A之地貌。使用一聚焦離子束(FIB)顯微鏡 來測量在不同特徵密度區域中之結構頂端上之平面薄膜厚 度。測量二個特徵密度區域。測量在一具有約〇 3//m直徑 穿孔以及約0.5 a m地貌之區域中之結構頂端上的薄膜厚 度,以及在一具有約〇.3/zm直徑穿孔以及約175//111地貌之 區域中之薄膜厚度。在二區域中所測量之高結構(非在穿孔 之頂端上)之頂端上的薄膜厚度分別約為〇.38 #㈤以孓 0.39// m。測量在具有與和在壓製晶圓中者相同之特徵密度 之區域上之參考晶圓薄膜厚度。參考晶圓薄膜厚度分別為 約 0.25# m 和 0.44/z m。 範例2 在一槽晶圓上之可光固化之平面化材料 藉由在黃光實驗室中完全混合20 g之環氧化物(der. 354LV,D〇w Chemical Co·),80 g之 PGME(Aldrich)以及 i 2 g 芡Sarcat KI-85(Sartomer)來製備一可光固化之材料。然後 以一 〇·2 /z m過濾器來過濾材料並將之儲存於一乾淨的褐瓶 中。 83889 -21 - 200405122 使用一具有約1 v m深之槽結構之矽晶圓來做為基板。此 晶圓之特徵密度範圍從4%至96%。 二小於〇·5 // m厚之可光固化平面化材料之薄膜被旋轉塗覆 :石夕槽晶圓上’其包括不㈣特徵密度區域。晶圓被轉移 ^壓製工具腔室且被置於一基板臺上。將塗覆的基板表 :指向為面對一光學透明的光平坦物體表面。⑮室蓋子被 山封且L主被淨空為小於2 0陶爾。腔壓維持在小於2 〇陶 爾L、.々3 0 #&gt;、以移除殘餘的溶劑。基板臺被升起來以一約$ $ PS1&lt;力量允許基板表面與光學平坦表面接觸達3〇〇秒。在基 板表面以68 psi之壓力與光學平坦表面接觸之同時,透過光 學平坦表面照射一 UV光線達1 〇秒以固化平面化材料。在曝 光後,基板臺被降低。壓製工具腔室從少於2〇陶爾(整個壓 製程序執行之腔室壓力)排放至大氣壓。腔室蓋子打開,且 晶圓從光學平坦表面分離且將之從腔室移除以供特性化。〜 使用除了壓製步驟之外的相同的處理狀況來以相同的材 料塗覆其他槽晶圓。將此晶圓製備為一參考。 以一 Tencor Alphastep輪廓形成器來特性化平面化過的槽 晶圓表面。橫跨結構來測量一約250 A之表面地貌,且橫跨 相鄰的特徵密度區域來測量不超過約5〇 A之地貌改變。參 考晶圓顯現横跨地貌結構約7000 A之測量表面地貌。使用 一掃瞄電子顯微鏡(SEM)來測量在平面化晶圓之不同的特徵 密度區域中之平面化薄膜厚度。測量在特徵密度區域上之 薄膜厚度,其表示在特徵密度中之約40%之最大差異。非在 槽上之結構頂端上之薄膜厚度’在二特徵密度區域中為約 83889 -22- 200405122 0.45# m,具有約〇 〇12#m(12〇A)之厚度差異。 範例3 在一穿孔晶圓上之可熱固化之平面化材料 藉由混合20 g環氧化物(D.E.R. 354LVThe D〇w c — d c〇·)’/ g的 PGME(Aldrich)以及1〇 g的 NAc_超級 xc_ ,催化刈(種熱酸產生物,可由King Industries獲得)來 製:-可熱固化材料,完全地製備和混合。以一〇2”過 濾器來過濾材料並將之儲存在一乾淨的褐瓶中。 使用一包含穿孔之矽晶圓做為基板。首先將矽晶圓塗覆 以—具有約Mm厚度之二氧化石夕薄膜。將一包含〇·2至 直徑之穿孔以及具有不同特徵密度區域之樣式形成至二氧 化矽薄膜上。穿孔深度為約 將一具有約0.2/zm厚度之可熱固化平面化材料之薄膜旋 轉塗覆至具〜有不同特徵密度區域之矽穿孔晶圓上。該晶国 被轉移至一壓製工具腔室且被放置在一基板臺上。被塗覆 、平面化材料之基板表面被定位為面對一光學透明之光平 坦物體表面。將腔室壓力保持在小於2〇陶爾達6〇秒以移除 剩餘的溶劑。提高基板臺以允許基板表面以一約Μ ρ。之力 I與光平坦表面接觸達60秒。在基板表面以一68 psi之壓力 維持與光平坦表面之接觸之同時,透過光平坦表面照射一 脈衝uv/紅外線加熱光以在至少約13〇t:之固化溫度上固化 平面化材料達210秒。在固化程序之後,將壓製工具腔室從 少於20陶爾排放至大氣壓。基板臺被降低,且腔室蓋子被 打開。基板與光平坦表面分離且從腔室移除以供特性化。 83889 -23- 200405122 以一 Tencor Alphastep輪廓形成器來特性化平面化的穿孔 晶圓表面。㈣量橫跨相鄰特徵密度區域之小於1〇〇 A和小於 約300 A之平面化結構上之表面地貌。使用一 sem來測量在 不同特徵密度區域中之結構上的平面化薄膜厚度。測量二 個特徵密度區域。測量在_具有約〇3心直徑穿孔以及約 0.5/zm深度之區域中之結構頂端上的薄膜厚度。亦在一具 有約0 · 3 /z m穿孔以及約1 7 S …、、哎忐、1 , • V m /木度 &lt; 區域中之結構頂端上 測量薄膜厚度。所測量的薄膜厚度分別為約〇 i”m和〇21 /z m 〇 L圖式簡單說明】 圖l(aHc)說明一先前技藝平面化程序之步驟. 其中基 圖2(aHc)說明其他先前技藝平面化程序之步驟 板具有二個不同的特徵密度區域; 圖3(a)-(d)說明根據發明方 接觸平面化程序之步 騾;以及 π 圖4(a)_(d)說明根據發明方法. 力忒又接觸平面化程序之步 騾、、中基板具有二個不同的特徵密度區域。 【圖式代表符號說明】 1 〇基板 12地貌 14平面化材料 1 6穿孔和槽 20基板 22穿孔/槽UJ1ZZ is intended to limit the overall scope of the present invention on a perforated wafer. # Α 丁 was deficient in solidified planar materials. Finished in the Page Lab. , D0W Chemical c, PGME (Aldrich) and 1.2 2 "sarcat KI_85 (one can be produced by Sartomer") to prepare light-curing materials. Then-M, ', · β m filter to Filter the material and store it in a clean brown bottle. A perforated H circle is used as the substrate. The Shi Xi wafer is first coated with a thickness of about 1 # m-Huang Fu Yu Luo Yan, Yu On the other hand, it emulsifies the silicon dioxide film. One has different characteristics, degrees, and has a straight furnace. The pattern of the perforated area is formed in a siliconized silicon film. The depth of the perforation is about 1 # m. A thin film of a photo-curable planar material having a thickness of about one is spin-coated onto a perforated wafer having regions with different pattern characteristic densities. The wafer is transferred: a pressing tool chamber and placed on a substrate table The top surface of the flat material 7 is positioned to face a light The surface is transparent and flat. Press the tool cavity to the quilt material, and the cavity is cleared to less than M Taoer. The cavity to pressure is maintained at less than 2G Taoerda for about 30 seconds to remove the remaining solvent. Substrate ® is lifted to allow the substrate surface to contact the flat surface with a force of about 68 psi for 3 G seconds. While the substrate surface is maintained in contact with the flat surface at a pressure of 68 Torr, a pulse of ultraviolet (uv) light passes through the light The flat surface is irradiated with solid surface material. The pulse of UV light is turned on and off in seconds, and the total exposure time is 3 seconds. After exposure, the pressing tool chamber is discharged from less than 20 Tao ( Carry out the entire pressing procedure of the chamber pressure) to atmospheric pressure. Reduce the 83889 -20-200405122 substrate stage 'and open the chamber mule. The substrate is separated from the smooth flat surface and removed from the chamber for characterization. Use except The same processing conditions other than the step are used to coat other perforated wafers with the same material. This additional wafer is also prepared and characterized and used as a reference wafer. A Tencor Alphastep profile former Characterize the planarized perforated wafer surface. Obtain a landform less than 200 A on the planarized structure and across adjacent feature density regions. Use a focused ion beam (FIB) microscope to measure in different feature density regions The thickness of the planar film on the top of the structure. Measure two characteristic density regions. Measure the thickness of the film on the top of the structure in an area with a perforation of about 0.3 / m in diameter and a landform of about 0.5 am, and a thickness of about 0. .3 / zm diameter perforation and film thickness in an area of about 175 // 111 landform. The thicknesses of the films on the tops of the high structures (not on the tops of the perforations) measured in the two regions were about 0.38 # ㈤ to 孓 0.39 // m, respectively. The thickness of the reference wafer film is measured over an area having the same characteristic density as that in the pressed wafer. The reference wafer film thickness is approximately 0.25 # m and 0.44 / z m, respectively. Example 2 A photo-curable planarizing material on a one-wafer wafer was completely mixed with 20 g of epoxide (der. 354LV, Dow Chemical Co.), 80 g of PGME ( Aldrich) and i 2 g 芡 Sarcat KI-85 (Sartomer) to prepare a photocurable material. The material was then filtered through a 0.2 / zm filter and stored in a clean brown bottle. 83889 -21-200405122 A silicon wafer with a trench structure with a depth of about 1 v m is used as the substrate. The characteristic density of this wafer ranges from 4% to 96%. Two thin films of photo-curable planarization material less than 0.5 m / m thick are spin-coated: on a shixi groove wafer 'which includes a region of characteristic density. The wafer is transferred to the press tool chamber and placed on a substrate table. Point the coated substrate: Point to face the surface of an optically transparent light flat object. The lid of the chamber was sealed by a mountain and the main clearance of L was less than 20 Tao. The cavity pressure was maintained at less than 200 tal L, .々3 0 # &gt; to remove residual solvent. The substrate table is raised with a force of approximately PS1 &lt; to allow the substrate surface to contact the optically flat surface for 300 seconds. While the substrate surface was in contact with the optically flat surface at a pressure of 68 psi, a UV ray was irradiated through the optically flat surface for 10 seconds to cure the planarization material. After exposure, the substrate stage is lowered. The pressing tool chamber is vented to atmospheric pressure from less than 20 Tao (the pressure of the chamber during which the entire pressing process is performed). The chamber lid is opened and the wafer is detached from the optically flat surface and removed from the chamber for characterization. ~ Coat other grooved wafers with the same material using the same processing conditions except the pressing step. This wafer was prepared as a reference. A Tencor Alphastep profiler was used to characterize the planarized grooved wafer surface. A surface topography of about 250 A was measured across the structure, and topographic changes of no more than about 50 A were measured across adjacent feature density regions. The reference wafer showed a measured surface topography of approximately 7000 A across the topography. A scanning electron microscope (SEM) was used to measure the thickness of the planarized film in different feature density regions of the planarized wafer. The film thickness is measured over the characteristic density region, which represents the largest difference of about 40% in the characteristic density. The thickness of the thin film on the top of the structure other than the groove is about 83889-22-200405122 0.45 # m in the two characteristic density region, and has a thickness difference of about 〇12 # m (12〇A). Example 3 A thermally curable planarizing material on a perforated wafer was mixed with 20 g of epoxide (DER 354LV The D0wc — dc〇 ·) '/ g of PGME (Aldrich) and 10 g of NAc_ Super xc_, catalytic rhenium (a kind of thermal acid generator, available from King Industries) to make:-heat-curable materials, fully prepared and mixed. Filter the material with a 102 ”filter and store it in a clean brown bottle. A silicon wafer containing a perforation is used as the substrate. The silicon wafer is first coated with—with a thickness of about Mm of dioxide. Shi Xi film. A pattern including a perforation of 0.2 to a diameter and a region with different characteristic density is formed on the silicon dioxide film. The depth of the perforation is about one of a heat-curable planarization material with a thickness of about 0.2 / zm. The film is spin-coated onto silicon-perforated wafers with areas with different characteristic densities. The wafer is transferred to a pressing tool chamber and placed on a substrate table. The surface of the substrate being coated and planarized is Positioned to face a flat surface of an optically transparent light. Keep the chamber pressure at less than 20 Taoerda for 60 seconds to remove the remaining solvent. Raise the substrate table to allow the substrate surface with a force of about Μρ. I is in contact with the light flat surface for 60 seconds. While the substrate surface is maintained in contact with the light flat surface at a pressure of 68 psi, a pulse of UV / IR heating light is irradiated through the light flat surface to at least about 13 t: The flattening material is cured at a temperature of 210 seconds. After the curing process, the pressing tool chamber is vented from less than 20 Taoer to atmospheric pressure. The substrate table is lowered and the chamber lid is opened. The substrate is separated from the smooth flat surface and Removed from the chamber for characterization. 83889 -23- 200405122 A Tencor Alphastep profiler was used to characterize the planarized perforated wafer surface. The volume was less than 100A and less than 100A across adjacent feature density regions. Surface topography on a planar structure of about 300 A. Use a sem to measure the thickness of the planarized film on the structure in different feature density regions. Measure two feature density regions. Measure a perforation with a core diameter of about 0.3 and The thickness of the film on the top of the structure in a region with a depth of about 0.5 / zm. Also in a region with a perforation of about 0.3 / zm and about 1 7 S ..., oops, 1, Vm / woodiness &lt; The thickness of the film is measured on the top of the structure. The measured thicknesses of the film are about 〇i ”m and 〇21 / zm 〇L Schematic illustration] Figure l (aHc) illustrates the steps of a prior art planarization process. 2 (aH c) illustrates that the step boards of other prior art planarization procedures have two different feature density regions; Figures 3 (a)-(d) illustrate the steps of contacting the planarization procedure according to the inventor; and π Figure 4 (a) _ (d) Explain that according to the method of the invention, the force contacting the step of the planarization procedure, the substrate has two different characteristic density regions. [Illustration of Symbols in the Drawings] 1 〇 Substrate 12 Landform 14 Planarization material 1 6 Perforation and groove 20 Substrate 22 Perforation / groove

83889 -24- 200405122 24,26 區域 2 8平面化層 3 0第二層 32基板 34結構或特徵 3 6平面化詹料 38全域平面表面 40光阻層_ 42基板 46區域 44結構或特徵 48 區域 50平面化材料 52全域平面表面 54光阻層 -25 - 8388983889 -24- 200405122 24,26 area 2 8 planarization layer 3 0 second layer 32 substrate 34 structure or feature 3 6 planarization material 38 global planar surface 40 photoresist layer _ 42 substrate 46 area 44 structure or feature 48 area 50 planarization material 52 global planar surface 54 photoresist layer -25-83889

Claims (1)

200405122 拾、申請專利範圍: 1 · 一種形成一微電子前導之女、土 . ’ 万去’孩万法包含下列步驟: (a) 提供一基板,JL且古 主&amp; ^ 〃具有一表面且包括複數個在該表 面上之地貌特徵; (b) 在該表面上形成一平面化層; (c) 以物之平面表面接觸平面化層達足夠的時 間[力和/皿度,以將平面表面之平坦轉移至平面化層; ⑷選擇性地形成一或多個中間層於該平面化層上; 以及 ⑷形成-成像層以得到微電子前導,若存在的話$ 成像層係被形成於該中間層上,或若不存在中間層的話; 在該平面化層上。 (f) 在該成像層上建立一樣式· (g) 先存在的話將該樣式轉移至該中間層,以及至, 平面化層,其中在該轉移步 兮1』支 一 + &lt;後,这基板表面保留並力 始地貌至少一部份。 ’、&quot; 2. 如申請專利範圍第丨項之方 4十面化層包含一由聚名 物、單體、寡聚物、或其混人、 此口物所構成芡群組中所 之化合物。 ' 3. 如帽專利範圍第2項之方法,該平面化層進—步包含一 由酸、酸產生物、鹼、驗產 ^ ^ ^ &quot; 座生物、表面活性劑、光起發 劑、為起發劑、及其混合物 份。 所構成〈群組所選擇之組成部 4·如申請專利範圍第2項之方法,並 〃中β化a物係從由環氧 83889 200405122 化物、壓克力鹽、乙醚乙缔、聚醋、有機和無機單體、 寡聚物、和聚合物、以及含乙缔之有機和無機單體、寡取 物和聚合物及有前述之混合物所構成之群組中所選擇水 5·如申請專利範圍第1項之方法,其進-步包括在該接觸步 驟期間或之後之大致固化或硬化該平面化層之步驟。 6·如申請專利範圍第5項之方法,其中該固:或硬:步驟包 含使該平面化層受UV光線作用達足夠的時間以實質固化 該合成物。 7. 如申請專利範圍第5項之方法,其中該固化或硬化步驟包 含將該平面化層加熱達一足夠的時間和溫度來實質硬化= 平面化層。 8. 如申請專利範圍第7項之方法,其中該固化或硬化步驟包 含將該平面化層冷卻至約其丁^以下。 9. 如申請專利範圍第7項之方法,其中該加熱包含使用—輳 射熱源來加熱該平面化層。 〜 10. 如申請專利範圍第7項之方法,其中該加熱包含使用汛熱 來加熱該平面化層。 11 ·如申請專利範圍第丨項之方法,其中在周圍壓力下執行步 驟(c) 〇 12.如申請專利範圍第丨項之方法,其中在真空下執行步驟 (c)。 1 3 ·如申請專利範圍第丨項之方法,其中在提高的壓力上執行 步驟(c)。 14.如申請專利範圍第1項之方法,其中步驟(c)係於一人工 83889 200405122 溫度下執行。 I5·如申請專利範圍第丨項之方法, 一 驟係以—從 驟係於—從 步驟執行達 /、中該接觸牛 約1-1,000 psi之壓力應用加以執行。 y 16·如申請專利範圍第丨項之方法,戈、 約周圍溫度至約35(TC之溫度上執行孩接觸步 17·如申請專利範圍第1項之方法,其切該接觸 一從約1秒至約120分鐘之時間。 1 8 ·如申睛專利範圍第}項之方法,其中存在有: 層,且各中間層基本上係無金屬。 或夕個中間 1 9 ·如申凊專利範圍第1項之方法,其中·· 該成像層包含一光阻層; 光阻層之部份曝露至uv 該建立步驟包含選擇性地將該 光線;以及 該轉移步驟包含形成該光阻層,若存在的話該中間層; 以及該平面化層。 4 20·如申請專利範圍第1項之方法,其中: $衾成像層包含《^墨印層; 該建立步驟包含以該壓印層接觸一負像,該負像具有 /包含樣式負像之壓印表面;以及 該轉移步驟包含若存在的話透過該中間層蝕刻該樣 式,以及該平面化層。 2 1.如申請專利範圍第1項之方法,其中: 該成像層包含一打印之樣式;以及 該轉移步驟包含若存在的話透過該中間層蝕刻該樣 83889 200405122 式,以及該平面化層。 22. 如申請專利範圍第1項之方法,其進一步包括在該微電子 前導上重覆步驟(a)_(g)至少一些之步驟。 23. 如申請專利範圍第1項之方法,其中存在至少一中間層, 該中間層係選自由光罩層、位障層、和抗反射層構成之群 組。 24·如申請專利範圍第1項之方法,其中步驟(c)結果造成一 平面化層,其在約10,000 // 111之距離上具有少於約1〇%之 薄膜厚度變異。 25·如申請專利範圍第i項之方法,其中步驟(c)造成一平面 化層,其在任何個別基板地貌特徵上具有一小於25〇人之 地貌特徵。 26.如申請專利範圍第”員之方法,其中步驟(c)造成一平面 化層,其在約10,000 /zm之基板表面長度上具有少於約6〇〇 A之地貌,在該處至少有二不同的特徵密度區域存在於該 基板表面長度上。 2 7 · —種組合: 一具有一表面和在該表面上有複數個地貌特徵之某 板; &amp; 一在該-表面上之全域平面的、固 Μ化的或硬化的平面化 層; 在該平面化層上選擇性的一或多個中間層;以及 若存在的話一在該中間層上之成像層,或若無存在 間層的法在該平面化層上。 83889 -4- 200405122 认如申請專利範圍第27項之組合’其中該基板係從切晶 圓、化合物半導體晶圓、絕緣體上石夕晶圓、玻璃基板、 石英基板、有機聚合物基板、合成材料基板、介電基板、 金屬基板、合金基板、碳化矽基板、氮化矽基板、藍寶 石基板、陶製基板、以及由耐火材料構成之基板構成之群 組中選擇。 29. 如申請專利範圍第27項之组合,其中該平面化層係由一 合成物形成的,該合成物包含一從由聚合物、單體、寡聚 物和其混合物構成之群組所選擇。 30. 如申請專利範圍第29項之组合,該合成物進一步包含一 由酸、酸產生物、驗、驗產生物、界面活性劑、光起發 劑、熱起發劑及其之混合物所構成之群組中選擇之組成部 份0 31·,申請專利範圍第29項之組合,其中該化合物係選自亨. 氧化物、壓克力鹽、乙烯乙驗、聚醋、多硫亞氨、有機 和”、、機單體、暴聚物、和聚合物、以及含有乙烯之有機和 ”、、機單m、暴聚物和聚合物,以及前述之混合物。 32_如申請專利範圍第27項之組合,其中存在至少一中間層, 邊中間層係從由光罩層、障礙層、和抗反射層構成之群組 中選擇。_ 33·如申凊專利範圍第27項之纟且合,其中該平面化層具有從 約0·Μ〇// m之厚度。 34.如申請專利範圍第27項之級合,其中該組合係一微電機 系統結構,且該平面化層具有一從約之厚度。 83889 200405122 3 5 ·如申凊專利範圍第2 7項之組合,其中存在至少一中間層, 該中間層係從由光罩層、障礙層、和抗反射層所構成之群 組選擇出來。 36·如申請專利範圍第27項之組合,其中該成像層係從由光 阻層、壓印層和打印層構成之群組中選擇出來。 37.如申請專利範圍第27項之組合,該平面化層在約⑼ V m之距離上具有一少於約1 〇%之薄膜厚度變異。 3 8·如申請專利範圍第27項之組合,其中該平面化層在任何 個別基板地貌特徵上具有少於約25〇人之地貌。 39·如申請專利範圍第27項之組合,其中該平面化層在一約 1〇,〇〇〇#!!1之基板表面長度上具有一少於約6〇()人之地貌, 其中在該基板表面長度上存在至少二不同的特徵密度區 域0 ’該方法包含下列步驟 面且在該表面上包括複 40· —種形成一微電子前導物之方法 (a) 挺供一基板,其具有一表 數個地貌特徵; (b) 在该表面上形成一平面化層; (c) 將平面化層與一物士 初&lt;千坦表面接觸達足夠的時 間、壓力和溫度,以將平扭类 —表面义平坦轉移至平面化層; (d) 在該平面化層上選擇性 谭f生地形成一或多個中間層, 該中間層基本上係無金屬;以及 電子前導物,若中間層存 間層上,或若無中間層的 (e)形成一成像層以得到微 在的話,該成像層係形成於該中 話形成於該平面化層上。 83889 '6- 200405122 41 · 一種形成一微電子前導物之方法,該方法包含下列步驟: (a) ^供一基板,其具有一表面且在該表面上包括複 數個地貌特徵; (b) 在該表面上形成一平面化層; (c) 將平面化層與一平坦物體之平坦表面接觸達足夠 的時間、壓力和溫度’以將平坦表面之平坦性轉移至平面 化層; (d) 選擇性地在該平面化層上形成一或多個中間層; 以及 (e) 开^成一成像層以得到微電子前導物,若中間層存 在的忐,该成像層係形成於該中間層上,或若無中間層存 在的話形成於該平面化層上。 42· —種組合: 一微電子基板,其具有一表面和在該表面上之複數個. 地貌特徵; ’ ; 一在孩表面上《全域平面的、固化的或硬化的平面化 層; 在該平面化層上之選擇性—或多個中間層,該中間層 基本上係無金屬;以及 若存在-的話在該中間層上之-成像層,若沒有中間層 存在的話在該平面化層上之一成像層。 83889200405122 The scope of patent application: 1 · A daughter and a soil to form a microelectronic leader. The 'Wan Qu' baby method includes the following steps: (a) Provide a substrate, JL and the ancient master & ^ 〃 has a surface and Including a number of topographical features on the surface; (b) forming a planarization layer on the surface; (c) contacting the planarization layer with the planar surface of the object for a sufficient time [force and / degree, to The flatness of the surface is transferred to the planarization layer; (i) selectively forming one or more intermediate layers on the planarization layer; and (ii) forming an imaging layer to obtain a microelectronic leader, if present, an imaging layer is formed on the On the intermediate layer, or if there is no intermediate layer; on the planarization layer. (f) Establish a pattern on the imaging layer. (g) Transfer the pattern to the intermediate layer if it exists first, and to the planarization layer, where after the transfer step 1 ′ + 1 +, this At least a part of the landform remains on the substrate surface. ', &Quot; 2. For example, the aspect 40 of the scope of the patent application includes a compound consisting of a polymer, a monomer, an oligomer, or a mixture thereof, and a group consisting of the same. . '3. As in the method of Cap 2 of the patent, the planarization layer further includes an acid, an acid generator, a base, and an inspection ^ ^ ^ ^ organism, surfactant, light hair agent, It is a hair conditioner and a mixture thereof. The constituents selected by the group 4. If the method of the scope of patent application is the second item, the β-a compound is composed of epoxy 83889 200405122 compound, acrylic salt, ethyl ether, polyacetate, Organic and inorganic monomers, oligomers, and polymers, and organic and inorganic monomers, oligomers and polymers containing ethylene, and selected water in the group consisting of the foregoing mixtures The method of item 1 further includes a step of substantially curing or hardening the planarizing layer during or after the contacting step. 6. The method of claim 5, wherein the solid: or hard: step includes subjecting the planarizing layer to UV light for a sufficient time to substantially cure the composition. 7. The method of claim 5, wherein the curing or hardening step includes heating the planarization layer for a sufficient time and temperature to substantially harden = the planarization layer. 8. The method according to item 7 of the patent application, wherein the curing or hardening step includes cooling the planarization layer to a temperature below about 3,000 square meters. 9. The method of claim 7, wherein the heating comprises heating the planarization layer using a 辏 -radiation heat source. ~ 10. The method according to item 7 of the scope of patent application, wherein the heating includes using flood heat to heat the planarization layer. 11 · The method according to the scope of the patent application, wherein step (c) is performed under ambient pressure. 12. The method according to the scope of the patent application, wherein step (c) is performed under vacuum. 1 3 · The method according to the scope of patent application, wherein step (c) is performed under increased pressure. 14. The method of claim 1, wherein step (c) is performed at an artificial temperature of 83889 200405122. I5. If the method in the scope of the patent application is applied, the first step is-from step to-from step to step, and the pressure of the contact cattle is about 1 to 1,000 psi. y 16. If the method of the scope of the patent application is applied, perform the contact step at a temperature of about ambient temperature to about 35 ° C (17.) If the method of the scope of the patent application is applied, the contact should be changed from about 1 Time from seconds to about 120 minutes. 1 8 · The method of item No.} in Shen Jing's patent scope, which includes: layers, and each intermediate layer is essentially metal-free. The method of item 1, wherein: the imaging layer includes a photoresist layer; a portion of the photoresist layer is exposed to UV; the establishing step includes selectively irradiating the light; and the transfer step includes forming the photoresist layer. If present, the intermediate layer; and the planarization layer. 4 20. The method according to item 1 of the scope of patent application, wherein: the imaging layer includes an ink layer; the step of establishing includes contacting the imprint layer with a negative Image, the negative image has / embossed surface of the negative image of the pattern; and the transferring step includes etching the pattern through the intermediate layer, if present, and the planarization layer. 2 1. Method as claimed in item 1 of the scope of patent application Where: The imaging Including a printed pattern; and the transferring step including etching the 83889 200405122 formula and the planarization layer through the intermediate layer, if present. 22. The method according to item 1 of the patent application scope, further comprising the microelectronics The preamble repeats at least some of the steps (a)-(g). 23. As in the method of claim 1 of the patent scope, there is at least one intermediate layer selected from the group consisting of a photomask layer, a barrier layer, And an anti-reflection layer. 24. The method of claim 1 in which the result of step (c) results in a planarization layer having less than about 10% at a distance of about 10,000 // 111 The thickness variation of the film. 25. The method according to item i of the patent application, wherein step (c) results in a planarization layer, which has a landform feature of less than 250 people on any individual substrate landform feature. 26. If applied The method of the patent scope, wherein step (c) results in a planarization layer, which has a landform of less than about 600A over a substrate surface length of about 10,000 / zm, and has at least two different features there. The degree region exists on the length of the surface of the substrate. 2 7 ·-a combination: a plate having a surface and a plurality of landform features on the surface; &amp; a global planar, solid surface on the surface A planarized or hardened planarization layer; one or more intermediate layers selectively on the planarization layer; and an imaging layer on the intermediate layer, if present, or on the surface if no interlayer method is present 83889 -4- 200405122 It is considered as the combination of patent application No. 27, where the substrate is cut from wafer, compound semiconductor wafer, insulator wafer, glass substrate, quartz substrate, organic polymer Select from the group consisting of substrate, synthetic material substrate, dielectric substrate, metal substrate, alloy substrate, silicon carbide substrate, silicon nitride substrate, sapphire substrate, ceramic substrate, and substrate made of refractory material. 29. The combination of claim 27, wherein the planarization layer is formed of a composition selected from the group consisting of a polymer, a monomer, an oligomer, and a mixture thereof . 30. According to the combination of item 29 in the scope of patent application, the composition further comprises an acid, an acid generator, a test, a test product, a surfactant, a light hair-generating agent, a thermal hair-generating agent, and a mixture thereof. The selected component in the group is 0 31 ·, the combination of the scope of application for item 29, wherein the compound is selected from the group consisting of H. oxide, acrylic salt, ethylene test, polyacetate, polythioimine, "Organic sum", organic monomers, oligomers, and polymers, and organic sums containing ethylene ", organic monomers, oligomers and polymers, and mixtures of the foregoing. 32_ The combination of item 27 of the patent application scope, wherein there is at least one intermediate layer, and the edge intermediate layer is selected from the group consisting of a photomask layer, a barrier layer, and an anti-reflection layer. 33. The combination of the 27th item in the patent application range, wherein the planarization layer has a thickness of from about 0 · M0 // m. 34. The cascade of item 27 in the scope of patent application, wherein the combination is a micro-motor system structure, and the planarization layer has a thickness of about 300 Å. 83889 200405122 3 5 As in the combination of claim 27 of the patent scope, there is at least one intermediate layer, the intermediate layer is selected from the group consisting of a mask layer, a barrier layer, and an anti-reflection layer. 36. The combination of claim 27 in the scope of patent application, wherein the imaging layer is selected from the group consisting of a photoresist layer, an imprint layer, and a print layer. 37. According to the combination of claim 27 in the scope of the patent application, the planarization layer has a film thickness variation of less than about 10% at a distance of about ⑼ V m. 38. The combination of item 27 in the scope of the patent application, wherein the planarization layer has a landform of less than about 250 people on any individual substrate landform feature. 39. The combination of item 27 in the scope of the patent application, wherein the planarization layer has a landform of less than about 60 () people on a substrate surface length of about 10,00 ## 1, where There are at least two different characteristic density regions on the surface length of the substrate. The method includes the following steps and includes on the surface a method of forming a microelectronic precursor. (A) A substrate is provided, which has A table of several topographic features; (b) forming a planarizing layer on the surface; (c) contacting the planarizing layer with a surface of the <br> <> Tantan for sufficient time, pressure, and temperature to Twisting—the surface is transferred flat to the planarization layer; (d) one or more intermediate layers are selectively formed on the planarization layer, and the intermediate layer is essentially metal-free; and the electron precursor, if intermediate On the interlayer, or if (e) without an intermediate layer forms an imaging layer to obtain micro-presence, the imaging layer is formed on the intermediate layer and on the planarization layer. 83889 '6- 200405122 41 · A method for forming a microelectronic precursor, the method includes the following steps: (a) a substrate having a surface and including a plurality of landform features on the surface; (b) in A planarizing layer is formed on the surface; (c) The planarizing layer is brought into contact with the planar surface of a flat object for a sufficient time, pressure, and temperature 'to transfer the flatness of the planar surface to the planarizing layer; (d) selecting Forming one or more intermediate layers on the planarizing layer; and (e) forming an imaging layer to obtain a microelectronic precursor, and if the intermediate layer exists, the imaging layer is formed on the intermediate layer, Or formed on the planarization layer if no intermediate layer is present. 42 · —a combination: a microelectronic substrate having a surface and a plurality of the geomorphological features on the surface; Selectivity on the planarization layer—or multiple intermediate layers, which are essentially metal-free; and—if present—on the intermediate layer—the imaging layer, if no intermediate layer exists on the planarization layer One imaging layer. 83889
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