US9612521B2 - Amorphous layer extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor - Google Patents

Amorphous layer extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor Download PDF

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US9612521B2
US9612521B2 US14139371 US201314139371A US9612521B2 US 9612521 B2 US9612521 B2 US 9612521B2 US 14139371 US14139371 US 14139371 US 201314139371 A US201314139371 A US 201314139371A US 9612521 B2 US9612521 B2 US 9612521B2
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layer
blank
mask
ultraviolet
euv
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Ralf Hofmann
Kevin Moraes
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Applied Materials Inc
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Applied Materials Inc
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultra-violet [EUV] masks; Preparation thereof
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/221Ion beam deposition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/35Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/35Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C23C14/352Sputtering by application of a magnetic field, e.g. magnetron sputtering using more than one target
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54Controlling or regulating the coating process
    • C23C14/541Heating or cooling of the substrates
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Exposure apparatus for microlithography
    • G03F7/708Construction of apparatus, e.g. environment, hygiene aspects or materials
    • G03F7/7095Materials, e.g. materials for housing, stage or other support having particular properties, e.g. weight, strength, conductivity, thermal expansion coefficient
    • G03F7/70958Optical materials and coatings, e.g. with particular transmittance, reflectance

Abstract

An integrated extreme ultraviolet blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a deposition system for depositing a multi-layer stack without removing the substrate from the vacuum; and a treatment system for treating a layer on the multi-layer stack to be deposited as an amorphous metallic layer. A physical vapor deposition chamber for manufacturing an extreme ultraviolet mask blank includes: a target, comprising molybdenum alloyed with boron. An extreme ultraviolet lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for placing an extreme ultraviolet mask blank with a multi-layer stack having an amorphous metallic layer; and a wafer stage for placing a wafer. An extreme ultraviolet blank includes: a substrate; a multi-layer stack having an amorphous metallic layer; and capping layers over the multi-layer stack.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/778,351 filed Mar. 12, 2013, and the subject matter thereof is incorporated herein by reference thereto.

The present application contains subject matter related to a concurrently filed U.S. patent application Ser. No. 14/139,307 filed Dec. 23, 2013. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto.

The present application contains subject matter related to a concurrently filed U.S. patent application Ser. No. 14/139,415 filed Dec. 23, 2013. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto.

The present application contains subject matter related to a concurrently filed U.S. patent application Ser. No. 14/139,457 filed Dec. 23, 2013. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto.

The present application contains subject matter related to a concurrently filed U.S. patent application Ser. No. 14/139,507 filed Dec. 23, 2013. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto.

TECHNICAL FIELD

The present invention relates generally to extreme ultraviolet lithograph blanks, and manufacturing and lithography systems for such extreme ultraviolet lithograph blanks.

BACKGROUND

Extreme ultraviolet lithography (EUV, also known as soft x-ray projection lithography) is a contender to replace deep ultraviolet lithography for the manufacture of 0.13 micron, and smaller, minimum feature size semiconductor devices.

However, extreme ultraviolet light, which is generally in the 5 to 40 nanometer wavelength range, is strongly absorbed in virtually all materials. For that reason, extreme ultraviolet systems work by reflection rather than by transmission of light. Through the use of a series of mirrors, or lens elements, and a reflective element, or mask blank, coated with a non-reflective absorber mask pattern, the patterned actinic light is reflected onto a resist-coated semiconductor wafer.

The lens elements and mask blanks of extreme ultraviolet lithography systems are coated with reflective multilayer coatings of materials such as molybdenum and silicon. Reflection values of approximately 65% per lens element, or mask blank, have been obtained by using substrates that are coated with multilayer coatings that strongly reflect light essentially at a single wavelength within a extremely narrow ultraviolet bandpass; e.g., 12 to 14 nanometer bandpass for 13 nanometer ultraviolet light.

There are various classes of defects in semiconductor processing technology which cause problems. Opaque defects are typically caused by particles on top of the multilayer coatings or mask pattern which absorb light when it should be reflected. Clear defects are typically caused by pinholes in the mask pattern on top of the multilayer coatings through which light is reflected when it should be absorbed. And phase defects are typically caused by scratches and surface variations beneath the multilayer coatings which cause transitions in the phase of the reflected light. These phase transitions result in light wave interference effects which distort or alter the pattern that is to be exposed in the resist on the surface of the semiconductor wafer. Because of the shorter wavelengths of radiation which must be used for sub-0.13 micron minimum feature size, scratches and surface variations which were insignificant before now become intolerable.

While progress has been made in reducing or eliminating particle defects and work has been done on repair of opaque and clear defects in masks, to date nothing has been done to address the problem of phase defects. For deep ultraviolet lithography, surfaces are processed to maintain phase transitions below 60 degrees. Similar processing for extreme ultraviolet lithography is yet to be developed.

For an actinic wavelength of 13 nanometers, a 180 degree phase transition in the light reflected from the multilayer coating may occur for a scratch of as little as 3 nanometers in depth in the underlying surface. This depth gets shallower with shorter wavelengths. Similarly, at the same wavelength, surface variations more abrupt than one (1) nanometer rise over one hundred (100) nanometers run may cause similar phase transitions. These phase transitions can cause a phase defect at the surface of the semiconductor wafer and irreparably damage the semiconductor devices.

In the past, mask blanks for deep ultraviolet lithography have generally been of glass but silicon or ultra low thermal expansion materials have been proposed as alternatives for extreme ultraviolet lithography. Whether the blank is of glass, silicon, or ultra low thermal expansion material, the surface of the mask blank is made as smooth as possible by such processes a chemical mechanical polishing, magneto-rheological finishing, or ion beam polishing. The scratches that are left behind in such a process are sometimes referred to as “scratch-dig” marks, and their depth and width depend upon the size of the particles in the abrasive used to polish the mask blank. For visible and deep ultraviolet lithography, these scratches are too small to cause phase defects in the pattern on the semiconductor wafer. However, for extreme ultraviolet lithography, scratch-dig marks are a significant problem because they will appear as phase defects.

Due to the short illumination wavelengths required for EUV lithography the pattern masks used must be reflective mask instead of the transmissive masks used in current lithography. The reflective mask is made up of a precise stack of alternating thin layers of molybdenum and silicon, which creates a Bragg refractor or mirror. Because of the nature of the multilayer stack and the small feature size, any imperfections in the surface of the substrate on which the multilayer stack is deposited will be magnified and impact the final product. Imperfections on the scale of a few nanometers can show up as printable defects on the finished mask and need to be eliminated from the surface of the mask blank before deposition of the multilayer stack.

Mask blanks are a critical item for the adoption of EUV lithography. The main hurdles relate to defectivity and the reflectance of the mask blank. The mask has a Bragg reflector of 80 alternating layers of molybdenum (Mo) and silicon (Si) deposited on it. The roughness of this layer stack is critical and relates to line edge roughness on the printed wafer.

The need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.

Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

SUMMARY

An embodiment of the present invention provides an integrated extreme ultraviolet blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a deposition system for depositing a multi-layer stack without removing the substrate from the vacuum; and a treatment system for treating a layer on the multi-layer stack to be deposited as an amorphous metallic layer.

An embodiment of the present invention provides a physical vapor deposition chamber for manufacturing extreme ultraviolet mask blanks includes: a target, comprising molybdenum alloyed with boron.

An embodiment of the present invention provides an extreme ultraviolet lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for placing an extreme ultraviolet mask blank with a multi-layer stack having an amorphous metallic layer; and a wafer stage for placing a wafer.

An embodiment of the present invention provides an extreme ultraviolet blank includes: a substrate; a multi-layer stack having an amorphous metallic layer; and capping layers over the multi-layer stack.

Certain embodiments of the invention have other elements in addition to or in place of those mentioned above. The steps or element will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an integrated extreme ultraviolet (EUV) mask production system.

FIG. 2 is a EUV mask blank in accordance with an embodiment of the present invention.

FIG. 3 is the EUV mask blank in an intermediate stage of manufacture.

FIG. 4 is the EUV mask blank in an intermediate stage of manufacture.

FIG. 5 is an optical train for a EUV lithography system.

FIG. 6 is a EUV lithography system.

DETAILED DESCRIPTION

The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.

The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing FIGS. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the FIGS. is arbitrary for the most part. Generally, the invention can be operated in any orientation.

Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will be described with similar reference numerals.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of a mask blank, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures. The term “on” indicates that there is direct contact between elements.

The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.

Embodiments of the present invention use various established techniques for depositing silicon, silicon oxide, and related layers of compatible thermal expansion coefficient by CVD, PVD, ALD, and flowable CVD to fill the pits and bury the defects. Once deposited, the layer's surface maybe smooth and flat enough for further multilayer stack deposition, or may then be smoothed further using a variety of established smoothing or polishing techniques, including CMP, annealing, or ion beam polishing.

Referring now to FIG. 1, therein is shown an integrated extreme ultraviolet (EUV) mask blank production system 100. The integrated EUV mask blank production system 100 includes a mask blank loading and carrier handling system 102 into which mask blanks 104 are loaded. An airlock 106 provides access to a wafer handling vacuum chamber 108. In the embodiment shown, the wafer handling vacuum chamber 108 contains two vacuum chambers, a first vacuum chamber 110 and a second vacuum chamber 112. Within the first vacuum chamber 110 is a first wafer handling system 114 and in the second vacuum chamber 112 is a second wafer handling system 116.

The wafer handling vacuum chamber 108 has a plurality of ports around its periphery for attachment of various other systems. The first vacuum chamber 110 has a degas system 118, a first physical vapor deposition system 120, a second physical vapor deposition system 122, and a preclean system 124.

The second vacuum chamber 112 may have various treatment systems, such as a first multi-cathode source 126, a flowable chemical vapor deposition (FCVD) system 128, a cure system 130, and a second multi-cathode source 132, connected to it.

The first wafer handling system 114 is capable of moving wafers, such as a wafer 134, among the airlock 106 and the various systems around the periphery of the first vacuum chamber 110 and through slit valves in a continuous vacuum. The second wafer handling system 116 is capable of moving wafers, such as a wafer 136, around the second vacuum chamber 112 while maintaining the wafers in a continuous vacuum.

Referring now to FIG. 2, therein is shown a EUV mask blank 200 in accordance with an embodiment of the present invention. The EUV mask blank 200 has an ultra-low thermal expansion substrate 202 of glass, silicon, or other ultra-low thermal expansion material. The ultra-low thermal expansion materials include fused silica, fused quartz, calcium fluoride, silicon carbide, silicon oxide-titanium oxide alloy, or other material having a thermal coefficient of expansion within the range of these materials.

The top surface of the ultra-low expansion substrate 202 has imperfections 203, such as pits, scratches, and particles, which result from chemical mechanical polishing (CMP) with an abrasive. The scratches that are left behind in such a process are sometimes referred to as “pits” and/or “scratch-dig” marks, and their depth and width depend upon the size of the particles in the abrasive used to polish the EUV mask blank 200.

It has been discovered that the imperfections in the EUV mask blank 200 can be eliminated by deposition of a planarization layer 204. The planarization layer 204, or flowable film, can be formed by depositing a flowable CVD film or depositing silicon, silicon oxide, or related films by CVD, PVD, or similar processes over the ultra-low expansion substrate 202. This step buries particles and other defects that are on the ultra-low expansion substrate 202.

In the case of flowable CVD films, no further processing may be required to achieve an acceptably smooth, flat surface 205 over the ultra-low expansion substrate 202. For silicon, silicon oxide, or related films, smoothing after deposition may be required. This smoothing can be done by a variety of polishing methods including, but not limited to CMP, chemical polishing, ion beam polishing or annealing. These smoothing techniques can also be applied to the flowable CVD film if further smoothing is required.

A multi-layer stack 206 is formed above the planarization layer 204 to form a Bragg reflector. Due to the transmissive nature of the optics and illuminating wavelengths used in EUV, reflective optics are used and the multi-layer stack 206 may be made of alternating layers of high-Z and low-Z materials, such as molybdenum and silicon, which form a reflector.

A capping layer 208 is formed above the multi-layer stack 206. The capping layer can be a material such as ruthenium (Ru) or a non-oxidized compound thereof to help protect the multi-layer stack 206 from oxidation and any chemical etchants to which the EUV mask blank 200 may be exposed during mask processing. Other material such as titanium nitride, boron carbide, silicon nitride, ruthenium oxide, and silicon carbide may also be used in the capping layer 208.

An absorber layer 210 is placed over the capping layer 208. The absorber layer 210 is of a material having a high absorption coefficient for a particular frequency of EUV light (about 13.5 nm) and may be a material such chromium, tantalum or nitrides thereof.

An anti-reflective coating (ARC) 212 is deposited over the absorber layer 210. The ARC 212 can be of a material such as tantalum oxynitride or tantalum boron oxide.

A backside chucking layer 214 is formed over the rear surface of the ultra-low expansion substrate 202 for chucking the substrate on or with an electrostatic chuck (not shown).

Referring now to FIG. 3, therein is shown the EUV mask blank 200 in an intermediate stage of manufacture.

During deposition of the multi-layer stack 206, the metallic layer 300 can be alloyed. It has been discovered that an alloyed deposition 302 can prevent the metallic layer 300 from being deposited as a polycrystalline layer. Instead, the metallic layer 300 can be maintained as an amorphous metallic layer 300.

For example, the alloyed deposition 302 can be performed in the second vacuum chamber 112 of FIG. 1 where the first multi-cathode source 126 is a boron alloyed molybdenum target and the second multi-cathode source 132 is a silicon target. The first multi-cathode source 126 and the second multi-cathode source 132 are angled with respect to a rotatable pedestal adapted to receive the substrate 202. Boron alloying will maintain the molybdenum in an amorphous state. By maintaining an amorphous phase in the metallic layer 300, the overall roughness of the multi-layer stack 206 is improved by having better EUV reflectivity with less flare than without the molybdenum in the amorphous state.

In an alternative method, it has been discovered that a gas 304, such as nitrogen, can be added to the sputter gas to disrupt the structure of the deposited molybdenum to also form an amorphous phase in the metallic layer 300.

Referring now to FIG. 4, therein is shown the EUV mask blank 200 in an intermediate stage of manufacture. The EUV mask blank 200 is held on a treatment system, such as an electrostatic chuck 404 with cooling passages 406. The electrostatic chuck 404 is the rotatable pedestal adapted to receive the substrate 202.

An ion beam, plasma, or magnetron sputtering tool 132 is used to deposit the multi-layer stack over the substrate. The silicon layer is deposited as an amorphous layer, while the molybdenum layer is polycrystalline. This morphology causes higher surface roughness of the molybdenum layer which then propagates through the stack. To achieve the required smoothness of the film stack ion beam polishing is at times employed to decrease roughness. This is a cumbersome process flow that does not meet the productivity requirements.

It has been shown in Magnetic RAM (MRAM) that B-alloying can prevent a CoFe layer from depositing as a polycrystalline layer. The B-alloyed layer also exhibits lower roughness.

It has been found that the same concept may be applied to the molybdenum deposition by using an alloyed molybdenum target. By maintaining an amorphous phase in the molybdenum layer the overall roughness of the multi-layer stack improves and leads to better EUV reflectivity with less flare. Examples of such alloying materials are boron and carbon. Another possibility is to add a small amount of nitrogen to the sputter gas to disrupt the structure of the deposited molybdenum.

Another technique that has been found that can be employed to suppress grain growth in the molybdenum layer is to cool the substrate to low temperatures. This can be accomplished by pre-cooling the substrate prior to deposition and actively cooling the substrate during the deposition process using water or gas cooling.

By maintaining an amorphous phase in the molybdenum layer the overall roughness of the multi-layer stack is improved and leads to better EUV reflectivity with less flare. An example of such alloying is boron. Another possibility is to add a small amount of nitrogen to the sputter gas to disrupt the structure on the deposited molybdenum layer.

Another technique that can be employed to suppress grain growth in the molybdenum layer is to cool the substrate to low temperatures. This can be accomplished by pre-cooling the substrate prior to deposition and actively cooling the substrate during the deposition process.

The resulting method and system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing EUV mask blanks.

An advantage of this method is that it is substrate independent and so it can be used on a variety of substrates and qualities of substrates. It has the potential to make it possible to use glass substrates that have the required properties for EUV blanks but do not have atomically flat, smooth surfaces after polishing. This independence makes it possible to use different substrate suppliers and minimizes the impact of unexpected changes to the substrate preparation and polishing by the suppliers.

Embodiments of the invention provide an atomically flat, low defect, smooth surface for an EUV mask blank. However, embodiments of the invention could also be used to manufacture other types of blanks, such as for mirrors. Over a glass substrate, embodiments of the invention can be used to form an EUV mirror. Further, embodiments of the invention can be applied to other atomically flat, low defect, smooth surface structures used in UV, DUV, e-beam, visible, infrared, ion-beam, x-ray, and other types of semiconductor lithography. Embodiments of the invention can also be used in various size structures that can range from wafer-scale to device level and even to larger area displays and solar applications.

Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.

It has been discovered that an amorphous phase can be formed in the metallic layer 400 by cooling the ultra-low expansion substrate 202 during deposition of the multilayer stack 206. The cooling of the multi-layer stack 206 suppresses grain growth in the molybdenum layer. This grain growth is suppressed by precooling the ultra-low expansion substrate 202 and actively cooling the ultra-low expansion substrate 202 during the deposition process using water.

Referring now to FIG. 5, therein is shown an optical train 500 for a EUV lithography system. The optical train 500 has a plasma source 502 for creating the EUV light and collecting it in a collector 504. The collector 504 provides the light to a field facet mirror 508 which is part of an illuminator system 506 which further includes a pupil facet mirror 510. The illuminator system 506 provides the EUV light to a reticle 512 (which is the fully processed version of the mask blank 104 of FIG. 1), which reflects the EUV light through projection optics 514 and onto a wafer 516.

Referring now to FIG. 6, therein is shown a EUV lithography system 600. The EUV lithography system 600 includes a EUV light source area 602, a reticle stage 604 and a wafer stage 606 as adjuncts to the optical train 600. The reticle stage 604 supports the reticle 512 of FIG. 5, which is the fully processed version of the mask blank 104 of FIG. 1.

It has been found that the EUV mirror 508 and the EUV mask blank 104 permit the EUV lithography system 600 to overcome many of the hurdles facing the production of ultra-miniaturized integrated circuits on die and wafers.

While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (22)

What is claimed is:
1. An extreme ultraviolet blank comprising:
a substrate;
a multi-layer stack having an amorphous metallic layer over the substrate, the multi-layer stack reflective of extreme ultraviolet light;
a capping layer over the multi-layer stack; and
an absorber layer which absorbs extreme ultraviolet light, the absorber layer over the capping layer.
2. The blank as claimed in claim 1 wherein the amorphous metallic layer is an alloyed amorphous metallic layer.
3. The blank as claimed in claim 1 wherein the amorphous metallic layer is alloyed with boron, nitrogen, or carbon.
4. The blank as claimed in claim 1 wherein the amorphous metallic layer is amorphous molybdenum.
5. The blank as claimed in claim 1 wherein the amorphous metallic layer has a disrupted crystalline structure.
6. The blank as claimed in claim 1 wherein the amorphous metallic layer has suppressed grain growth.
7. The blank as claimed in claim 1 wherein the multi-layer stack forms an extreme ultraviolet mask blank.
8. The blank as claimed in claim 1 wherein the multi-layer stack forms an extreme ultraviolet mirror.
9. The blank as claimed in claim 1 wherein the substrate is an ultra-low thermal expansion material.
10. The blank as claimed in claim 1 wherein the substrate is a glass.
11. The blank as claimed in claim 1, wherein the multi-layer stack comprises alternating layers of molybdenum and silicon.
12. The blank as claimed in claim 11, further comprising an antireflective coating over the absorber layer.
13. The blank as claimed in claim 11, wherein the capping layer comprises ruthenium and the absorber layer comprises tantalum.
14. The blank as claimed in claim 13, wherein the amorphous metallic layer is an alloyed amorphous metallic layer.
15. The blank as claimed in claim 13, wherein the amorphous metallic layer is alloyed with boron, nitrogen, or carbon.
16. The blank as claimed in claim 15, wherein the amorphous metallic layer is amorphous molybdenum.
17. The blank as claimed in claim 13, wherein the amorphous metallic layer has a disrupted crystalline structure.
18. The blank as claimed in claim 13, wherein the amorphous metallic layer has suppressed grain growth.
19. The blank as claimed in claim 13, wherein the multi-layer stack forms an extreme ultraviolet mask blank.
20. The blank as claimed in claim 13, wherein the multi-layer stack forms an extreme ultraviolet mirror.
21. The blank as claimed in claim 13, wherein the substrate is an ultra-low thermal expansion material.
22. The blank as claimed in claim 13, wherein the substrate is a glass.
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US201361778351 true 2013-03-12 2013-03-12
US14139507 US9417515B2 (en) 2013-03-14 2013-12-23 Ultra-smooth layer ultraviolet lithography mirrors and blanks, and manufacturing and lithography systems therefor
US14139457 US9632411B2 (en) 2013-03-14 2013-12-23 Vapor deposition deposited photoresist, and manufacturing and lithography systems therefor
US14139415 US20140272684A1 (en) 2013-03-12 2013-12-23 Extreme ultraviolet lithography mask blank manufacturing system and method of operation therefor
US14139371 US9612521B2 (en) 2013-03-12 2013-12-23 Amorphous layer extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor
US14139307 US9354508B2 (en) 2013-03-12 2013-12-23 Planarized extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor

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CN 201480010492 CN105009255B (en) 2013-03-12 2014-03-12 Extreme ultraviolet lithography blank amorphous layer and a method for manufacturing the blank and the lithography system
PCT/US2014/025116 WO2014165298A1 (en) 2013-03-12 2014-03-12 Amorphous layer extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor
KR20157027662A KR20150130371A (en) 2013-03-12 2014-03-12 Amorphous layer extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor
JP2016501750A JP2016519329A (en) 2013-03-12 2014-03-12 Amorphous layer extreme ultraviolet lithography blank and manufacturing lithography system therefor
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160342096A1 (en) * 2013-12-22 2016-11-24 Applied Materials, Inc. Extreme ultraviolet lithography system having chuck assembly and method of manufacturing thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9632411B2 (en) 2013-03-14 2017-04-25 Applied Materials, Inc. Vapor deposition deposited photoresist, and manufacturing and lithography systems therefor
US9739913B2 (en) 2014-07-11 2017-08-22 Applied Materials, Inc. Extreme ultraviolet capping layer and method of manufacturing and lithography thereof
US9690016B2 (en) 2014-07-11 2017-06-27 Applied Materials, Inc. Extreme ultraviolet reflective element with amorphous layers and method of manufacturing thereof
US9581890B2 (en) 2014-07-11 2017-02-28 Applied Materials, Inc. Extreme ultraviolet reflective element with multilayer stack and method of manufacturing thereof

Citations (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995008840A1 (en) 1993-09-20 1995-03-30 The Government Of The United States, Represented By The Secretary Of The Navy Method of fabricating sub-half-micron trenches and holes
US5427671A (en) 1989-09-26 1995-06-27 Applied Vision Limited Ion vapor deposition apparatus and method
US5645646A (en) 1994-02-25 1997-07-08 Applied Materials, Inc. Susceptor for deposition apparatus
US6010916A (en) 1997-12-05 2000-01-04 Advanced Micro Devices, Inc. Method for improving semiconductor wafer processing
US6142641A (en) 1998-06-18 2000-11-07 Ultratech Stepper, Inc. Four-mirror extreme ultraviolet (EUV) lithography projection system
US6202318B1 (en) 1996-12-13 2001-03-20 Texas Instruments Incorporated System for processing wafers and cleaning wafer-handling implements
US6224638B1 (en) 1996-10-21 2001-05-01 Applied Materials, Inc. Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
US20010019803A1 (en) * 1999-12-06 2001-09-06 The Regents Of The University Of California Mitigation of substrate defects in reflective reticles using sequential coating and annealing
US20020015855A1 (en) 2000-06-16 2002-02-07 Talex Sajoto System and method for depositing high dielectric constant materials and compatible conductive materials
JP2002222764A (en) 2000-11-22 2002-08-09 Hoya Corp Substrate with multilayer film, reflection mask blank for exposure, reflection mask for exposure, method of manufacturing it and method of manufacturing semiconductor
US20030176079A1 (en) 2002-03-12 2003-09-18 Michael Sogard Periodic clamping method and apparatus to reduce thermal stress in a wafer
US6656643B2 (en) 2001-02-20 2003-12-02 Chartered Semiconductor Manufacturing Ltd. Method of extreme ultraviolet mask engineering
US20040009410A1 (en) 2002-07-15 2004-01-15 International Business Machines Corporation Integrated cooling substrate for extreme ultraviolet reticle
US20040029041A1 (en) 2002-02-27 2004-02-12 Brewer Science, Inc. Novel planarization method for multi-layer lithography processing
US20040091618A1 (en) 2002-11-08 2004-05-13 Park Han-Su Photoresist depositon apparatus and method for forming photoresist film using the same
US20040151988A1 (en) 2003-02-05 2004-08-05 Silverman Peter J. EUV mask blank defect mitigation
US6780496B2 (en) 2001-07-03 2004-08-24 Euv Llc Optimized capping layers for EUV multilayers
US20050009175A1 (en) 1999-03-03 2005-01-13 Symyx Technologies, Inc. Chemical processing microsystems comprising high-temperature parallel flow microreactors
US20050008864A1 (en) 2003-05-21 2005-01-13 Asml Netherlands B.V. Method for coating a substrate for euv lithography and substrate with photoresist layer
US20050064298A1 (en) 2003-09-18 2005-03-24 Silverman Peter J. Multilayer coatings for EUV mask substrates
US20050084773A1 (en) 2002-04-12 2005-04-21 Krauth Anthony C. Use of a planarizing layer to improve multilayer performance in extreme ultraviolet masks
US20050085042A1 (en) 2003-06-23 2005-04-21 Jong-Sik Chun Dual gate oxide structure in semiconductor device and method thereof
US20050199830A1 (en) 2004-03-10 2005-09-15 Bowering Norbert R. EUV light source optical elements
US20050266317A1 (en) 2004-05-25 2005-12-01 International Business Machines Corporation Light scattering euvl mask
US7001788B2 (en) 2003-05-29 2006-02-21 Applied Materials, Inc. Maskless fabrication of waveguide mirrors
US7005227B2 (en) 2004-01-21 2006-02-28 Intel Corporation One component EUV photoresist
US20060166108A1 (en) 2005-01-27 2006-07-27 Applied Materials, Inc. Method for etching a molybdenum layer suitable for photomask fabrication
US20060245057A1 (en) 2005-04-27 2006-11-02 Asml Netherlands B.V. Spectral purity filter for multi-layer mirror, lithographic apparatus including such multi-layer mirror, method for enlarging the ratio of desired radiation and undesired radiation, and device manufacturing method
US20060275547A1 (en) 2005-06-01 2006-12-07 Lee Chung J Vapor Phase Deposition System and Method
US20070020903A1 (en) 2005-07-19 2007-01-25 Applied Materials, Inc. Hybrid PVD-CVD system
US7186630B2 (en) 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US20070099414A1 (en) 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20070141257A1 (en) 2004-03-31 2007-06-21 Tokyo Electron Limited Method and apparatus for forming metal silicate film, and method for manufacturing semiconductor device
US20070187228A1 (en) 2000-09-12 2007-08-16 Hoya Corporation Manufacturing Method and Apparatus of Phase Shift Mask Blank
US7279252B2 (en) 2003-01-17 2007-10-09 Schott Ag Substrate for the micro-lithography and process of manufacturing thereof
US7282318B2 (en) 2003-11-19 2007-10-16 Hynix Semiconductor Inc. Photoresist composition for EUV and method for forming photoresist pattern using the same
US20070240453A1 (en) 2006-03-29 2007-10-18 Asahi Glass Company Limited Method for smoothing a surface of a glass substrate, and substrate for a reflective mask blank used in EUV lithography, obtainable by that method
US20080076252A1 (en) 2006-09-26 2008-03-27 Fujitsu Limited Resist composition, resist pattern forming process, and method for manufacturing semiconductor device
US20080123073A1 (en) 2006-11-27 2008-05-29 Nikon Corporation Optical element, exposure apparatus using the same, and device manufacturing method
US20090031953A1 (en) 2006-05-30 2009-02-05 Applied Materials, Inc. Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US20090091752A1 (en) 2007-10-04 2009-04-09 Renesas Technology Corp. Apparatus and a method for inspection of a mask blank, a method for manufacturing a reflective exposure mask, a method for reflective exposure, and a method for manufacturing semiconductor integrated circuits
US7541297B2 (en) 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US20090176367A1 (en) 2008-01-08 2009-07-09 Heidi Baks OPTIMIZED SiCN CAPPING LAYER
US20090278233A1 (en) 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20100133092A1 (en) 2007-09-07 2010-06-03 Canon Anelva Corporation Sputtering method and sputtering apparatus
US7736820B2 (en) 2006-05-05 2010-06-15 Asml Netherlands B.V. Anti-reflection coating for an EUV mask
US7867923B2 (en) 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US7892719B2 (en) 2006-11-03 2011-02-22 Intel Corporation Photonic crystal EUV photoresists
USRE42388E1 (en) 2001-03-29 2011-05-24 Scott Summers Air folder adjuster apparatus and method
US7960077B2 (en) 2006-01-12 2011-06-14 Asahi Glass Company, Limited Reflective-type mask blank for EUV lithography
US20110305978A1 (en) * 2008-03-31 2011-12-15 Hoya Corporation Photomask blank, photomask, and method of manufacturing photomask blank
US20120099065A1 (en) 2010-10-22 2012-04-26 Jang Yong-Kyu Liquid crystal display and manufacturing method of the same
US20120129083A1 (en) 2010-11-22 2012-05-24 Kabushiki Kaisha Toshiba Method for manufacturing reflective mask and apparatus for manufacturing reflective mask
US20120141923A1 (en) 2010-12-02 2012-06-07 Wim Yves Deweerd Protective Cap for Extreme Ultraviolet Lithography Masks
US20120145534A1 (en) 2010-12-14 2012-06-14 Asahi Glass Company, Limited Process for producing reflective mask blank for euv lithography and process for producing substrate with functional film for the mask blank
US20120147353A1 (en) 2010-12-14 2012-06-14 Asml Netherlands B.V. Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
US20130094009A1 (en) 2011-10-14 2013-04-18 Asml Netherlands B.V. Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
US8465903B2 (en) 2010-10-06 2013-06-18 Applied Materials, Inc. Radiation patternable CVD film
US20130157177A1 (en) * 2011-12-16 2013-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Euv mask and method for forming the same
US8524382B2 (en) 2011-03-14 2013-09-03 Fuji Electric Co., Ltd. Oxide substrate and manufacturing method therefor
US20140256129A1 (en) 2013-03-11 2014-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor film deposition apparatus and method with improved heater cooling efficiency

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2850580B2 (en) * 1991-07-16 1999-01-27 日本電気株式会社 The method of manufacturing thin film
JPH06112009A (en) * 1992-09-28 1994-04-22 Ulvac Japan Ltd High resistance film and manufacture thereof
JP3281173B2 (en) * 1993-03-15 2002-05-13 ワイケイケイ株式会社 High hardness thin film and manufacturing method thereof
US6673524B2 (en) * 2000-11-17 2004-01-06 Kouros Ghandehari Attenuating extreme ultraviolet (EUV) phase-shifting mask fabrication method
JP4009102B2 (en) * 2001-12-19 2007-11-14 独立行政法人科学技術振興機構 Amorphous iron silicide film and a manufacturing method thereof having semiconductor characteristics
US7026076B2 (en) * 2003-03-03 2006-04-11 Freescale Semiconductor, Inc. Method of patterning photoresist on a wafer using a reflective mask with a multi-layer ARC
JP3683261B2 (en) * 2003-03-03 2005-08-17 Hoya株式会社 How reflective mask blank and a preparation having a false defects, the reflective mask and a manufacturing method thereof having a pseudo defect, and manufacturing substrate for a reflective mask blank or the reflective mask having a pseudo defect
DE10317792A1 (en) * 2003-04-16 2004-11-11 Schott Glas Mask blank for use in the EUV lithography, and process for its preparation
JP4703354B2 (en) * 2005-10-14 2011-06-15 Hoya株式会社 Multilayer reflective film coated substrate, a manufacturing method thereof, a reflective mask blank and the reflective mask
WO2008084680A1 (en) * 2006-12-27 2008-07-17 Asahi Glass Company, Limited Reflective mask blanc for euv lithography
DE102008007387A1 (en) * 2007-02-05 2008-08-07 Carl Zeiss Smt Ag The reflective optical element for EUV lithography devices
DE102008042212A1 (en) * 2008-09-19 2010-04-01 Carl Zeiss Smt Ag The reflective optical element and method for its preparation
CN103026296B (en) * 2010-07-27 2014-12-10 旭硝子株式会社 Substrate provided with reflecting layer for EUV lithography, and reflective mask blank for EUV lithography

Patent Citations (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5427671A (en) 1989-09-26 1995-06-27 Applied Vision Limited Ion vapor deposition apparatus and method
WO1995008840A1 (en) 1993-09-20 1995-03-30 The Government Of The United States, Represented By The Secretary Of The Navy Method of fabricating sub-half-micron trenches and holes
US5645646A (en) 1994-02-25 1997-07-08 Applied Materials, Inc. Susceptor for deposition apparatus
US6224638B1 (en) 1996-10-21 2001-05-01 Applied Materials, Inc. Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
US6202318B1 (en) 1996-12-13 2001-03-20 Texas Instruments Incorporated System for processing wafers and cleaning wafer-handling implements
US6010916A (en) 1997-12-05 2000-01-04 Advanced Micro Devices, Inc. Method for improving semiconductor wafer processing
US6142641A (en) 1998-06-18 2000-11-07 Ultratech Stepper, Inc. Four-mirror extreme ultraviolet (EUV) lithography projection system
US20050009175A1 (en) 1999-03-03 2005-01-13 Symyx Technologies, Inc. Chemical processing microsystems comprising high-temperature parallel flow microreactors
US20010019803A1 (en) * 1999-12-06 2001-09-06 The Regents Of The University Of California Mitigation of substrate defects in reflective reticles using sequential coating and annealing
US20020015855A1 (en) 2000-06-16 2002-02-07 Talex Sajoto System and method for depositing high dielectric constant materials and compatible conductive materials
US20070187228A1 (en) 2000-09-12 2007-08-16 Hoya Corporation Manufacturing Method and Apparatus of Phase Shift Mask Blank
JP2002222764A (en) 2000-11-22 2002-08-09 Hoya Corp Substrate with multilayer film, reflection mask blank for exposure, reflection mask for exposure, method of manufacturing it and method of manufacturing semiconductor
US6656643B2 (en) 2001-02-20 2003-12-02 Chartered Semiconductor Manufacturing Ltd. Method of extreme ultraviolet mask engineering
USRE42388E1 (en) 2001-03-29 2011-05-24 Scott Summers Air folder adjuster apparatus and method
US6780496B2 (en) 2001-07-03 2004-08-24 Euv Llc Optimized capping layers for EUV multilayers
US20040029041A1 (en) 2002-02-27 2004-02-12 Brewer Science, Inc. Novel planarization method for multi-layer lithography processing
US20030176079A1 (en) 2002-03-12 2003-09-18 Michael Sogard Periodic clamping method and apparatus to reduce thermal stress in a wafer
US20050084773A1 (en) 2002-04-12 2005-04-21 Krauth Anthony C. Use of a planarizing layer to improve multilayer performance in extreme ultraviolet masks
US20040009410A1 (en) 2002-07-15 2004-01-15 International Business Machines Corporation Integrated cooling substrate for extreme ultraviolet reticle
US7186630B2 (en) 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US20070117359A1 (en) 2002-08-14 2007-05-24 Asm America, Inc. Deposition of amorphous silicon-containing films
US20040091618A1 (en) 2002-11-08 2004-05-13 Park Han-Su Photoresist depositon apparatus and method for forming photoresist film using the same
US7279252B2 (en) 2003-01-17 2007-10-09 Schott Ag Substrate for the micro-lithography and process of manufacturing thereof
US20040151988A1 (en) 2003-02-05 2004-08-05 Silverman Peter J. EUV mask blank defect mitigation
US20050008864A1 (en) 2003-05-21 2005-01-13 Asml Netherlands B.V. Method for coating a substrate for euv lithography and substrate with photoresist layer
US7001788B2 (en) 2003-05-29 2006-02-21 Applied Materials, Inc. Maskless fabrication of waveguide mirrors
US20050085042A1 (en) 2003-06-23 2005-04-21 Jong-Sik Chun Dual gate oxide structure in semiconductor device and method thereof
US20080113303A1 (en) 2003-09-18 2008-05-15 Intel Corporation Multilayer Coatings For EUV Mask Substrates
US20050064298A1 (en) 2003-09-18 2005-03-24 Silverman Peter J. Multilayer coatings for EUV mask substrates
US7282318B2 (en) 2003-11-19 2007-10-16 Hynix Semiconductor Inc. Photoresist composition for EUV and method for forming photoresist pattern using the same
US7005227B2 (en) 2004-01-21 2006-02-28 Intel Corporation One component EUV photoresist
US20050199830A1 (en) 2004-03-10 2005-09-15 Bowering Norbert R. EUV light source optical elements
US20070141257A1 (en) 2004-03-31 2007-06-21 Tokyo Electron Limited Method and apparatus for forming metal silicate film, and method for manufacturing semiconductor device
US20050266317A1 (en) 2004-05-25 2005-12-01 International Business Machines Corporation Light scattering euvl mask
US20060166108A1 (en) 2005-01-27 2006-07-27 Applied Materials, Inc. Method for etching a molybdenum layer suitable for photomask fabrication
US20060245057A1 (en) 2005-04-27 2006-11-02 Asml Netherlands B.V. Spectral purity filter for multi-layer mirror, lithographic apparatus including such multi-layer mirror, method for enlarging the ratio of desired radiation and undesired radiation, and device manufacturing method
US20060275547A1 (en) 2005-06-01 2006-12-07 Lee Chung J Vapor Phase Deposition System and Method
US20070020903A1 (en) 2005-07-19 2007-01-25 Applied Materials, Inc. Hybrid PVD-CVD system
US20070099414A1 (en) 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US7960077B2 (en) 2006-01-12 2011-06-14 Asahi Glass Company, Limited Reflective-type mask blank for EUV lithography
US20070240453A1 (en) 2006-03-29 2007-10-18 Asahi Glass Company Limited Method for smoothing a surface of a glass substrate, and substrate for a reflective mask blank used in EUV lithography, obtainable by that method
US7736820B2 (en) 2006-05-05 2010-06-15 Asml Netherlands B.V. Anti-reflection coating for an EUV mask
US20090031953A1 (en) 2006-05-30 2009-02-05 Applied Materials, Inc. Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US20080076252A1 (en) 2006-09-26 2008-03-27 Fujitsu Limited Resist composition, resist pattern forming process, and method for manufacturing semiconductor device
US7892719B2 (en) 2006-11-03 2011-02-22 Intel Corporation Photonic crystal EUV photoresists
US20080123073A1 (en) 2006-11-27 2008-05-29 Nikon Corporation Optical element, exposure apparatus using the same, and device manufacturing method
US20090278233A1 (en) 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20100133092A1 (en) 2007-09-07 2010-06-03 Canon Anelva Corporation Sputtering method and sputtering apparatus
US20090091752A1 (en) 2007-10-04 2009-04-09 Renesas Technology Corp. Apparatus and a method for inspection of a mask blank, a method for manufacturing a reflective exposure mask, a method for reflective exposure, and a method for manufacturing semiconductor integrated circuits
US7541297B2 (en) 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US7867923B2 (en) 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US20090176367A1 (en) 2008-01-08 2009-07-09 Heidi Baks OPTIMIZED SiCN CAPPING LAYER
US20110305978A1 (en) * 2008-03-31 2011-12-15 Hoya Corporation Photomask blank, photomask, and method of manufacturing photomask blank
US20110117726A1 (en) 2008-07-24 2011-05-19 Amberwave Systems Corporation Bonded intermediate substrate and method of making same
US8465903B2 (en) 2010-10-06 2013-06-18 Applied Materials, Inc. Radiation patternable CVD film
US8536068B2 (en) 2010-10-06 2013-09-17 Applied Materials, Inc. Atomic layer deposition of photoresist materials and hard mask precursors
US20120099065A1 (en) 2010-10-22 2012-04-26 Jang Yong-Kyu Liquid crystal display and manufacturing method of the same
US20120129083A1 (en) 2010-11-22 2012-05-24 Kabushiki Kaisha Toshiba Method for manufacturing reflective mask and apparatus for manufacturing reflective mask
US20120141923A1 (en) 2010-12-02 2012-06-07 Wim Yves Deweerd Protective Cap for Extreme Ultraviolet Lithography Masks
US20120145534A1 (en) 2010-12-14 2012-06-14 Asahi Glass Company, Limited Process for producing reflective mask blank for euv lithography and process for producing substrate with functional film for the mask blank
US8562794B2 (en) 2010-12-14 2013-10-22 Asahi Glass Company, Limited Process for producing reflective mask blank for EUV lithography and process for producing substrate with functional film for the mask blank
US20120147353A1 (en) 2010-12-14 2012-06-14 Asml Netherlands B.V. Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
US8524382B2 (en) 2011-03-14 2013-09-03 Fuji Electric Co., Ltd. Oxide substrate and manufacturing method therefor
US20130094009A1 (en) 2011-10-14 2013-04-18 Asml Netherlands B.V. Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
US20130157177A1 (en) * 2011-12-16 2013-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Euv mask and method for forming the same
US20140256129A1 (en) 2013-03-11 2014-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor film deposition apparatus and method with improved heater cooling efficiency

Non-Patent Citations (15)

* Cited by examiner, † Cited by third party
Title
Final Office Action in U.S. Appl. No. 14/139,415 dated Oct. 7, 2016, 31 pages.
Final Office Action in U.S. Appl. No. 14/139,457 dated Jul. 22, 2016, 16 pages.
International Search Report & Written Opinion for PCT App No. PCT/US2014/025116 dated Jul. 22, 2014.
International Search Report & Written Opinion for PCT App No. PCT/US2014/025124 dated Jul. 24, 2014.
International Search Report & Written Opinion for PCT App No. PCT/US2014/026844 dated Sep. 3, 2014.
International Search Report & Written Opinion for PCT App No. PCT/US2014/25110 dated Jul. 22, 2014.
International Search Report & Written Opinion for PCT App No. PCT/US2014/26826 dated Jul. 15, 2014.
PCT International Preliminary Report on Patentability in PCT/US2014/025110 dated Sep. 15, 2015, 10 pages.
PCT International Preliminary Report on Patentability in PCT/US2014/025116 dated Sep. 15, 2015, 9 pages.
PCT International Preliminary Report on Patentability in PCT/US2014/025124 dated Sep. 15, 2015, 8 pages.
PCT International Preliminary Report on Patentability in PCT/US2014/026826 dated Sep. 15, 2015, 7 pages.
U.S. Appl. No. 14/139,307, filed Dec. 23, 2013, Beasley et al.
U.S. Appl. No. 14/139,415, filed Dec. 23, 2013, Hofmann et al.
U.S. Appl. No. 14/139,457, filed Dec. 23, 2013, Michaelson et al.
U.S. Appl. No. 14/139,507, filed Dec. 23, 2013, Barman et al.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160342096A1 (en) * 2013-12-22 2016-11-24 Applied Materials, Inc. Extreme ultraviolet lithography system having chuck assembly and method of manufacturing thereof

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