TW200304688A - Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate - Google Patents

Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate Download PDF

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TW200304688A
TW200304688A TW092105525A TW92105525A TW200304688A TW 200304688 A TW200304688 A TW 200304688A TW 092105525 A TW092105525 A TW 092105525A TW 92105525 A TW92105525 A TW 92105525A TW 200304688 A TW200304688 A TW 200304688A
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layer
gate stack
gate
manufacturing
oxide layer
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TW092105525A
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TWI220554B (en
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Martin Popp
Andreas Wich-Glasen
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Description

200304688
相同閘極^ ΐ的；i半v體基材上製造多個高度相近且間隔 雖然本發明的方法原則上可以 路上，但在本說明書中係以岸用二 有種類的積體電 在這方面所碰到的問題來說記憶積體電路及 時，路時’尤其是在製造半導體積體記憶電路 :最少的光刻層及最少的㈣步驟製 點’以達到很好的定位精度(校準精度)及降；觸 記憶=:==;!;尺:#'此在半導體積體 聂之鬥&七^ 間頁汉置一個使兩個相鄰的閘極堆 ϋ敗：&雜，、區形成導電接觸的關鍵觸點類型。關鍵觸點的 子通常是由其他較不具關鍵性的觸點經蝕刻而成。 如何找到一種適當的CB通路接觸孔蝕刻（SAC蝕刻：Se 1 f 、gned Contact) 一直是科技界的一個中心議題。適當的cb 通路接J獨孔蝕刻需符合以下的要求： 不此引起位元線和字元線之間的短路（CB-GC短路），因此 餘刻時&應盡可能選擇在氮化矽層對面進行； 立y不此使通路接觸孔上半部的CD尺寸變大，因為只要這路 4分的CD尺寸變大一點點，就會經由校準不良的金屬化通路
200304688 五、發明說明（2) 使得發生CB-GC短路的風險大幅升高 到目前為止，業界都 方式來達到上述要求。第 刻至氮化矽蓋，第二階段 蝕刻時盡可能不使通路接 本發明要解決的一個 多晶石夕層及一個位於其上 化中，矽化金屬層會出現 觸孔蓋蝕刻時，當氮化物 被除去，因矽化金屬層過 CB-GC短路的出現。 是採用一種由兩個階 一個階段是盡可構成的餘刻 是、登：t:: 各向異性垂直蝕 疋選擇性的蝕刻至氮化矽蓋，且 觸孔KB的上半部輪廓變大。 f重要的問題是’在具有一個底部 的f化金屬層的閘極堆疊的侧壁氧 ，氧化的現象。在進行關鍵通路接 ，蝕透及位於其下方的側壁氧化物 氧化而產生的吊耳可能會導致 這個K具有本發明巾請專利範圍1之特徵的方法即可解決 可以降：^: 2 T 5優點是經由向上逐漸變小的氧化層厚度 以提高it二接觸孔韻刻時發生短路的風險，因此可 衣私的產$(例如提高卯賴製程的產量）。 作用向^將具有阻礙氧化物生長 側壁面肉 如 且的弟一層的兩個相對而立的露出的 ，在此步驟中，相鄰的閘極堆疊具有將閘極堆疊的 第6頁 200304688 五、發明說明（3) 第一層的露出的側劈而、危^ 7 化步驟中就可以使氧化；f =作用。這樣在隨後進行的氧 耳。 化層厗度向上逐漸變小，以避免形成吊 從屬於申請專南I f 造方法的進一以：；1的其他申請範圍均為本發明之製 文良及其他有利實施方式。 本發明的一種右：丨ΛΑ h 氧 過 化。乾式氧化的好處”=方式使用的氧化方式是乾式 原則上亦可使用濕式=:。曰生長差異效應比較明顯，不 在本發明的另外—链士 ^ _ 多晶矽層，第二層是一 一有利的貫施方式中，第一層是一個 層 個矽化金屬層，尤其是一個矽化鎢 的方式是由下：：：：：利的實施方式中，形成閘極堆疊 (第—層、第二層、第閘三極層;質材料上依序疊上三個堆疊層 氮化it發明的另外―種有利的實施方式中，第三層是一個 在本發明的另外_ 第二個氧化層的閘極堆#有利的實施方式中，在具有第-及 ]才隹囔之上另外形成一個氮化矽側壁空
第7頁 200304688
在本發明的另外 物是氮氣。 一種有利的實施方式中 所使用的注入 的說明 以下配合圖式_本發明的特徵及優點作進一步 圖式1 · 間隔相同閘極;疊顯Λ在法半= 的構件或是具有C:同作以 ::構的代表的構件表示係相同 圖式la的半導體基材（1)係以矽為材 層閘極介質材料⑸，例如閘極氧化物 1上有- 介質材料。圖式13未將半導體基材⑴内位閘極 ⑽’GS2，GS3)下方及/或位於閑極堆豐 之間的記憶電路的主動區繪出。 2，GS3 ) 在具有閘極介質材料（5)的半導體基材（1 )上 個多晶矽層（1 〇)、一個矽化鎢層（2 )、 :食上一 ⑽’然後利用-種已知的光j術：二;:：二層 (GSl ’GS2，GS3)。閘極堆疊的形狀為長方形，在1 之間為光蝕刻所蝕刻出的蝕刻溝槽，因此閘極堆疊^隹宜
200304688 五、發明說明（5) GS2 ’ GS3)各有兩個相對而立的露出的側壁面。 接下來進行的是兩個斜向注入步驟丨丨及丨2，其目的是將 ^有阻礙氧化物生長作用的氮離子注入矽化鎢層（2 〇 )的兩個 露出的側壁面。在進行這兩個斜向注入步驟丨丨及丨2時，相鄰 的閘極堆$具有遮敝多晶石夕層（1 〇 )的露出的側壁面及閘極堆 $(GS1，GS2，GS3)之間的溝槽底部的作用。 =圖式lb所示，接下來進行的是一個乾式氧化的步驟。 、及過乾式氧化步驟會在多晶矽層（丨〇)及矽化鎢層（2〇)的側壁 同厚度的氧化層。由於在前面的步驟中將具有阻 在多曰坊W長1用的氮氣注入矽化鎢層（2 〇 )的側壁面，因此 ί二：(2 °丄的側壁面上形成的氧化層(01)的厚度大於在 可以避i在矽==上形成的氧化層(02)的厚度。這樣就 夕化鎢層(20)的側壁面上形成氧化物吊耳。 如圖式lc所示，通堂合产4立 + (GW，GS2/會在接下來的步驟中為閘極堆疊 GS3)形成一個氮化矽側壁空間（40)。 出），閘果極接堆者疊進:; 半個通路接觸孔蝕刻步驟(未在圖式中繪 ^ ^ ^ ^ (02) ^ ^ ^ Λ ^ 保護。在閘極堆疊的 σ I厚的虱化矽層（40)的有效 的區域，由於氮化石夕；^(4η° :也就是通路接觸孔在其内變小 夕層(4〇)比較薄而氧化層(〇2)比較厚，因 200304688 五、發明說明（6) 此可以提供良好的電防護作用。 減少在矽化鎢層（2〇)的侧壁面上的氧化物生長的另外— 個好處是’由於矽化鎢的消耗量較少，因此薄膜電阻也會比 較小。 …、 ’、 種貫施方式來說明本發明的製造方法， 但是本發明的製造方法的座田# m — ^ , ffn - rv ^ ^ ,的應用乾圍絕非僅限於這種貫施方 式，而疋可以再進行許多改 良亚擴大至更廣泛的應用範圍。 前面提及的各個層的製造 類 中的一種，並非唯一的選擇Y 料僅為多種可能的材料種
200304688 圖式簡單說明 圖式la--c :顯示在半導體基材上製造多個高度相近且間隔 相同閘極堆疊的方法的示意圖。 元件符號說明： 1 半導體 基材 5 閘 極 介 質 材 料 10 多晶矽 層 20 矽 化 物 層 30 氮化矽 層 40 氮 化 矽 側 壁 空間 GS1 ，GS2 ，G S 3閘極堆疊 01 ，02 第- -個氧化物層， 第二 -個 氧 化 物 層
第11頁

Claims (1)

  1. 200304688 ^、、申清專利範圍 1 ·按照以下步驟在半導體基材（1)上製造多個高度相近且間 隔相同閘極堆疊（GS1，GS2，GS3)的方法·· 在半；體基材（1 )上設置一層閘極介質材料（5 ); ^在閘極介質材料（5)上由下往上至少依序設置第一層〇〇) 及第二層（20)，以形成閘極堆疊（GS1，GS2，GS3); --所以斜向注入方式（I1，12)將具有阻礙氧化物生長作用的 ί Ϊ注入閘極堆疊（GS1，GS2，GS3)的第二層（20)的兩個相 出的側壁面内，在此步驟中，相 :::r:r，’GS2’Gs3)的第-層⑽ ^(GSl ^S2，〇δ3).^(2〇ΓΛ^ 第二個氧化層（02)，且第一個氧化層（〇1)的严/面上★形成 氧化層（02)的厚度。 ，旱又大於第二個 2·如申請專利範圍第！項的製造方法， 氧化或濕式氧化。 八符徵為·採用乾式 3 ·如申請專利範圍第1或第2項的製造方 丨 疋一個石夕化鎮層。 / 隻屬層，尤其 4·如申請專利範圍第！ 第2、或第3項的製造方法 其特徵
    200304688
    為：在閘極介質材料（5)上由下往上依序設置第一層（1〇) 第二層（20)、以及第三層（30)，以形成閘極堆疊^， GS2 ， GS3)。 ’其特徵為：第三層 5 ·如申請專利範圍第4項的製造方法 (3 0 )係一氮化石夕層。 6 ·如前述申請專利範圍中任一項的劁；生 乃〜衣k方法，直牲供 在具有第一個氧化物層（01)及第二個4 W徵為： 丨固乳化物層ί η 9、λα 疊（G S1，G S 2，G S 3)外部形成一個氮化々 的閘極堆 虱化矽侧壁空間（4〇)。
TW092105525A 2002-03-28 2003-03-13 Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate TWI220554B (en)

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DE10214126A DE10214126A1 (de) 2002-03-28 2002-03-28 Herstellungsverfahren für eine Mehrzahl von ungefähr gleich hohen und gleich beabstandeten Gatestapeln auf einem Halbleitersubstrat

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US (1) US7129155B2 (zh)
DE (1) DE10214126A1 (zh)
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KR20160148795A (ko) * 2015-06-16 2016-12-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법

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US5278438A (en) * 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
US5691212A (en) * 1996-09-27 1997-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. MOS device structure and integration method
JPH10223900A (ja) * 1996-12-03 1998-08-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
EP0971414A1 (de) * 1998-06-15 2000-01-12 Siemens Aktiengesellschaft Grabenkondensator mit Isolationskragen und vergrabenen Kontakt und entsprechendes Herstellungsverfahren
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
KR100291512B1 (ko) * 1998-11-26 2001-11-05 박종섭 반도체 소자의 게이트 전극 형성방법
US6187657B1 (en) * 1999-03-24 2001-02-13 Advanced Micro Devices, Inc. Dual material gate MOSFET technique
US6426253B1 (en) * 2000-05-23 2002-07-30 Infineon Technologies A G Method of forming a vertically oriented device in an integrated circuit
DE10062494A1 (de) * 2000-12-15 2002-05-29 Infineon Technologies Ag Verfahren zur Herstellung von Abstandsoxidschichten
DE20104747U1 (de) * 2001-03-20 2002-05-02 Baedje K H Meteor Gummiwerke Spaltdichtungsanordnung

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US7129155B2 (en) 2006-10-31
TWI220554B (en) 2004-08-21

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