TWI220554B - Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate - Google Patents
Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate Download PDFInfo
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- TWI220554B TWI220554B TW092105525A TW92105525A TWI220554B TW I220554 B TWI220554 B TW I220554B TW 092105525 A TW092105525 A TW 092105525A TW 92105525 A TW92105525 A TW 92105525A TW I220554 B TWI220554 B TW I220554B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 title claims abstract description 12
- 238000000926 separation method Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000003989 dielectric material Substances 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 230000000694 effects Effects 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 230000000903 blocking effect Effects 0.000 claims abstract 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 239000002689 soil Substances 0.000 claims description 2
- 241001674048 Phthiraptera Species 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000009279 wet oxidation reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 35
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 229940125898 compound 5 Drugs 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Description
1220554 五、發明說明（1) 本發明係一種在半導體基材上製造多個高度相近且間隔 目同閘極堆疊的方法。 路雖然本發明的方法原則上可以應用在所有種類的積體電 在*但在本說明書中係以應用在矽科技的記憶積體電路及 沒方面所碰到的問題來說明本發明的方法。 時，製造積體電路時，尤其是在製造半導體積體記憶電路 以印二要製造各種不同種類的觸點。因此在製程上最好能夠 點；1光刻層及最少的蝕刻步驟製造出這些不同種類的觸 1達到很好的定位精度（校準精度）及降低成本的目的。 記愔！T閘極堆疊的間距為一關鍵尺寸，因此在半導體積| 疊之間的主動區把^ t間使兩個相鄰的閘極土 通路接觸$、s ^成v電接觸的關鍵觸點類型。關鍵觸點6 路接觸孔通常是由其他較不具關鍵性的觸點錢刻而成（ ：Sel 通路接，個中心議題。適當的c' ^ ^ ^fa1 ^ M ^(CB_GC ^ ^ ^ ―不在氮化矽層對面進行； 部分二尺T變大觸孔：半部的… k大一點點，就會經由校準不良的金屬化通路
liM 第5頁 五、發明說明（2) 使得發生CB-GC短路的風險大幅升高。 ^目餉為止，業界都是採用一種由兩個 方式來達到上述要求。第一 白奴構成的蝕亥1 刻至Λ化石々莫 ^ 卩自^又疋迪'可能各向異性垂直备 蝕列日;杳叮：’弟二階段是選擇性的姓刻至氮化石夕苔，且, 餘心姐可能不使通路接觸侧的上半部輪廊變大:且名 本發明要解決的一個最重要 多晶石夕層及一個位於主上=要的疋，在具有一個底部 化中，矽化全眉厗奋屮、目夕化金屬層的閘極堆疊的侧壁氧 觸孔蓋钱料，當氮化物蓋钱 ^進仃關鍵通路接 被除去’因矽化金屬層過氧 下方的側壁氧化物 CB-GC短路的出現，八氧化而產生的吊耳可能會導致 利用具有本發明申請專 這個問題。 胃寻扪祀圍1之特敛的方法即可解決 ^發明的的最大優點是經由向 在進行通路接觸孔敍刻時發生：厚 “製程的產量（例如提高DRAM製程的產量）險’因此 本發明的基本構想是以斜向方式將且古 作用的物質注入閘極堆疊的"：：個有阻礙氧化物生 在此步驟中，相鄰的問極堆叠具有將閑 1220554 五、發明說明（3) 第一層的露出的側壁面遮蔽 、二 化步驟中就可以使氧化； — 。廷樣在隨後進行的氧 耳。 9尽度向上逐漸變小，以避免形成吊 ^從屬於申請專利範圍丨的其他 k方法的進一步改良及其他有利實施明方&气圍均為本發明之製 本發明的一種有利的實 化。乾式氧化的好處是氧化 ：的氧化方式是乾式 原則上亦可使用濕式氧化s玍長差異效應比較明顯，不 在本發明的另外一插士 ^ 多晶矽層，第二層是一伽J利的實施方式中， 層，尤其是一個矽化鎢 層0 是一個矽化金屬 第一層是一個 在本發明的另外一籀右 個堆疊層 的方式是由下而上在閘質：：T方式中，形成閘極堆疊 (第-層、第二層、第三層；質材科上依序疊上三 氮化>5夕層 ;;發明的另外一種有利的實施方式中， 第三層是一個 1220554 五、發明說明（4) 間。 ，=發明的另外一種有利的實施方式巾，所使用的注入 物疋氮氣。 以下配合圖式對本發明的特徵及優點作進一步的說明。 圖式la--c :顯示在半導體基材上製造多個高度相近且 間隔相同閘極堆疊的方法的示意圖。 在圖式la--c中，以相同標號的代表的構件表示係相同 的構件或是具有相同作用的構件。 圖式la的半導體基材係以矽為材料製成，其上一 層閘極介質材料（5)，例如閘極氧化物即為一種ς : 介質材料。圖式la未將半導體基材⑴内位於問極二疊 (GS1 ’GS2，GS3)下方及/或位於閘極堆疊（GS1，gs2,gs 之間的記憶電路的主動區繪出。 在具有閘極介質材料（5)的半導體基材（1)上依 個多晶矽層（10)、一個矽化鎢層（20)、 ㈤卜然後利用-種已知的光兹刻技術丄層 (GS1 ’GS2，GS3)。閘極堆疊的形狀為長方形，在閘隹極-之間為光蝕刻所蝕刻出的蝕刻溝槽，因此閘極堆疊（GW，且
第8頁 1220554 五、發明說明（5) " ' ' ------- GS2，GS3)各有兩個相對而立的露出的側壁面。 接下來進行的是兩個斜向注入步驟η&12，纟目 i出：2 :化物5長作用的氮離子注入矽化鎢層(20)的兩個 的=?面。Ϊ進行這兩個斜向注入步驟11及K時，相鄰 4CGS1 ^Gsl) Λ；" (1〇) ^ ^ ^ ^ ^ ® ^ ^ ^ 且WS1，GS2，GS3)之間的溝槽底部的作用。 經過Hi:::會-個乾式氧化的步驟。 面上形成不同厚度的二)層⑽的側壁 =化物生長作用的氮氣注入石夕化鶴層(2。)的側辟Π: 在夕晶石夕層U。)的側壁面上形 “：：： 石夕化嫣層⑽的側壁面上形成的氧化層匕)=度大於在 可以避…化嫣層(2。)的側壁面上形成氧化樣就 (GS! ^ ^ t 4 Γ, „ „ # …GS3)形成_個氮切側壁”⑷）。“ 如果接著進行一個通路接觸孔 出），閘極堆疊的上半部、也就步驟（未在圖式中繪 區域，氧化層（02)受到相對而言較厚觸孔在其内變大的 保護。在閘極堆疊的下半 虱化矽層（40)的有效 的區域，…化二以變： 1220554 五、發明說明（6) 此可以提供良好的電防護作用 減）在矽化鎢層（2 0 )的侧壁面上的氧化物生長的另外一 個好處是’由於矽化鎢的消耗量較少，因此薄膜電阻也會比 較小。 曰雖然前面係以一種實施方式來說明本發明的製造方法， 但疋本發明的製造方法的應用範圍絕非僅限於這種實施方 Λ 而疋可以再進行許多改良並擴大至更廣泛的應用範圍。 前面提及的各個層的製造材料僅為多種可能 中的一種，並非唯一的選擇。 、材料種_ 第10頁 1220554 圖式簡單說明 圖式la--c :顯示在半導體基材上製造多個高度相近且間隔 相同閘極堆疊的方法的示意圖。 元件符號說明： 5閘極介質材料 2 0 矽化物層 40 氮化矽側壁空間 1 半導體基材 1 0多晶矽層 3 0 氮化矽層 GS1，GS2，GS3閘極堆疊 01，0 2第一個氧化物層，第二個氧化物層 %
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Claims (1)
122055敎……tI止誓換頁! 2105525 修正 六、申請專利範圍 1 · 一種按照以下步驟在半導體基材（1)上製造多個高度相 近且間隔相同閘極堆疊（GS1，GS2，GS3)的製造方法： --在半導體基材（1)上設置一層閘極介質材料（5); --在閘極介質材料（5 )上由下往上至少依序設置第一層 (10)及第二層（20)，以形成閘極堆疊（gsi，GS2，GS3); --以斜向注入方式（Π，12)將具有阻礙氧化物生長作用 的物質注入閘極堆疊（GSI，GS2，GS3)的第二層（20)的兩 個相對而立的露出的側壁面内，在此步驟中，相鄰的閘極 堆*具有將閘極堆疊（GSI，GS2，GS3)的第一層（1〇)的露 出的側壁面遮蔽住的作用； —經由氧化作用同時在閘極堆疊（GS1，GS2，GS3)的第— 層（10)的露出的側壁面上形成第一個氧化層（〇l)，以及 :ΐ ΠGS2，GS3)的第二層(20)的露出的側壁面 於弟二個氧化層（02)的厚度。 及尺 如申請專利範圍第1項的釗徉古土 . ^ 為··採用兹彳ϋ几斗、、 方法，其氧化作用的特徵 抹用乾式虱化或濕式氧化。 了试 •如申請專利範圍第1項的萝诰古、车甘 徵為··第一層（1 〇 )係一多曰= 资，/、閘極介質材料特 屣μ ,女' ±窃乂 阳夕層，第二層（20)係一矽仆厶 弯層，尤其疋一個矽化鶴層。 J你矽化金 .如申請專利範圍第μ的製造方法，直 特徵為··在 閘極 1220554 ····. +. …十 .:f 一 U -一於丨 & ’案^丨她咖__主月曰_修正__ 六、申請專利範圍 介質材料（5)上由下往上依序設置第一層（1〇)、第二層 (2〇)、以及第三層（30)，以形成閘極堆疊（GS1，GS2， GS3)。 5 ·如申請專利範圍第4項的製造方法，其特徵為：第三層 (3 0 )係一氮化矽層。 6 ·如前述申請專利範圍中第1項的製造方法，其特徵為： 在具有第一個氧化物層（01)及第二個氧化物層（02)的閘極 堆疊（GS1，GS2，GS3)外部形成一個氮化矽側壁空間 (40)。 7·如刖述申請專利範圍中第1項的製造方法，其特徵发· 注入物為氮氣。 為·
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Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10214126A DE10214126A1 (de) | 2002-03-28 | 2002-03-28 | Herstellungsverfahren für eine Mehrzahl von ungefähr gleich hohen und gleich beabstandeten Gatestapeln auf einem Halbleitersubstrat |
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| Publication Number | Publication Date |
|---|---|
| TW200304688A TW200304688A (en) | 2003-10-01 |
| TWI220554B true TWI220554B (en) | 2004-08-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW092105525A TWI220554B (en) | 2002-03-28 | 2003-03-13 | Method of manufacturing multiple gate stacks with similar height and same separation on a semiconductor substrate |
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|---|---|
| US (1) | US7129155B2 (zh) |
| DE (1) | DE10214126A1 (zh) |
| TW (1) | TWI220554B (zh) |
| WO (1) | WO2003083931A1 (zh) |
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| KR20160148795A (ko) * | 2015-06-16 | 2016-12-27 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
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| US5278438A (en) * | 1991-12-19 | 1994-01-11 | North American Philips Corporation | Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure |
| US5691212A (en) * | 1996-09-27 | 1997-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS device structure and integration method |
| JPH10223900A (ja) * | 1996-12-03 | 1998-08-21 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
| EP0971414A1 (de) * | 1998-06-15 | 2000-01-12 | Siemens Aktiengesellschaft | Grabenkondensator mit Isolationskragen und vergrabenen Kontakt und entsprechendes Herstellungsverfahren |
| US6143611A (en) * | 1998-07-30 | 2000-11-07 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming electronic components, and transistors |
| KR100291512B1 (ko) * | 1998-11-26 | 2001-11-05 | 박종섭 | 반도체 소자의 게이트 전극 형성방법 |
| US6187657B1 (en) * | 1999-03-24 | 2001-02-13 | Advanced Micro Devices, Inc. | Dual material gate MOSFET technique |
| US6426253B1 (en) * | 2000-05-23 | 2002-07-30 | Infineon Technologies A G | Method of forming a vertically oriented device in an integrated circuit |
| DE10062494A1 (de) * | 2000-12-15 | 2002-05-29 | Infineon Technologies Ag | Verfahren zur Herstellung von Abstandsoxidschichten |
| DE20104747U1 (de) * | 2001-03-20 | 2002-05-02 | Baedje K H Meteor Gummiwerke | Spaltdichtungsanordnung |
-
2002
- 2002-03-28 DE DE10214126A patent/DE10214126A1/de not_active Withdrawn
-
2003
- 2003-03-13 TW TW092105525A patent/TWI220554B/zh not_active IP Right Cessation
- 2003-03-18 WO PCT/EP2003/002832 patent/WO2003083931A1/de not_active Application Discontinuation
-
2004
- 2004-08-12 US US10/916,742 patent/US7129155B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20050026407A1 (en) | 2005-02-03 |
| US7129155B2 (en) | 2006-10-31 |
| TW200304688A (en) | 2003-10-01 |
| WO2003083931A1 (de) | 2003-10-09 |
| DE10214126A1 (de) | 2003-10-23 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |