TW565883B - Method for forming a semiconductor gate - Google Patents

Abstract

The invention provides a method for forming a semiconductor gate, by forming spacers to isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby preventing single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate. After a cap layer is formed on a conductive structure over the substrate, an HDP dielectric layer is formed exposing the cap layer. A top of the HDP dielectric layer is higher than a top of the first conductive layer. After removing the cap layer to form a recess between the HDP dielectric layer and on the conductive structure, spacers are formed on sidewalls of the recess. Afterwards, a conductive layer is formed and connected to the conductive structure.

Description

565883 V. Description of the invention (1) The invention relates to a method for forming a semiconductor element, and particularly to a method for forming a semiconductor gate. (Che currently has a wide-conductor manufacturing process that does not require chemical mechanical polishing process: POUShing, CMP for short) as a flattening ΪΠ has attracted attention due to its environmental protection and low cost advantages. This method of making a semiconductor gate is mainly using the top cover sound f formed on the gate to connect the ΛΑ ▲ layer (P Ηγ10, and cooperate with the base, 2 hlgh density plasma (HDP) Oxygen I ^ uses hydrogen fluoride (HF) to remove part of the high-density plasma oxide layer up to the top cap layer, and then uses the step of removing the top cap layer to remove the excess J = degree plasma oxide layer on the gate, and Obtain a high-density layer with a flat surface = ^ j. Moreover, after the size of the semiconductor device is miniaturized, the width of the gate line will become extremely narrow after the channel size is reduced. Forming a large-scale polycrystalline silicon layer as the upper I of the gate is used to increase the upper surface of the gate to ensure the process margin of the subsequent processes and reduce the resistance. ^ 5 'The method of forming a semiconductor gate described above is easy Because the interface between the high-density electrode layer and the gate has defects, there is a danger of penetrating the substrate when a larger area of the gate is subsequently formed, resulting in a single bit failure. Affect its reliability f el iabi 1 lty). Moreover, when the semiconductor device is developing toward miniaturization, f = 1 to increase the upper surface of the gate and reduce the size of the component. It is necessary to reduce the distance between the two gates by as much as possible, so it is easy to follow the lithography process. In the cause of misalignment (mis — caused by component failure,

Page 5 565883 V. Description of the invention (2) Reduce the gate coupling rati (gcr). Therefore, an object of the present invention is to provide a method for forming a semiconductor gate to prevent a single bit failure caused by an interface defect between a high-density dielectric layer and a polycrystalline silicon gate. Method Another object of the present invention is to provide a method for forming a semiconductor gate to prevent a reliability issue from occurring. Method Another object of the present invention is to provide a method for forming a semiconductor gate to increase the gate lightening ratio. Another object of the present invention is to provide a method for forming a semiconductor gate to expand the error margin (window) when the lithography process is performed on the gate. The semiconductor cover ^ includes forming a stacked structure including a-layer conductor layer and a-layer cap layer on the substrate. Then, a two-plasma dielectric layer is formed on the substrate and the cap layer is exposed, wherein the top of the high-density plasma dielectric is two layers above the top of the conductor layer. The top cap layer is subsequently removed. Because the top of the dielectric layer is higher than the top of the conductor layer, a recess is formed in the conductor layer after the top cap layer is removed. It was confirmed that the P-β was connected to the side wall of the depression to form oxygen so that another layer of the conductor layer covering the depression was deposited, and the conductor layer formed below the two electrodes was connected to form a semiconductor element. The invention is based on the conductor layer. The shame formed on the side wall of the depression to isolate the high-density electrical dielectric > j | said, the gate Ϊ: face: two: Ϊ due to the high-density dielectric polysilicon layer and the polycrystalline silicon gate Single bit failure caused by surface defects to prevent the occurrence of a single bit failure. Page 6 W2twl'.pl (j 565883

Rely on f's question. To increase the gate coupling rate. In addition, because the oxidized spacer formed on the side wall of the depression prevents the present invention from being able to expand the erroneous margin of the lithography process of the gate electrode ^: 'The county team is a transcript; the above and other ㈣, features " Point: more obvious :: The following is a detailed description of a preferred embodiment, and in conjunction with the attached drawings <, the details are explained as follows: The simple description of the mark: 100, 200: the base 102, 114, 114a, 114b, 202, 214, 214a, 214b: conductor layers 104, 204: cap layers 106, 206: high-density plasma dielectric layers I 0 8, 2 0 8 · · depressions II 0, 11 0 a, 21 0 · · oxide layer 11 2: Patterned photoresist layer 210a: Oxidation spacers First embodiment The present invention is a method for forming a semiconductor gate, mainly by using a buried oxide spacer to solve high-density electrical barriers. High density plasma (HDP) dielectric layer defects. The present invention can be widely used in various semiconductor processes including semiconductor gates, such as mask read-only memory (mask, flash memory (FLASH memory) ) Or buried bit line And other processes' and the following embodiment is a floating gate in flash memory

9562twf.ptd Page 7 565883 V. Description of the invention (4) (floating gate) formation method. 1A to 1E are cross-sectional views of a manufacturing process of a floating gate of a flash memory according to a first embodiment of the present invention. Please refer to FIG. 1A. A stacked structure including a conductive layer 102 and a cap layer 104 is formed on a substrate 100. The material of the conductive layer 102 is, for example, polysilicon, and a cap. The material of the layer 104 is, for example, silicon nitride (S "N4), and a tunneling oxide layer (not shown) is further included between the substrate 100 and the conductor layer 102. Then, a layer is formed on the substrate 100 Nanxuan's plasma dielectric layer 106 is exposed and the top cover layer is exposed. The top of the high-density plasma dielectric layer 106 is higher than the top of the conductor layer 102. The material is, for example, a high-density plasma oxide layer (HDP 〇). xide layer). To form a high-density dielectric layer 106, for example, first form a high layer on the substrate 100 to cover the entire capping layer 104, and then use hydrogen fluoride. The top cover layer 104 is exposed. Remove the middle: Figure, the top cover layer 104 (refer to Figure 1A) The second method, for example, uses the top of the hot-disk acid 102, so the top dielectric layer is removed. The top of 106 is higher than the conductor layer to form a depression 108. After the layer 104, it will be on the conductor layer 102. The shape 110 covers the depression 108, and forms an oxide layer on the substrate 100. "The intermediate oxide layer 110 is, for example, high-density plasma oxygen, and then 'please refer to the photoresist layer 112 and use the figure, A pattern is formed on the substrate 100 to expose the conductor layer. The oxide layer 11 is etched for the etching mask, and the oxide layer on the sidewall of the depression 1 08 is retained. 9562twf.pic | Page 8 »1 丁 丨565883

11 Oa 〇 Then, referring to the second paragraph, the patterned photoresist layer 112 is deposited on the substrate 100 to deposit another layer of conductor 114 #. AiiA captures the basket layer 114, covering the depression 108 and the oxide layer 110a. The conductor layer, the V 媸 layer, and the conductor layer 102 below it are connected to form a floating gate of the flash memory cell and achieve the effect of increasing the floating gate. The material of the conductor layer 114 is, for example, It is polycrystalline silicon. After that, please refer to FIG. 1E, and may further include defining a conductive layer 114 to form several parts. As shown in the figure, a part of the conductive layer U4a is connected to the conductive layer 102 below it to form a flash memory cell. The floating gate; and another, part of the conductor layer 11 4b can become another floating gate of the flash memory cell. In particular, after the development of semiconductor components toward miniaturization, in order to simultaneously increase the upper surface of the floating gate and reduce the size of the components, the distance between the two memories must be shortened as much as possible. Because the present invention has the protection of the oxide layer 丨 〇a, as shown in FIG. 1E, the mis-alignment window when defining the conductor layer 114 will be significantly larger than the conventional technology. The gate coupling ratio (GCR) of the floating gate formed by the present invention will also increase. Second Embodiment FIGS. 2A to 2E are cross-sectional views of a manufacturing process of a floating gate of a flash memory according to a second embodiment of the present invention. Referring to FIG. 2A, a stacked structure including a conductor layer 202 and a cap layer 204 is formed on a substrate 200. The conductor layer 202 is, for example, a polycrystalline silicon layer, and the cap layer 2 is a silicon nitride layer. A tunneling oxide layer (not shown) is further included between the substrate 2000 and the conductor layer 202. Then, Yu Ji

565883 Description of the invention (6) A high-density plasma dielectric layer 206 is formed on the bottom 200 and the top cover layer 204 is exposed. The top of the south-density plasma dielectric layer 206 is higher than the top of the conductor layer 202, and the material is, for example, From the group of silicon oxide. Then, referring to FIG. 2B, the top cover layer 204 (see FIG. 2A) is removed using, for example, hot phosphoric acid. Since the top of the high-density plasma dielectric layer 206 is higher than the top of the conductive layer 202, a recess 208 will be formed on the conductive layer 202 after the top cap layer 204 is removed. Subsequently, an oxide layer 210 covering the depression 208, which is a high-density plasma oxide layer, is formed on the substrate 200.

Subsequently, referring to FIG. 2C, an etchback process is performed on the oxide layer 21 to form an oxide gap wall 210a on the sidewall of the depression 208, and the conductor layer 202 is exposed. Next, referring to FIG. 2D, another conductor layer 214 is deposited on the substrate 200 to cover the depression 208 and the oxidized spacer 21a. The material of the conductor layer 214 is, for example, polycrystalline spar, and is used to communicate with The conductor layer 202 below it is successively formed into a floating gate of the flash memory cell, and has the following effects. The π property is the name, 'Please refer to the figure 2. You can also define the conductor layer 214 into a number of four blades, as shown in the figure. Part of the conductor layer 21 "is connected to the Zhao 2 :: Λ? flash below it. The floating gate of the memory cell; another-part of the conductor / Λ of a flash memory cell of the floating gate. Especially the upper surface of the pole shrinks I-ί After the development, the number of floating gates is increased at the same time. The coat surface and the purpose of reducing the size of the element, the gate conductor layer 214a and the 2Ub gate & distance 1 must be shortened to reduce the distance between the two oceanic gates as M Lu Kai, λ. β ', 10a protection' Therefore, the margin of right and wrong when defining the conductor layer 214

565883 V. Description of the invention (7) It will be significantly larger than the above mentioned by Xi. 1. The wall of the present invention is used to isolate high-level contacts, and the interface between them is lacking to prevent reliability. 2. When the present invention can be expanded, And the simultaneous increase of 'then increase' Although the present invention is to limit the scope and scope of the present invention, the scope of protection should be seen later. The invention uses a conductor-density plasma to avoid the problems caused by sinking. The invention has been defined because the oxygen pair is defined to increase the coupling of the floating gate electrode. Any well-known feature that can be made as an attached application includes the dielectric at the layer depression. Layers and singularity due to high density. Increase the gate rate of the gap wall gate. Better implementation of this technique. Xu changed the interface between the oxidized interstitial polycrystalline stone gate formed on the side wall of the patent scope, the outer plasma dielectric layer, and the single crystal bit of the polycrystalline stone gate. Part of the conductor layer, so the right and wrong surface of the lithography process and the reduction of the size of the component are disclosed as above, but it is not the user's without departing from the essence and finishing of the present invention. Therefore, the warranty of the present invention is defined as quasi.

Page 565883 Brief description of the drawings Figures 1A to 1E are cross-sectional views of the manufacturing process of the floating gate of the flash memory according to a first embodiment of the present invention; and Figures 2A to 2E FIG. Is a sectional view of a manufacturing process of a floating gate of a flash memory according to a second embodiment of the present invention.

9562twf.ptd Page 12

Claims (1)

565883 VI. Scope of Patent Application '------- 1 · A method for forming a semiconductor gate, including: · forming on a substrate containing a first-tw = 6 姐 sister · a conductor layer and a cap layer A high-density dielectric polymer layer is formed on the substrate to expose the top cap layer, wherein the top of the high-density plasma dielectric layer is higher than the top of the first conductor layer; remove The capping layer to form a depression on the first conductor layer; an oxide spacer on the sidewall of the depression; and depositing a second conductor layer on the substrate to cover the depression so that the second The conductor layer is connected to the first conductor layer. 2. The method for forming a semiconductor gate as described in item i of the scope of patent application, wherein the material of the first conductor layer and the second conductor layer includes polycrystalline stone 0 3 • As described in item 1 of the scope of patent application The method for forming a semiconductor gate, wherein the material of the capping layer includes silicon nitride. 4. The method of forming a semiconductor gate as described in item 3 of the scope of the patent application, wherein the step of removing the cap layer includes removal using hot phosphoric acid. 5. The method for forming a semiconductor gate as described in item 1 of the scope of patent application, wherein the material of the high-density plasma dielectric layer includes a high-density plasma oxide layer. 6. The method for forming a semiconductor gate according to item 5 of the scope of patent application, wherein the step of forming the high-density dielectric layer on the substrate includes: forming a high-density plasma dielectric on the substrate Layer 'covers the top cover 565883 VI. Patent application layer; and using hydrogen fluoride to remove part of the high-density plasma dielectric layer to expose the capping layer. 7. A method for forming a floating gate of a flash memory, comprising: forming a stacked structure including a first conductive layer and a capping layer on a substrate; exposing the first conductive layer of the capping layer into a stack; A depression; a floating stone in the material package of the floating body layer of the floating gate memory of the floating plasma dielectric layer of the memory, which is located in the depression, and remains. A density plasma dielectric layer, the top of the electrical layer is higher than the forming layer on the first conductor layer to cover the recess to expose the first conductor layer; and two conductor layers covering the layers are connected. The high-density two-conductor layer is formed on the formation of a flash substrate according to the item, and the material for forming the flash conductor layer as described in the item and the flash layer as described in the second item includes nitride on the substrate. A high layer is formed, in which the high-density plasma top is removed; the cap layer is removed to form an oxygen layer on the substrate to define the oxide layer, and a portion of the sidewall of the depression is exposed to the oxygen to deposit a first layer on the substrate. The second conductor layer and the first conductor 8. The method of applying the seventh gate of the patent scope, which includes the definition of the 0th pole after the base step. 9. The method of applying the seventh gate of the patent scope, where The first enclosing compound crystal $ eve. 10. The method of applying a seventh gate according to the patent application, wherein the top cover 9562twf.ptd Page 14 565883 11. The method for forming a floating gate of a flash memory as described in item 10 of the scope of the patent application, wherein the step of removing the capping layer includes removing using hot-disk acid. 1 2 The method for forming a floating gate of a flash memory as described in item 7 of the scope of the patent application, wherein the material of the high-density plasma dielectric layer includes a high-density plasma oxide layer. & 1 3. The method for forming a floating gate of a flash memory as described in item 2 of the patent application scope, wherein the step of forming the high-density plasma dielectric layer on the substrate includes: A high-density plasma dielectric layer is formed on the substrate to cover the capping layer; and a portion of the high-density plasma dielectric layer is removed using hydrogen fluoride to expose the capping layer. 1 4 · A method for forming a floating gate of a flash memory, comprising: forming a conductor structure on a substrate; forming a capping layer on the conductor structure; forming a high-density plasma dielectric on the substrate An electrical layer, exposing the capping layer, wherein the top of the high-density plasma dielectric layer is higher than the top of the conductor structure; removing the capping layer to form a depression in the conductor structure; at the depression An oxide wall is formed on the side wall; and a conductor layer is deposited on the substrate to cover the recess so that the conductor layer is connected to the conductor structure. 15 · Floating flash memory as described in item 14 of the scope of patent application 565883 ^ Application for a method of placing a gate electrode ′ wherein after the step of forming the high-density plasma dielectric layer on the substrate, the method further includes defining the conductor layer to form a plurality of floating gate electrodes. 16 · The method for forming a floating gate of a flash memory according to item 14 of the scope of the patent application, wherein the material of the conductor structure and the conductor layer includes polycrystalline silicon. 17 · The method for forming a floating gate of a flash memory as described in item 14 of the scope of the patent application, wherein the step of forming the inter-silicon oxide wall on the side wall of the depression includes ... on the substrate Forming an oxide layer; and carrying out money transfer and engraving on the oxide layer. 18 · The method for forming a floating gate of a flash memory as described in item 14 of the scope of patent application, wherein the material of the high-density plasma dielectric layer includes a high-throughput plasma oxide layer. 19. ^ t tf ^ ® ^ 14 ^ ^ ^ ^ ^ The method of placing the gate electrode, wherein the material of the capping layer, 0: | ^-% describes the formation of a flash δ memory body. Scope # 19 of the scope ^ # 本 啵 刀 红 制 田 为 / < The step of layering includes the method of using thermal phosphoric acid to set the gate, in which the predicate is removed. 9562twf.ptd