TWI296136B - Method for manufacturing nand flash memory - Google Patents

Description

I296Ufedoc/e IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a memory device, and more particularly to a method of fabricating an anti-gate type flash memory. [Prior Art] Flash memory components have the ability to store, read, erase, etc., and the stored data will not disappear after power-off.

Point, so it has become a non-volatile memory component widely used in personal computers and electronic devices. /, i 丨夬 3 丨 丨 丨 丨 丨 丨 丨 丨 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 11! The lower the voltage of the servo will be, and the depolarization of the memory, because the gate ratio is floating, this increases the value of the gate coupling. And, in the trend of the integrated circuit, the memory of the system is reduced, and the memory sample is reduced. As a result, the line width and the coupling ratio of the component must be reduced. The gate that will follow the falling gate and the control gate will be forced to increase. This is the portable electronic product gas = military memory used for the operating voltage required for 军f military memory. Please refer to Figure 1 for energy consumption requirements. US VI': local disadvantage. National patent us6897116 discloses a fast I296m wf.doc/e. Body 2 is set on the substrate 110, and the substrate n〇 is sequentially arranged for oxidation. Layer 111, floating dummy 13〇, insulating stack structure 115 disk control, pole 116. Using a floating secret m with a semiconductor spacer to increase between two, 116 The equivalent capacitance area. Therefore, the gate coupling ratio of the flash memory can be increased. 斤7 ί然^ The interval between the floating electrodes 130 in the above flash memory =, i, Γ谷易 because of etching Incomplete, or dropped in the gap of the conductor into a floating _ 13G short circuit, so that the entire flash memory can not work. θ or inter-type flash memory memory capacity of the second large anti-demand products. Can't be used in memory capacity as far as the NAND flash type commemoration? ί== will float the f handsome 'the tender capacitor between the U-system gate and the equivalent capacitance area' Set the gate: it should be formed by the method of lithography, so the smaller, the lower 'is easy to be exposed in the exposure. Therefore, how to make a high wafer rate It is an extremely important issue for the early manufacturing of the reed and the spear J. ^The flash memory of Bemitu will be the current content of the invention. The purpose of providing an embodiment according to the present invention is to provide I296UL.doc /e for a method of manufacturing a reverse-gate type flash memory, which can be used by itself The invention provides a floating gate. Another object of the present invention is to provide a method for manufacturing a reverse-gate type flash memory, which can save process steps, shorten the manufacturing process, and avoid short circuit of the memory. The problem.

The invention provides a method for manufacturing a reverse-gate type flash memory, which is provided, for example, by first providing a substrate, and sequentially forming a tunneling dielectric layer 2, a first conductor layer and a mask layer on the substrate. A plurality of isolation structures are then formed in the mask layer, the first conductor layer, the tunnel cladding, and the substrate. Next, the cover sound is removed such that the top surface of each isolation structure is higher than the top surface of the first conductor layer. The second conductor layer is then formed on the two sidewalls exposed by the four isolation structures. A gate dielectric layer and a third conductor layer are sequentially formed on the substrate. In the manufacturing method of the upper il and the inter-type flash memory, the second conductor layer is formed by, for example, forming a layer of the conductor material on the substrate, and then forming the self-aligning mask by the structure of the second layer. Curtain, at least remove the layer of conductor material on these isolation structures.

* "The method of manufacturing the method of removing the conductive material (4), for example, is the material-directed side method. In the step of the non-4-directional method, In the manufacturing method including removing part of the first-conductor layer 0 and the gate type flashing, the isolation layer is formed by forming a layer-patterned photoresist photoresist layer on the mask layer. , remove part of the mask layer, first, "曰H1_ and the substrate to form a plurality of trenches. Then remove the 〇3twf.doc/e ΙίΓ resist layer, the woven material fills the insulation (4) to form the partition (4) i In the method of manufacturing the gate-type flash memory, the dielectric material of the gate is, for example, oxidized oxide/Nitrogen oxide/Oxidized oxide. The second conductor: for example, doped polycrystalline stone. The material of the curtain layer is, for example, a manufacturing method of the formation body of the nitride nitride, and the manufacturing method of the tunnel dielectric layer and the gate type flash memory, and the isolation structure is used to align the screen The formation of a floating gate (the second conductor layer and the first guide) can save the -channel mask and shorten the manufacturing process. In contrast to the method for fabricating a gate type flash memory, a substrate is sequentially formed on the substrate to form a layer of the dielectric layer of the dielectric layer, and then the first layer of the conductor layer, the dielectric layer and the substrate layer and The third conductor layer forms a dielectric between the gates on the substrate, and the mask/structure is formed after the step of forming the teeth with the dielectric layer and the first conductor layer. That is, it is formed on the mask layer, the first conductor layer, and the through-screen. The material of the mask layer is, for example, nitride nitride. In the method of manufacturing the 閛-type flash memory, the method of removing each structure is, for example. In the method of manufacturing the above-described reverse and inter-type flash memory, the material of the inter-gate dielectric layer 1296 H/e is, for example, yttrium oxide/nitridation, for example, doped polysilicon. The material of the first conductor layer is formed by the method of forming the thermal oxidization f, for example, in the method of fabricating the thermal oxidization f, and the structure of the opposite layer of the dielectric layer is used to make the isolation structure Top t manufacturing method, remove part of the isolation but can save the gallbladder. So - come, It is also possible to use the free-to-close ratio of the gate area between the floating gate and the memory-free short-circuit, to improve the floating closed-end and control, and other purposes, features and advantages can be more obvious. Men, also listed, and in conjunction with the drawings, for a detailed description, such as [Embodiment] Memory #examples of the reverse and closed type fast flashing constant two 4 map. 凊 first refer to Figure 2A, this reverse and fast For example, the substrate 2 〇 0 is provided first, and the substrate 200 Depends with the dielectric layer 21 〇, the conductor layer 22 〇 and the mask layer 223. The bauxite & 〇〇 is, for example, the Shi Xi substrate. The material which is inserted through the dielectric layer 21〇, for example, the C-conducting H-type method is, for example, a thermal oxidation method or a chemical vapor deposition. The material of the body layer 220 is, for example, doped polycrystalline stone, and the method forms a layer by chemical vapor deposition. After the undoped polycrystalline stone layer is formed, it is formed by stepping into the step; or it may be formed by the on-site implantation of the dopant ~, the gas accumulation method. As for the material of the mask layer 223, the formation method is, for example, a chemical residual deposition method. 9

After 1296 UL, with continued reference to FIG. 2A, a portion of the mask layer 223, the conductor layer 220, the tunneling dielectric layer 210, and the substrate 200 are removed to form a plurality of trenches 225. The method for removing the film layers is, for example, forming a patterned photoresist layer (not shown) on the mask layer 223, and then using the patterned photoresist layer as a mask, using the reactive singularity The exposed mask layer 223, and the conductor layer 220 under it, the tunneling dielectric layer 21 and the substrate 200 are removed, and then the patterned photoresist layer is removed to form it. Then, referring to FIG. 2B, an insulating material is filled in the trench 225 to form the isolation structure 230. The isolation structure 23 is formed, for example, by forming a layer of insulating material on the substrate 200, such as yttrium oxide, which is formed by, for example, high-density plasma chemical vapor deposition. Of course, the insulating material that has just been deposited will cover the mask layer 223, so it is necessary to planarize the insulating material with the mask layer 223 as a termination layer to form a top planar isolation structure 230. The method of planarizing the insulating material is, for example, a chemical mechanical polishing method or an etching process. Then, the mask layer 223 is removed, and the conductor layer 22 is exposed, and the top surface of the isolation structure 230 is higher than the top surface of the conductor layer 22A. Among them, • In addition to the mask? 223 method is for example, an isotropic remnant method. Referring to FIG. 2C, a layer of conductive material layer 233 is formed on the substrate 200. The material of the conductive material layer 233 is, for example, doped polysilicon. The forming method is, for example, forming a layer of uncrystallized f layer by chemical vapor deposition. The ion implantation step is performed to form it; or the material layer 233 formed by chemical vapor deposition may cover the isolation structure 230 and the conduction layer 220, for example, in a manner of being implanted. After the genus, please refer to FIG. 2D, and the isolation structure 230 is used as a self-aligning cover 10 I296ii34^c/e curtain, and a part of the conductor material layer 233 is removed to form a conductor layer 235 on both sidewalls of the isolation structure 23 . The method for removing a portion of the conductive material layer 233 is, for example, an anisotropic etching such as reactive ion etching, and when performing the step of anisotropic etching, a part of the conductor layer may be removed as shown in FIG. 2D. 220. The conductor layer 235 and the conductor layer 220 together form the floating gate 240 of the flash memory. Next, #茶知, FIG. 2E, forming a inter-gate dielectric layer 25 on the substrate 2 (8) = the inter-gate dielectric layer 250 is, for example, a composite dielectric formed by stacking a hafnium oxide layer 251, a tantalum nitride layer and a hafnium oxide layer 255. The layer may also be a dielectric material such as yttrium oxide or tantalum nitride. A method of forming these dielectric materials such as ruthenium oxide and ruthenium nitride is, for example, a chemical vapor deposition method. Then, a conductor layer 261 is formed on the inter-gate dielectric layer 250. The material of the conductor layer = is, for example, doped (four), which is formed by, for example, chemical vapor deposition to form a layer of undoped (four) layers, and then formed into steps to form; or

It is formed by chemical vapor deposition. Thereafter, a layer of metal wafer layer 263 can be formed on the conductor layer 2Q. The material of the metal impurity layer 263, such as Wei tungsten, is formed by, for example, b-vapor deposition of metal Wei materials: followed by a tempering step to reduce the metal rate . The conductor layer 261 and the metal lithium layer 263 form the control gate 260 of the flash memory. As for the method of subsequently completing the anti-gate flash memory, such as forming the source doc/e 1296 and 1 in the above embodiment, the isolation structure 230 is used to remove a portion of the conductor material layer 233 and a portion of the conductor. Layer 220 forms a floating gate 240. In other words, the manufacturing method can produce a flash memory having a high gate coupling ratio without going through a complicated lithography process which is prone to stacking errors. Therefore, not only can the manufacturing process be shortened, but also the short circuit can be avoided, thereby improving the reliability of the memory.

Another method of manufacturing the reverse and closed type flash memory proposed by the present invention will be described below.

3A to 3C are views showing a method of manufacturing an anti- and inter-type flash memory according to another embodiment of the present invention. Referring first to FIG. 3A, the manufacturing method is, for example, first providing a substrate 3GG, and forming a tunneling dielectric layer 31, a conductor layer 32A, and a mask layer 323 on the substrate. Among them, the mask layer milk can be set according to the design of the component. The substrate is for example a silk sole. The material to be worn with the dielectric layer is, for example, an oxidative dream, and its formation method is, for example, a thermal oxidation method or a chemical vapor deposition method. The material of the conductor layer 32 () is, for example, a doped polycrystalline stone: the formation method is, for example, formation by a chemical vapor deposition method, after the layer is not formed, and then subjected to an ion implantation step to form it; or It is possible to use the branch of the hanging stalker to synthesize the chemical gas: L: = material, for example, a forming method, and continue to refer to FIG. 3A, removing part of the mask layer, the conductor layer 320, the tunneling dielectric layer 31Q and The substrate (10) is formed to form a plurality of carcasses. For example, the method of forming the film layer is formed on the mask layer milk (not shown), and then the photoresist layer is patterned. I296U4vf.doc/e Removal of the conductor layer 320 underneath the naked conductor, 323 M and the patterned photoresist layer to remove the patterned photoresist layer by reactive ion engraving 'Then the ancestral structure of the 祖 卢 而 ° 图 图 图 图 图 图 图 图 图 3 沟 沟 沟 沟 沟 沟 沟 沟 沟 沟 沟 沟The isolation structure 33 is formed by a method of forming a layer of insulating material, and the insulating material is, for example, oxygenated n', i, for example, a high-density plasma chemical vapor deposition method. =, 'The insulating material formed by the deposition will cover the mask layer 323, so the two cores: ί: ί: 2333 is: Ϊ layer, flattening the insulating material to form the top surface ^ ^, : structure 330. The method of planarizing the insulating material is, for example, a chemical machine, and then removing a portion of the isolation structure 33, such that the surface of each of the isolation structures 33 is lower than the top surface of the conductor layer 320, and the conductor sound is exposed 3: the partial isolation structure is removed The 33〇 method is, for example, “the curtain layer 323λ: the mask, the entrance (four), etc., the (10) service, such as the anti-hetero ion side process. It is to be noted that, in this embodiment, the conductor layer is fine for this. If the removed isolation structure 330 is on the eve of the night, the more exposed floating gate sidewalls will be added. ... The idle pole and the post-clear ___# 1 brethren;; further 仟 to improve the gate coupling ratio of the flash memory. However, the top surface of the isolation structure 330 should not be lower than the top of the dielectric layer 3 〇 导致 导致 基底 基底 与 与 与Abnormal through-holes between the layers 320. Of course, the higher the height of the conductor layer 320, the more the sidewalls that can be exposed are also 13 1296m, which is also related to the gate coupling ratio, and the height is determined by the design of the components. Next, referring to FIG. 3B, the mask layer 323 is removed, and the conductor layer 320 is exposed. The method of removing the mask layer 323 is, for example, an anisotropic etching method. After the opening, referring to FIG. 3C, a gate dielectric layer 340 is formed on the substrate 300. The gate dielectric layer 34 is, for example, a hafnium oxide layer 341. , a nitride dielectric layer _ and a composite dielectric layer formed by stacking yttria layer 345, or a dielectric material such as oxidized stone, gasification, etc. These dielectric materials such as oxidized dream, nitriding; The method is, for example, a chemical vapor deposition method. / Then, a conductor layer 351 is formed on the inter-gate dielectric layer 340. The material is, for example, doped sand, and the formation method thereof is, for example,

In 4 cases, it is only necessary to form a two-layer conductor material (the conductor layer is implanted by a hoarding method to form a layer of undoped polycrystalline stone, and then an ion is widely formed to form it, or a field implantable dopant can also be used. It is formed by chemical vapor deposition. After that, it can be further touched: it will not be described here. In the above embodiment, 14 I296li4f.d〇〇/e 320, conductor layer 351) has a manufacturing process. The floating (four) pole and the control can be formed, and the design can be shortened, and the side wall structure 33 of the exposed conductor layer 320 (the floating interpole) can be removed, and the -channel lithography process can be omitted. Also avoid this: come 'not only one generation (generati0_ #地有利. The grain is pushed to the bottom, in addition, the sidewall area of the conductor layer 320 (floating idler) can be used to increase the floating bungee and the control electrode 35G material area Thus, the gate-to-close ratio is increased, and the operation speed and efficiency of the dragon are further improved. Although the invention has been disclosed above by way of example, it is not intended to limit the invention, and any skilled person is not Within the spirit and scope of the present invention, the scope of protection of the present invention is defined by the scope of the appended claims. [Figure 1] FIG. 2A to FIG. 2E are cross-sectional views showing the manufacturing process of the anti-gate type flash CMOS according to an embodiment of the present invention. FIG. 3A to FIG. 3C are diagrams. Inverting gate type according to another embodiment of the present invention Cross-sectional view of the manufacturing process of flash memory. [Description of main component symbols] 110, 200, 300: substrate 111: gate oxide layer H5: insulating stack structure 15 doc/e 1296136, 116, 260, 350: control gate 130, 240 · Floating gates 210, 310 · Tunneling dielectric layers 220, 235, 261, 320, 351: Conductor layers 230, 330: isolation structure 25 255, 34 345: yttrium oxide layer 253, 343: nitrogen Plutonium layer 263, 353: metal telluride layer

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Claims (1)

1296 m X. Patent application scope: 1. A method for manufacturing a reverse-gate type flash memory, comprising: providing a substrate; sequentially forming a tunneling dielectric layer, a first conductor layer and a substrate on the substrate a mask layer; forming a plurality of isolation structures in the mask layer, the first conductor layer, the tunneling dielectric layer, and the substrate; removing the mask layer such that top surfaces of the isolation structures are higher than a top surface of the first conductor layer; a second conductor layer formed on the exposed sidewalls of the isolation structures; a gate dielectric layer formed on the substrate; and a first dielectric layer formed on the gate dielectric layer Three conductor layer. 2. The method of manufacturing the reverse-gate type flash memory according to claim 1, wherein the method of forming the second conductor layer comprises: forming a layer of a conductor material on the substrate; and isolating the layer The structure is self-aligning the mask, and at least the layer of the conductor material on the isolation structures is removed. 3. The method of fabricating an anti-gate type flash memory according to claim 2, wherein the method of removing the layer of the conductor material on the isolation structures comprises an anisotropic etching method. 4. The method of manufacturing a reverse-gate type flash memory according to claim 3, wherein the step of the anisotropic etching further comprises removing a portion of the first conductor layer. 5. The manufacturing method of the anti-gate type flash memory 17 1296· twf.doc/e according to claim 1, wherein the method of forming the mask layer on the mask layer comprises: a patterned c-resistive layer; a conductor layer, the via layer, a portion of the mask layer, the first removed the patterned light substrate' (10) into a plurality of trenches, and filled in the trenches Into the network" L 6. If you apply for special materials to form the isolation structure. The manufacturing method, the towel of the _ person ^ is the opposite of _ flash memory / oxidized stone eve. θ "The material of the electric layer includes the oxidized stone eve/nitrite eve 7. The manufacturing method as in the patent application scope, wherein the wearable dielectric anti-ancient and closed type flash memory & Including thermal oxidation. Manufacturing method, wherein the second conductor == gate type flash memory 9. The manufacturing method of the patented range includes doped polycrystal, wherein the mask < gate type flash memory is not: The material of the hood layer includes nitrite. And a method of manufacturing the anti-gate type flash memory according to claim 10, further comprising forming the tunneling dielectric layer and the first conductor After the step of the layer, a mask layer is formed. 12. The method of fabricating an anti-gate type flash memory according to claim 11, further comprising forming the mask layer, the first conductor layer, the tunneling dielectric layer, and the substrate These isolation structures. 13. The method of manufacturing the anti-gate type flash memory according to claim 12, further comprising removing the portion of the isolation structure by using the mask layer as a mask. 14. The method of manufacturing the anti-gate type flash memory according to claim 11, wherein the material of the mask layer comprises tantalum nitride. The method of manufacturing the anti-gate type flash memory according to claim 10, wherein the method of removing portions of the isolation structure comprises an anisotropic etching method. 16. The method of manufacturing the anti-gate type flash memory according to claim 10, wherein the material of the inter-gate dielectric layer comprises yttrium oxide / lanthanum nitride / yttrium oxide. 17. The method of fabricating an anti-gate type flash memory according to claim 10, wherein the method of forming the tunneling dielectric layer comprises a thermal oxidation method. 18. The method of manufacturing the anti-gate type flash memory according to claim 10, wherein the material of the first conductor layer comprises doped polycrystalline stone. 19