CN104143551A - Nonvolatile memory cell and manufacturing method thereof - Google Patents
Nonvolatile memory cell and manufacturing method thereof Download PDFInfo
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- CN104143551A CN104143551A CN201310164784.7A CN201310164784A CN104143551A CN 104143551 A CN104143551 A CN 104143551A CN 201310164784 A CN201310164784 A CN 201310164784A CN 104143551 A CN104143551 A CN 104143551A
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Abstract
The invention relates to a nonvolatile memory cell and a manufacturing method of the nonvolatile memory cell. The nonvolatile memory cell comprises a substrate, electric charge storage structures and a tunneling dielectric layer. An isolation structure is arranged in the substrate, active areas are defined, and the electric charge storage structures are arranged on the active areas respectively. The width of the bottom of each electric charge structure is equal to the width of the corresponding active area in essence, the first included angle between the side wall of each electric charge storage structure and the upper surface of the substrate is different from the second included angle between the side wall of each isolation structure and the upper surface of the substrate. The tunneling dielectric layer is arranged between the electric charge storage structures and the substrate, the lower surface of the tunneling dielectric layer is flat, and the upper surface of the tunneling dielectric layer is parallel to the upper surface of the substrate in essence.
Description
Technical field
The present invention relates to a kind of integrated circuit and manufacture method thereof, particularly relate to a kind of nonvolatile memory born of the same parents and manufacture method thereof.
Background technology
Nonvolatile memory allows data programing repeatedly, reads and erase operation, even after the power interruptions of memory body, can also preserve the data that are stored in wherein.Due to these advantages, nonvolatile memory has become widely used memory body in PC and electronic equipment.
Can programming and wipe (electrically programmable and erasable) nonvolatile memory technology by electricity of the application charge storing structure of knowing (charge storage structure), as electronics erasable programmable read-only memory (EEPROM) and fast flash memory bank (flash memory body), various modernization application have been used in.Fast flash memory bank is designed to have memory cell, and it can be programmed and read independently.General fast flash memory bank memory cell by charge storage in floating grid.The nonvolatile memory of another kind of similar general fast flash memory bank is to make charge-trapping structure (charge-trapping structure) with silicon nitride, to replace the conductor material of floating grid.When the charge-trapping memory cell of silicon nitride is programmed, electric charge is captured and can not moves through the charge-trapping structure of silicon nitride.When not continuing supply power supply, electric charge can remain in silicon nitride electric charge capture layer always, maintains its data mode, until memory cell is wiped free of.Because electric charge can not move through silicon nitride electric charge capture layer, so electric charge can be positioned at different charge-trapping places.In other words, in the fast-flash memory body member of charge-trapping structural type, in each memory cell, can store an information more than bit.
At present existing several different methods puts forward to make above-mentioned two kinds of nonvolatile memories, but because the irrigation canals and ditches drift angle of making isolation structure is easily out exposed in manufacture process or suffer etched destruction, make the thinner thickness of formed tunneling dielectric layer on irrigation canals and ditches drift angle, cause the problem in memory body reliability.Moreover, if the height that will reduce isolation structure by etch-back, to promote grid coupling ratio (GCR), must avoid the tunneling dielectric layer of irrigation canals and ditches drift angle top to suffer etched destruction and become thinner, therefore, its etch back process also must accurately be controlled, and its process margin is very little.
As can be seen here, above-mentioned existing nonvolatile memory born of the same parents and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is completed by development always, and common product and method do not have appropriate structure and method to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new nonvolatile memory born of the same parents and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defect that existing nonvolatile memory born of the same parents exist, and propose a kind of new nonvolatile memory born of the same parents, technical problem to be solved is to make it have high grid coupling ratio and reliability, is very suitable for practicality.
Another object of the present invention is to, overcome the defect of existing nonvolatile memory born of the same parents' manufacture method existence, and a kind of new nonvolatile memory born of the same parents' manufacture method is proposed, technical problem to be solved is to make its manufacture process have enough process margin, thereby is more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of nonvolatile memory born of the same parents that propose according to the present invention, comprise substrate, charge storing structure and tunneling dielectric layer.In substrate, there is isolation structure, define active region.Charge storing structure is positioned on active region.The bottom width of charge storing structure equals in fact the width of active region, and the first angle of the sidewall of charge storing structure and the upper surface of substrate is different from the second angle of the sidewall of isolation structure and the upper surface of substrate.Tunneling dielectric layer is between charge storing structure and substrate.The lower surface of tunneling dielectric layer is smooth, and the upper surface of tunneling dielectric layer is parallel with the upper surface of substrate in fact.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid nonvolatile memory born of the same parents, the material of wherein said charge storing structure is electric charge capture layer or conductor layer.
Aforesaid nonvolatile memory born of the same parents, wherein said the first angle is less than above-mentioned the second angle.
Aforesaid nonvolatile memory born of the same parents, the intermediate width of wherein said charge storing structure is identical in fact with its bottom width, or its difference is less than 10nm.
Aforesaid nonvolatile memory born of the same parents, the intermediate width of wherein said charge storing structure and its top width or identical in fact, or its difference is less than 10nm.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of nonvolatile memory born of the same parents' that propose according to the present invention manufacture method, is included in the cover curtain layer that forms a plurality of patternings in substrate.Sidewall at the cover curtain layer of patterning forms a plurality of clearance walls.Take the cover curtain layer of patterning and clearance wall as cover curtain, remove part substrate, to form a plurality of irrigation canals and ditches, wherein between two irrigation canals and ditches of arbitrary neighborhood, define active region.Form a plurality of isolation structures, isolation structure is in irrigation canals and ditches and extends upwardly between clearance wall.Remove cover curtain layer and the clearance wall of patterning, to form a plurality of openings between isolation structure and on active region.In each opening, form tunneling dielectric layer and charge storing structure.Wherein, the lower surface of tunneling dielectric layer is smooth and parallel with the upper surface of substrate in fact, the bottom width of charge storing structure equals in fact the width of corresponding active region, and the first angle of the sidewall of charge storing structure and the upper surface of substrate is different from the second angle of the sidewall of isolation structure and the upper surface of substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid nonvolatile memory born of the same parents' manufacture method, is also included between above-mentioned clearance wall and the cover curtain layer of above-mentioned patterning and forms a plurality of linings.And form tunneling dielectric layer and charge storing structure in each opening before, remove lining.
Aforesaid nonvolatile memory born of the same parents' manufacture method, wherein said lining is different from the material of above-mentioned clearance wall, and different from the material of above-mentioned patterning cover curtain layer.
Aforesaid nonvolatile memory born of the same parents' manufacture method, the step that wherein forms above-mentioned isolation structure is included in above-mentioned substrate and forms insulating barrier, and fills in above-mentioned irrigation canals and ditches, then, carries out flatening process, removes the insulating barrier on cover curtain layer.
Aforesaid nonvolatile memory born of the same parents' manufacture method, also comprises the above-mentioned insulating barrier on the above-mentioned irrigation canals and ditches of etch-back.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, nonvolatile memory born of the same parents of the present invention and manufacture method thereof at least have following advantages and beneficial effect:
Nonvolatile memory born of the same parents' of the present invention manufacture method, the step that removed insulating barrier before tunneling dielectric layer forms has very large process margin (process window).In addition, by the etch-back of isolation structure, can increase the coupling area between control gate and charge storing structure, promote grid coupling ratio.
Moreover charge storing structure of the present invention can have vertical sidewall, can avoid the problem of conductor string (conductor stringer), also can avoid forming hole below charge storing structure.
Nonvolatile memory born of the same parents of the present invention, it has high grid coupling ratio and reliability.
Nonvolatile memory born of the same parents' of the present invention manufacture method, its manufacture process has enough process margin.
In sum, the invention relates to a kind of nonvolatile memory born of the same parents and manufacture method thereof.This nonvolatile memory born of the same parents, comprise substrate, charge storing structure and tunneling dielectric layer.Wherein in substrate, there is isolation structure, define active region.Charge storing structure is positioned on active region.The bottom width of charge storing structure equals in fact the width of active region, and the first angle of the sidewall of charge storing structure and the upper surface of substrate is different from the second angle of the sidewall of isolation structure and the upper surface of substrate.Tunneling dielectric layer is between charge storing structure and substrate.The lower surface of tunneling dielectric layer is smooth, and the upper surface of tunneling dielectric layer is parallel with the upper surface of substrate in fact.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 I is the flow process section of a kind of nonvolatile memory born of the same parents' of illustrating of an one exemplary embodiment of the present invention manufacture method.
10: substrate 12: the cover curtain layer of patterning
14: ground floor 16: the second layer
18,18a, 18b: lining 20: spacer material layer
20a: clearance wall 22: irrigation canals and ditches
24: active region 26: insulating barrier
26a, 26b: isolation structure 28,29: opening
30: tunneling dielectric layer 32: charge storing structure
34: dielectric layer 36: control gate
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, nonvolatile memory born of the same parents and its embodiment of manufacture method, structure, method, step, feature and effect thereof to proposing according to the present invention, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, should be to reach technological means and the effect that predetermined object takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic being only to provide with reference to the use with explanation, is not used for the present invention to be limited.
Refer to shown in Figure 1A, in substrate 10, form the cover curtain layer 12 of patterning.Substrate 10 can be semiconductor base, in this way silicon or germanium silicide.Substrate 10 can be also on insulating barrier, to have silicon (SOI) substrate.The cover curtain layer 12 of aforementioned pattern can be monolayer material layer, double layer material layer or multilayer material layer.In an one exemplary embodiment, two material layer that the cover curtain layer 12 of aforementioned each patterning is comprised of ground floor 14 and the second layer 16 is formed.Ground floor is for example pad oxide, and the second layer is for example silicon nitride layer.Formation method can first sequentially form the first material layer and the second material layer, then via micro-shadow and etch process patterning the second material layer and the first material layer.
Then, shown in Figure 1A, in substrate 10, form lining 18, with cover curtain layer 12 and the substrate 10 of overlay pattern.Afterwards, on lining 18, form spacer material layer 20.The material of lining 18 is different from the material of patterning cover curtain layer 12.In an one exemplary embodiment, the material of lining 18 is different from the material of the second layer 16 of the cover curtain layer of patterning 12.The material of lining 18 is for example silica, boron-phosphorosilicate glass or polysilicon.The formation method of lining 18 is for example chemical vapour deposition technique or atomic layer deposition method, and thickness is for example 1nm to 20nm.The material of spacer material layer 20 is different from lining 18, and different from the insulating barrier 26 (Fig. 1 C) of follow-up formation.The material of spacer material layer 20 is for example silicon nitride, oxynitride or polysilicon.The formation method of spacer material layer 20 is for example chemical vapour deposition technique or atomic layer deposition method, and thickness is for example 1nm to 20nm.
Refer to shown in Figure 1B, anisotropic etching spacer material layer 20 and lining 18, with sidewall formation clearance wall 20a and the lining 18a of the cover curtain layer 12 at patterning.Then, cover curtain layer 12, lining 18a and the clearance wall 20a of patterning of take is cover curtain, removes part substrate 10, to form irrigation canals and ditches 22, wherein between two irrigation canals and ditches 22 of arbitrary neighborhood, defines active region 24.Afterwards, in substrate 10 and in irrigation canals and ditches 20, form insulating barrier 26.The material of insulating barrier 26 can be insulating material, for example, be silica or boron-phosphorosilicate glass, and the method for its formation is for example chemical vapour deposition technique.
Refer to shown in Fig. 1 C, carry out flatening process, remove the insulating barrier 26 on the cover curtain layer 12 of patterning.Flatening process can, with the cover curtain layer 12 of patterning as grinding stop layer, adopt chemical mechanical milling tech to implement.
Refer to shown in Fig. 1 D to Fig. 1 F, remove cover curtain layer 12, lining 18a and the clearance wall 20a of patterning.More particularly, in an one exemplary embodiment, refer to shown in Fig. 1 D, first remove the second layer 16 of the cover curtain layer 12 of patterning.Then, refer to shown in Fig. 1 E, remove the ground floor 14 of the cover curtain layer 12 of part lining 18a and patterning, leave residual lining 18b.Afterwards, refer to shown in Fig. 1 F, remove clearance wall 20a and residual lining 18a, between isolation structure (insulating barrier staying) 26a and form opening 28 on active region 24.
Refer to shown in Fig. 1 C and Fig. 1 D; when removing the second layer 16 of cover curtain layer 12 of patterning; because the material of the ground floor 14 of the cover curtain layer 12 of lining 18a and patterning is different from the material of the second layer 16 of the cover curtain layer 12 of patterning; therefore; the ground floor 14 of the cover curtain layer 12 of lining 18a and patterning can be protected insulating barrier 26, avoids insulating barrier 26 to suffer etched destruction.Similarly; refer to shown in Fig. 1 D and Fig. 1 E; when removing the ground floor 14 of cover curtain layer 12 of lining 18a and patterning; because the material of clearance wall 20a is different from the ground floor 14 of the cover curtain layer 12 of lining 18a and patterning; therefore, clearance wall 20a can protect insulating barrier 26, avoids insulating barrier 26 to suffer etched destruction; the upper surface of insulating barrier 26 can part be removed because there not being any protection, and the insulating barrier 26 staying is as isolation structure 26a.Moreover, refer to shown in Fig. 1 E and Fig. 1 F, in removing the process of clearance wall 20a, because the material of clearance wall 20a is different from insulating barrier 26, can select the etchant for clearance wall 20a/ insulating barrier 26 with high etching selectivity to carry out etch process, the sidewall that reduces isolation structure 26a is subject to etched destruction.Therefore, after removing clearance wall 20a, the upper surface of substrate 10 is smooth in fact, and the sidewall of isolation structure 26a does not have in fact depression.In addition,, in removing the process of clearance wall 20a, residual lining 18a also can protect substrate 10 and the isolation structure 26a at the drift angle place of irrigation canals and ditches 22, avoids being recessed to form.Residual lining 18a can remove after clearance wall 20a removes again, or is removed in the process that removes clearance wall 20a.
Refer to shown in Fig. 1 G, among the opening 28 between isolation structure (insulating barrier staying) 26a and on active region 24, form tunneling dielectric layer 30.The material of tunneling dielectric layer 30 is for example silica.The formation method of tunneling dielectric layer 30 can adopt thermal oxidation method or chemical vapour deposition technique.The thickness of tunneling dielectric layer 30 is for example 1nm to 10nm.Due to after removing clearance wall 20a, the upper surface of substrate 10 is still for smooth in fact, and therefore, the lower surface of formed tunneling dielectric layer 30 is also smooth in fact, and its upper surface is parallel with the upper surface of substrate 10 in fact.
Then, on tunneling dielectric layer 30, form charge storing structure 32.The material of charge storing structure 32 can be electric charge capture layer or conductor layer.Electric charge capture layer can be single layer structure or sandwich construction.The material of electric charge capture layer comprises silicon nitride.In one embodiment, the material of electric charge capture layer from bottom to top comprises the stacked structure of silica, silicon nitride and silica, the method forming is for example chemical vapour deposition technique or thermal oxidation method or hot nitriding, and thickness is respectively for example 1nm to 5nm, 1nm to 5nm and 1nm to 5nm.The material of conductor layer is for example doped polycrystalline silicon, and the method for formation is for example chemical vapour deposition technique, and thickness is for example 1nm to 100nm.Because the sidewall of isolation structure 26a does not have in fact depression, therefore, the charge storing structure 32 being formed among the opening 28 between isolation structure 26a is for example to have vertical sidewall, and in the middle of it, width W 2 is identical in fact with its top width W1, or its difference is less than 10nm; And the intermediate width W2 of charge storing structure 32 is identical in fact with its bottom width W3, or its difference is less than 10nm.In addition, the bottom width W3 of charge storing structure 32 equals in fact the width W 4 of corresponding active region 24.Because charge storing structure 32 has vertical sidewall, therefore can avoid the problem of conductor string (Conductor stringer), also can avoid forming hole below charge storing structure.
Afterwards, refer to shown in Fig. 1 H, can be according to the demand of actual gate coupling ratio (Gate coupling ratio, GCR), selectivity removes a part for the upper surface of isolation structure 26a again, forms opening 29.The apparent height of the isolation structure 26b staying reduces, and can be used to increases the control gate 36 of follow-up formation and the coupling area between charge storing structure 32, to promote GCR.The method of selective removal isolation structure 26a can adopt etch-back method.Etch-back method can be wet etching, for example, be as etchant with hydrofluoric acid solution.Because the opening 29 on isolation structure 26b is that different time forms with the irrigation canals and ditches 22 in substrate 10, and its sidewall has different gradients, therefore, the first angle α of the upper surface of the sidewall of the charge storing structure in opening 29 32 and substrate 10 is different from the second angle β of the sidewall of isolation structure 26a in irrigation canals and ditches 22 and the upper surface of substrate 10.The difference of the first angle α and the second angle β is for example 0 degree to 10 degree.
, consult shown in Fig. 1 I thereafter, in substrate 10 and opening 29 form dielectric layers 34 and control gates 36.The material of dielectric layer 34 is for example silica, and the method for formation is for example chemical vapour deposition technique or thermal oxidation method, and thickness is for example 1nm to 20nm.Control gate 36 is conductor layer, and it can be monolayer material or double layer material.In an one exemplary embodiment, control gate 36 is monolayer material, for example, be doped polycrystalline silicon, and the method for formation is for example chemical vapour deposition technique, and thickness is for example 10nm to 200nm.For example, because electric charge storage structure 32 has level and smooth sidewall (being vertical sidewall), therefore, dielectric layer 34 can conformally cover on the surface of electric charge storage structure 32, and control gate 36 can contact with dielectric layer 34 and opening 29 be filled up, do not have and cannot contact dielectric layer 34 and maybe cannot fill up the situation that opening 29 forms holes.
In sum, according to the nonvolatile memory born of the same parents' of the embodiment of the present invention manufacture method, the step that removed insulating barrier before tunneling dielectric layer forms has very large process margin (process window).In addition, by the etch-back of isolation structure, can increase the coupling area between control gate and charge storing structure, promote grid coupling ratio.Moreover, the width that equals in fact active region according to the bottom width of the nonvolatile memory born of the same parents' of the embodiment of the present invention charge storing structure, the first angle of the sidewall of charge storing structure and the upper surface of substrate is different from the second angle of the sidewall of isolation structure and the upper surface of substrate.Charge storing structure can have vertical sidewall, to avoid the problem of conductor string (conductor stringer), also can avoid forming hole below charge storing structure.The lower surface of nonvolatile memory born of the same parents' tunneling dielectric layer is smooth, and the upper surface of tunneling dielectric layer is parallel with the upper surface of substrate in fact, that is the even thickness of tunneling dielectric layer, so nonvolatile memory born of the same parents have high reliability.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. nonvolatile memory born of the same parents, is characterized in that it comprises:
Substrate, has isolation structure in this substrate, defines active region;
Charge storing structure, be positioned on this active region, wherein the bottom width of this charge storing structure equals in fact the width of this active region, and the first angle of the sidewall of this charge storing structure and the upper surface of this substrate is different from the second angle of the sidewall of this isolation structure and this upper surface of this substrate; And
Tunneling dielectric layer, between this charge storing structure and this substrate, wherein the lower surface of this tunneling dielectric layer is smooth, and the upper surface of this tunneling dielectric layer is parallel with this upper surface of this substrate.
2. nonvolatile memory born of the same parents according to claim 1, is characterized in that wherein the material of this charge storing structure is electric charge capture layer or conductor layer.
3. nonvolatile memory born of the same parents according to claim 1, is characterized in that wherein this first angle is less than this second angle.
4. nonvolatile memory born of the same parents according to claim 1, it is characterized in that wherein the intermediate width of this charge storing structure is identical with its bottom width, or its difference are less than 10nm.
5. nonvolatile memory born of the same parents according to claim 1, it is characterized in that wherein the intermediate width of this charge storing structure is identical with its top width, or its difference are less than 10nm.
6. nonvolatile memory born of the same parents' a manufacture method, is characterized in that it comprises the following steps:
In substrate, form the cover curtain layer of a plurality of patternings;
Sidewall at the cover curtain layer of those patternings forms a plurality of clearance walls;
Take the cover curtain layer of those patternings and those clearance walls is cover curtain, removes this substrate of part, to form a plurality of irrigation canals and ditches, wherein between two irrigation canals and ditches of arbitrary neighborhood, defines active region;
Form a plurality of isolation structures, those isolation structures are in those irrigation canals and ditches and extend upwardly between those clearance walls;
Remove cover curtain layer and those clearance walls of this patterning, to form a plurality of openings between those isolation structures and on those active regions; And
In each opening, form tunneling dielectric layer and charge storing structure, wherein, the lower surface of those tunneling dielectric layers is smooth and parallel with the upper surface of this substrate, the bottom width of those charge storing structures equals the width of those active regions of correspondence, and the first angle of the sidewall of those charge storing structures and this upper surface of this substrate is different from the second angle of the sidewall of this isolation structure and this upper surface of this substrate.
7. nonvolatile memory born of the same parents' according to claim 6 manufacture method, is characterized in that it also comprises:
Between those clearance walls and the cover curtain layer of those patternings, form a plurality of linings; And
Form this tunneling dielectric layer and this charge storing structure in each opening before, remove those linings.
8. nonvolatile memory born of the same parents' according to claim 7 manufacture method, is characterized in that wherein this lining is different from the material of those clearance walls, and different from the material of those patterning cover curtain layers.
9. nonvolatile memory born of the same parents' according to claim 6 manufacture method, is characterized in that the step that wherein forms those isolation structures comprises:
In this substrate, form an insulating barrier, and fill in those irrigation canals and ditches; And
Carry out flatening process, remove this insulating barrier on this cover curtain layer.
10. nonvolatile memory born of the same parents' according to claim 9 manufacture method, is characterized in that it also comprises this insulating barrier on these irrigation canals and ditches of etch-back.
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| TW200725817A (en) * | 2005-12-26 | 2007-07-01 | Powerchip Semiconductor Corp | Method of manufacturing non-volatile memory and floating gate layer |
| TWI296136B (en) * | 2006-04-28 | 2008-04-21 | Macronix Int Co Ltd | Method for manufacturing nand flash memory |
| CN101894804A (en) * | 2009-05-21 | 2010-11-24 | 海力士半导体有限公司 | Method of manufacturing nonvolatile memory device |
| TW201128768A (en) * | 2010-02-12 | 2011-08-16 | Macronix Int Co Ltd | Bit line structure, semiconductor device and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200725817A (en) * | 2005-12-26 | 2007-07-01 | Powerchip Semiconductor Corp | Method of manufacturing non-volatile memory and floating gate layer |
| TWI296136B (en) * | 2006-04-28 | 2008-04-21 | Macronix Int Co Ltd | Method for manufacturing nand flash memory |
| CN101894804A (en) * | 2009-05-21 | 2010-11-24 | 海力士半导体有限公司 | Method of manufacturing nonvolatile memory device |
| TW201128768A (en) * | 2010-02-12 | 2011-08-16 | Macronix Int Co Ltd | Bit line structure, semiconductor device and method of forming the same |
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