c/006 12744^,。 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件與其製造方法，且特 別是有關於一種非揮發性記憶體與其製造方法。 【先前技術】 在半導體應用元件中，非揮發性記憶體具有體積小、 存取速度快及耗電置低的優點，因此，近來被使用於數位 照相機(Digital Still Cameras)及記憶卡(Memory Card)等可 攜式掌上型終端器(Portable Handy Terminal)的大量儲存 (Mass Storage)元件中。 典型的非揮發性記憶體係以摻雜的多晶矽製作浮置閘 極(Floating Gate)與控制閘極(Control Gate)。當記憶體進行 程式化(Program)時，注入浮置閘極的電子會均勻分布於整 個多晶矽浮置閘極層之中。然而，當多晶矽浮置閘極層下 方的穿隧氧化層有缺陷存在時，就容易造成浮置閘極 (Floating Gate)所儲存的電荷流失(漏電流），影響元件的可 • 靠度。 為了解決這個問題，一種半導體_氧化物_氮化物_氧化 半導體(SONOS)的結構已被提出。S0N0S結構即使在 •牙隧氧化層具有漏電路徑的情形下仍可以維持良好的電荷 保存能力。 在一般SONOS記憶體的製程中，其主動區域(Active Region)之間通常都有隔離結構來作元件之間的隔離之 用。目w普遍利用的隔離結構是淺溝渠隔離結構(S11)。 le797twf.doc/006 A ”圖1所繪示為習知一種SONOS記憶體的剖面圖。請 蒼知圖1 ’此SONOS記憶體是由矽基底100、隔離結構 102、底氧化層104、氮化矽層106、頂氧化層1〇8、多晶 矽層no、金屬矽化物層112以及介電層114所構成。底 氧化層104是利用熱氧化製程來形成的。然而，在此熱氧 ， 化製私步驟中，氧氣容易穿透隔離結構102的溝渠填充絕 緣層並且與溝渠的内壁反應，因此導致溝渠填充絕緣層的 ‘ 體_彡脹。這獅體獅脹會在麟渠戟層相接的石夕基 • 底100上產生應力。如指標II6所指示的部位，施加在矽 基底10〇上的應力會導致例如為差排的晶格缺陷(Crystal Defect)，而造成漏電的問題。 另方面在Ά溝卩网離結構的形成過程中，在溝渠 絕緣結構的邊緣形成的凹陷會造成後續形成的底氧化層變 薄(Gate Oxide Thinning)的現象。如指標118所指示的部 位。當施以大電壓於此SONOS記憶體上時，例如施以大 於5V以上的電壓時，容易產生許多問題，例如漏電現象， • 以及造成不必要的基底電流，大大降低元件的可靠性 (Reliability)。 【發明内容】 • 有鑑於此，本發明的目的就是在提供一種非揮發性記 一 憶體的製造方法，以防止晶格缺陷以及底氧化層變^的現 象。 本發明的再一目的是提供一種非揮發性記憶體，以提 供良好的可靠性。 6 rtwf.doc/006 、，^發明提供一種非揮發性記憶體的製造方法。此方法 ^提供基底，紐於基底巾形減_渠。此些溝严、往 =:延:二接；’於基絲面及溝渠表面形成； 包層。於弟一介電層上形成一層電荷陷入層。於 層。於基底上形成一層第二介電層。之後，： ^-a層上形成-層導體層，此導體層往第二方 伸。其中第一方向與該第二方向交錯。 a底m、=二上述於基底中形成溝渠之步驟是先於 ίίΐϊΐ 層，再於墊層上形成—層罩幕層。圖案 m；^、此闕，以形絲露出基底的數個開口。移 一些溝渠。然後，移除此轉 於-實_中，上述第—介電層特質例如 矽，上述於基底表面及溝渠表面形 如是熱氧化法。 包層的方法例 於一實施例中，上述電荷陷入層之材質 L目電荷陷入層之方法例如=學 積法。 械弟一，丨电層的方法例如是化學氣相沈 是先===’ i述於溝渠内填入絕緣層之步驟例如 料層，再移除部分此絕緣材 “备出书何^入層。移除部分絕緣材料層之方法 7 12744¾¾ twf.doc/006 例如是化學機械研磨法。 於一貫施例中，上述在移除部分絕緣材料層之步驟 中，更包括使此絕緣材料層之表面低於電荷陷人層。此時 移除部分絕緣材料層之方法例如是回蝕刻法。c/006 12744^,. IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a non-volatile memory and a method of fabricating the same. [Prior Art] In semiconductor application components, non-volatile memory has the advantages of small size, fast access speed, and low power consumption. Therefore, it has recently been used in digital still cameras and memory cards. ) In the mass storage (Mass Storage) component of the Portable Handy Terminal. A typical non-volatile memory system uses a doped polysilicon to create a floating gate and a control gate. When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polysilicon floating gate layer. However, when the tunneling oxide layer under the polysilicon floating gate layer is defective, it is easy to cause the charge loss (leakage current) stored in the floating gate, which affects the reliability of the component. In order to solve this problem, a structure of a semiconductor_oxide-nitride-oxide semiconductor (SONOS) has been proposed. The S0N0S structure maintains good charge retention even in the case where the tunnel oxide layer has a leakage path. In the general SONOS memory process, there is usually an isolation structure between the active regions for isolation between components. The commonly used isolation structure is a shallow trench isolation structure (S11). Le797twf.doc/006 A ” Figure 1 is a cross-sectional view of a conventional SONOS memory. Please know that Figure 1 'This SONOS memory is made of germanium substrate 100, isolation structure 102, bottom oxide layer 104, nitride The ruthenium layer 106, the top oxide layer 〇8, the polysilicon layer no, the metal hydride layer 112, and the dielectric layer 114. The bottom oxide layer 104 is formed by a thermal oxidation process. However, here, the hot oxygen is formed. In the private step, oxygen easily penetrates the trench of the isolation structure 102 to fill the insulating layer and react with the inner wall of the trench, thereby causing the trench to fill the insulating layer's body _ swell. This lion body bulge will be connected in the lining of the lining Shi Xiji • Stress is generated on the bottom 100. As indicated by the index II6, the stress applied to the crucible base 10〇 causes a crystal defect such as a poor row, which causes a problem of electric leakage. During the formation of the gutter-net structure, the depression formed at the edge of the trench insulation structure may cause a subsequent formation of a thin oxide layer (Gate Oxide Thinning), as indicated by the index 118. Large voltage for this SONOS When the voltage is applied to the body, for example, when a voltage of more than 5 V is applied, many problems such as electric leakage, and unnecessary base current are caused, and the reliability of the element is greatly reduced. Accordingly, it is an object of the present invention to provide a method for fabricating a non-volatile memory to prevent lattice defects and underlying oxide layers. A further object of the present invention is to provide a non-volatile memory. To provide good reliability. 6 rtwf.doc/006,, ^ Invented to provide a non-volatile memory manufacturing method. This method provides a substrate, which is added to the base towel shape to reduce the channel. : extension: two connections; 'formed on the surface of the base wire and the trench; cladding. Form a layer of charge trapping layer on the dielectric layer of the younger brother. On the layer, a second dielectric layer is formed on the substrate. After that: ^ Forming a layer conductor layer on the -a layer, the conductor layer extending toward the second side, wherein the first direction is interlaced with the second direction. a bottom m, = 2 The step of forming a trench in the substrate is preceded by the ίίΐϊΐ layer, Re-mat Forming a layer-up mask layer. The pattern m; ^, the 阙, to expose a plurality of openings of the substrate by the wire. Move some of the trenches. Then, remove the turn-to-real _, the above-mentioned first-dielectric layer characteristics, for example矽, the surface of the substrate and the surface of the trench are shaped by thermal oxidation. The method of cladding is as an example. In the embodiment, the method of the material of the charge trapping layer is in the form of a charge trapping layer, for example, the method of learning and accumulation. The method of the electric layer is, for example, chemical vapor deposition, which is first described in the step of filling the insulating layer in the trench, for example, the material layer, and then removing part of the insulating material. Method for removing part of the insulating material layer 7 127443⁄43⁄4 twf.doc/006 For example, chemical mechanical grinding. In a consistent embodiment, the step of removing a portion of the insulating material layer further includes causing the surface of the insulating material layer to be lower than the charge trapping layer. The method of removing a portion of the insulating material layer at this time is, for example, an etch back method.
於-實施例中，上述導體層之材質為多晶石夕化金屬。 本發明的步驟流程所製造的非揮發性記憶體可避免因 為晶格缺陷而造成的接合漏電_。而且可以避免底氧化 層變薄的現象。而且，因為上述第—介電層在溝渠中的部 义具有襯賴魏，因此省略了製作襯層的步驟， 了 Mi告洁轺。 本發明再提出一種非揮發性記憶體。此非揮發性記憶 ，疋由基底、數舰緣層、電荷陷人層収油導體層所 f成。基底中具有數個溝渠，這些溝渠往第-方向延伸。 數個絕緣層填滿此些溝渠。電荷陷人層設置於此些絕緣層 =間的基底上以及此些絕緣層絲底之間。此些導體層往 弟二方向延伸。其中第—方向與第二方向交錯。In the embodiment, the material of the conductor layer is a polycrystalline stone. The non-volatile memory fabricated by the step flow of the present invention can avoid junction leakage caused by lattice defects. Moreover, the phenomenon that the bottom oxide layer is thinned can be avoided. Moreover, since the above-mentioned first dielectric layer has a lining in the trench, the step of fabricating the lining is omitted, and Mi is cleaned. The invention further proposes a non-volatile memory. This non-volatile memory is formed by the base, the several ship's edge layer, and the charge trapping layer. There are several trenches in the substrate that extend in the first direction. A number of insulating layers fill the trenches. The charge trapping layer is disposed on the substrate between the insulating layers and between the insulating layers. These conductor layers extend in the direction of the second. The first direction is interlaced with the second direction.
於-實施例中，上述電荷陷入層與基底之間更包括一 層第一介電層’此第-介電層的材質例如是氧切。 一介電層例如是穿隧介電層。 於貝知例中，上述電荷陷入層與導體層之間更句括 門-層’此第二介電層更包括位於導體層與絕緣層之 曰1 :此弟二介電層的材質例如是氧化⑪’此第二^ 如是阻擋介電層。 兒層例 於貝〜例中，上述此些絕緣層之表面低於電荷陷入 8 rtwf.doc/006 層 屬 糊叙她㈣多晶樹 1 ^ ^ H f，上述電荷陷人層之材質例如是氮化石夕。 ，在徭二二:Γί發性記憶體的電荷陷入層可以缓衝絕緣 =因其^體積膨脹而對基底施加的應力，以避 免口土底的晶格缺陷而產生漏電的問題。 錢為ϊίΓ把上述和其他目的、特徵和優點能更明顯 明如下。、舉較佳實施例，並配合所附圖式，作詳細說 【實施方式】 曰圖Α是本發明的一種非揮發性記憶體的上視圖，圖 2B疋沿圖2A的剖面線I _ I，之剖面圖。 、、、>f 2A與圖2B。本發明之非揮發性記憶體是由 土氏〇〇、，丨電層208、絕緣層212、電荷陷入層21〇 ^層214以及導體層216所構成。基底200例如是石夕基底。 土底如〇中具有數個溝渠206以及溝渠206之間的主動區 fnf ^ 2〇6 ° 21^ 二溝糸206。絕緣層212之材質例如是氧化矽。電荷陷入 層210設置於這些絕緣層212之間的基底2〇〇上以及=此 ^緣層212與基底2〇〇之間。電荷陷入層21〇之材質例如 是氮化矽。電荷陷入層21〇與基底200之間更包括二層^ 電層208。介電層的材質例如是氧化石夕，介電層： 例如是穿隧介電層。數個導體層216位於電荷陷入層2⑺ rtwf.doc/006 上並往方向X延伸。方向y與方向x交錯。此外，電荷陷 入層210與這些導體層216之間更設置有一層介電^ 214 °介電層214更設置於此些導體層214與絕^層^二 之間。介電層214的材質例如是氧化矽，介電層214θ例如 為阻擋介電層。導體層216之材質例如是多晶矽化金屬。 這些導體層216例如為此非揮發性記憶體的閘極。 圖2C繪示在另一實施例之非揮發性記憶體的剖面 ^在圖2C中，構件與圖2B中的構件相同者給予相同的 標號，並省略其說明。在此只針對不同點做說明。請參昭 2圖if ’絕緣層212之表面低於溝渠裏外的電荷陷又層、 ”本發明之非揮發性記憶體的電荷陷入層21〇可以緩 j層212在後績的熱製程因體積膨脹而對基底200施加 ^應力，㈣免造絲底的晶格缺陷喊生漏電的問 剖面i M至圖3E為本發明之非揮發性記憶體的製造流程 ，先’ 照® 3A，提供基底·，基底例如是 =。然後於基底2G〇上形成一層 g 墊層2〇2之材質例如是氧化石夕，墊層“3 如，法。罩幕層2〇4之材質例如是氮化:成 (LPC;)。4之形成方法例如是低壓化學氣相沈積法 接著’請參照圖3B，圖案化軍幕層204與塾層202， rtwf.doc/006 以形成暴露出基底200的數個開口（未繪示）。圖案化罩幕 層204與墊層202的方法例如是先於基底200上形成一層 圖案化光阻層（未繪示），再以此圖案化光阻層為罩幕，移 除部分罩幕層204與部分墊層202，然後移除此圖案化光 阻層。之後，以圖案化的罩幕層204為罩幕，對基底2〇〇 進行非等向性蝕刻製程以移除部分基底2〇〇,而於基底2〇〇 中形成數個溝渠206。此些溝渠206往y方向延伸。各溝 ‘ 206之間的基底200是做為此非揮發性記憶體的主動區 W 207 〇 - 然後，請參照圖3C，例如以麟酸為姓刻劑的濕式钱刻 製私來移除罩幕層204。之後例如以氫氟酸為姓刻劑的濕 式餘刻製程來移除墊層202。接著，例如以熱氧化法於基 底200表面及溝渠206表面形成一層共形的介電層2〇8。 介電層208的材質例如是氧化矽。之後，例如以化學氣相 沈積法於介電層208上形成一層共形的電荷陷入層。 黾荷陷入層210之材質例如是氮化石夕。值得注意的是，在 • 後續的熱氧化製程步驟中，氧氣容易穿透溝渠填充絕緣層 並且與溝渠的内壁反應，因此導致溝渠填充絕緣層的體積 膨脹，而在與溝渠填充層相接的基底2〇〇上產生應力，尤 '其是溝渠206底部的邊緣。施加在基底2〇〇上的應力會導 • 致例如為差排的晶格缺陷，而造成接合漏電。位於溝渠"2〇6 中的電荷儲存層210就是可以缓衝溝渠填充絕緣層:加於 基底200上的應力，以避免接合漏電的問題。 之後，於基底200上形成一層絕緣材料層（未繪示）。 11 1274偏 twf.doc/006 之材質例如是氧化石夕。於基底上形成絕緣 = 驟例如是高密度電漿_)化學氣相沈積法。 =^月多,¾圖3D，利用化學機械研磨法並以電荷陷入層 '、、、研磨終jL>f切除科此 ，柿^In an embodiment, the charge trapping layer and the substrate further comprise a first dielectric layer. The material of the first dielectric layer is, for example, oxygen cut. A dielectric layer is, for example, a tunneling dielectric layer. In the example of the invention, the gate layer-layer is further included between the charge trapping layer and the conductor layer. The second dielectric layer further includes a layer 1 between the conductor layer and the insulating layer: the material of the second dielectric layer is, for example, Oxidation 11' this second ^ is to block the dielectric layer. In the case of the shell layer, the surface of the above-mentioned insulating layer is lower than the charge trapping 8 rtwf.doc/006, and the layer of the above-mentioned charge trapping layer is, for example, nitrogen. Fossil eve. In the second 22: Γ 发 发 发 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆The above and other objects, features and advantages will be more apparent as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is a top view of a non-volatile memory of the present invention, and FIG. 2B is a cross-sectional line I _ I along FIG. 2A. , the section view. , , , > f 2A and Fig. 2B. The non-volatile memory of the present invention is composed of a ruthenium, a ruthenium layer 208, an insulating layer 212, a charge trapping layer 21, and a conductor layer 216. The substrate 200 is, for example, a stone base. The soil bottom has a plurality of ditches 206 and an active area fnf ^ 2〇6 ° 21^ between the ditches 206. The material of the insulating layer 212 is, for example, cerium oxide. The charge trapping layer 210 is disposed on the substrate 2 between the insulating layers 212 and between the edge layer 212 and the substrate 2A. The material of the charge trapping layer 21 is, for example, tantalum nitride. The charge trap layer 21A and the substrate 200 further include a second layer 208. The material of the dielectric layer is, for example, oxidized oxide, and the dielectric layer is, for example, a tunneling dielectric layer. A plurality of conductor layers 216 are located on the charge trapping layer 2 (7) rtwf.doc/006 and extend in the direction X. The direction y is interleaved with the direction x. In addition, a dielectric layer 214 is further disposed between the charge trapping layer 210 and the conductor layers 216, and is disposed between the conductor layers 214 and the second layer. The material of the dielectric layer 214 is, for example, tantalum oxide, and the dielectric layer 214θ is, for example, a barrier dielectric layer. The material of the conductor layer 216 is, for example, a polycrystalline metal. These conductor layers 216 are, for example, the gates of such non-volatile memory. Fig. 2C shows a cross section of a non-volatile memory in another embodiment. In Fig. 2C, the same members as those in Fig. 2B are given the same reference numerals, and the description thereof is omitted. Only the differences are explained here. Please refer to Figure 2 if the surface of the insulating layer 212 is lower than the charge trapping layer inside and outside the trench, "the charge trapping layer 21 of the non-volatile memory of the present invention can slow down the thermal process of the layer 212. The volume is expanded to apply stress to the substrate 200, and (4) the lattice defect of the wire-making bottom is called the leakage profile i M to FIG. 3E is the manufacturing process of the non-volatile memory of the present invention, first provided by 'Photo® 3A The substrate, for example, is =. Then, a material of the g-layer 2〇2 is formed on the substrate 2G〇, for example, oxidized stone, and the underlayer “3. The material of the mask layer 2〇4 is, for example, nitrided (LPC;). The formation method of 4 is, for example, low pressure chemical vapor deposition followed by 'please referring to FIG. 3B, patterning the military layer 204 and the tantalum layer 202, rtwf.doc/006 to form a plurality of openings (not shown) exposing the substrate 200. . The method of patterning the mask layer 204 and the pad layer 202 is, for example, forming a patterned photoresist layer (not shown) on the substrate 200, and then using the patterned photoresist layer as a mask to remove part of the mask layer. 204 and a portion of the pad layer 202, and then removing the patterned photoresist layer. Thereafter, with the patterned mask layer 204 as a mask, the substrate 2 is anisotropically etched to remove portions of the substrate 2, and a plurality of trenches 206 are formed in the substrate 2A. These trenches 206 extend in the y direction. The substrate 200 between each trench '206 is the active region W 207 做 for this non-volatile memory. Then, please refer to FIG. 3C, for example, the wet money engraving privately with the sulphuric acid as the surname Mask layer 204. The backing layer 202 is then removed, for example, by a wet engraving process using hydrofluoric acid as the surname. Next, a conformal dielectric layer 2〇8 is formed on the surface of the substrate 200 and the surface of the trench 206 by thermal oxidation, for example. The material of the dielectric layer 208 is, for example, ruthenium oxide. Thereafter, a conformal charge trapping layer is formed over the dielectric layer 208, for example by chemical vapor deposition. The material of the charge trapping layer 210 is, for example, nitrite. It is worth noting that in the subsequent thermal oxidation process step, oxygen easily penetrates the trench to fill the insulating layer and react with the inner wall of the trench, thereby causing the volume expansion of the trench filled insulating layer and the substrate in contact with the trench filling layer. The stress is generated on the ridge, which is the edge of the bottom of the trench 206. The stress applied to the substrate 2〇〇 causes, for example, a poor lattice lattice defect, causing junction leakage. The charge storage layer 210 located in the trench "2〇6 is a buffer-filled insulating layer: a stress applied to the substrate 200 to avoid the problem of junction leakage. Thereafter, a layer of insulating material (not shown) is formed on the substrate 200. 11 1274 The material of twf.doc/006 is, for example, oxidized stone. Forming insulation on the substrate = for example, high density plasma _) chemical vapor deposition. =^月多多,3⁄4图3D, using chemical mechanical polishing method and charging into the layer ',,, grinding final jL>f cut off this, persimmon ^
電荷陷入層210,並形成絕緣層212。 關暴U 接著’請參照圖3E，於基底200上形成一層介電声 二。介電層214之材質例如是氧切，於基底200上形^ 方法例如是以化學氣相沈積法以沈積一層高 /皿軋物（igh Temperature 0xide，HT〇)。然後，於介 層214上形成-層導體層216，此導體層2i6往方向X延 伸，而方向y與方向x交錯。導體層216之材質例如是多 晶石夕化金屬’導體層216之形成方法例如是先以低壓化學 ^相沈積法(LPCVD)於基底2〇〇上形成一層播雜 層，再以LPCVD於摻雜多晶社形成—層魏金屬層。 導體層216是做為此非揮發性記憶體之控制閑極與字元 、線。 圖4A與圖4B是本發明另一實施例之 的製造流程剖面圖。圖4A是接續圖3C所繪示㈣ 剖面圖。在圖4A與圖4B中，構件與圖3A〜圖咒中的 件相同者給予相同的標號，並省略其說明。 川上述移除部分絕緣材料層而形成絕緣層 之^.中，更可以使此絕緣材料層之表面低於電荷陷 入層210 ’以確保於主動區2〇7上的電荷陷入層2川完全 暴露在外。為了使此絕緣材料層之表面低於電荷陷入層 12 rtwf.doc/006 .可選擇_喊赃取航學频鄉絲 絕緣材料層。回㈣法例如是乾式似彳。_電荷陷;J 別(例如是氮切)與絕緣材料層(例如是氧切)之^ 擇性的不㈤’此乾絲祕以移除部分絕緣 此絕緣材料層之表面低於電荷陷入層21G，卻不 =:=二可以確保於主動區2〇7上的電荷二 王暴路在外’而且電荷陷入層別不會受到損害，The charge sinks into the layer 210 and forms an insulating layer 212. Turn off the storm U. Next, please refer to FIG. 3E to form a layer of dielectric acoustics on the substrate 200. The material of the dielectric layer 214 is, for example, oxygen-cut, and is formed on the substrate 200 by, for example, chemical vapor deposition to deposit a layer of high temperature 0xide (HT〇). Then, a layer conductor layer 216 is formed on the dielectric layer 214, and the conductor layer 2i6 extends in the direction X, and the direction y is staggered with the direction x. The material of the conductor layer 216 is, for example, a polycrystalline lithiated metal 'conductor layer 216. For example, a low-level chemical phase deposition (LPCVD) method is first formed on the substrate 2, and then a layer is formed by LPCVD. The heteropolyline forms a layer of Wei metal. Conductor layer 216 is used to control the idle poles and characters and lines of this non-volatile memory. 4A and 4B are cross-sectional views showing a manufacturing process of another embodiment of the present invention. Figure 4A is a cross-sectional view (4) taken along line 3C. In Figs. 4A and 4B, the same members as those in Fig. 3A to Fig. 3A are given the same reference numerals, and the description thereof will be omitted. In the above, a part of the insulating material layer is removed to form an insulating layer, and the surface of the insulating material layer can be made lower than the charge trapping layer 210' to ensure that the charge trapping layer 2 on the active region 2〇7 is completely exposed. outer. In order to make the surface of the insulating material layer lower than the charge trapping layer 12 rtwf.doc / 006. You can choose to sneak a sneaker. The back (four) method is, for example, dry like. _charge trapping; J (for example, nitrogen cutting) and insulating material layer (for example, oxygen cutting) of the optional (five) 'this dry silk secret to remove part of the insulating material layer surface lower than the charge trapping layer 21G, but not =:=2 can ensure that the charge on the active area 2〇7 is outside the road, and the charge trapping layer will not be damaged.
因此在各主動區207上的電荷陷人層21G可以具有比較平 均的電性。 接著、，請參照圖4B，利用上述的方法來依序形成介電 層214與導體層216，而形成緣示於圖4B的結構。由於回 =法不會傷害電荷陷入層21〇，因此繪示於圖4β的結構 具有比較平均的電性。Therefore, the charge trapping layer 21G on each active region 207 can have relatively uniform electrical properties. Next, referring to Fig. 4B, the dielectric layer 214 and the conductor layer 216 are sequentially formed by the above method, and the structure shown in Fig. 4B is formed. Since the back = method does not damage the charge trapping layer 21, the structure shown in Fig. 4β has a relatively average electrical property.
在本發明所提供之非揮發性記憶體的製造方法中，由 於在溝渠高中配置有電荷陷入層2職為溝渠高之概 層’可緩衝後續形成的絕緣層212對基底200施加的應力， 免口為基底200產生晶格缺陷而造成的接合漏電問 通而且，由於絕緣層212在形成過程中不會遭受破壞， 所以後績的製程不會發生底氧化層變薄的現象。 本發明的另一項特點是製造流程的簡化。介電層208 是做為本發明之非揮發性記憶體的穿隧介電層^襯層 (Lmer)。在本發明中，由於穿隧介電層與襯層在同丄步驟 中形成，因此簡化了製造流程而降低成本。 雖;、、;本發明已以較佳貫施例揭露如上，然其並非用以 13 rtwf.doc/006 限^本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之 摩巳圍當視後附之申請專利範圍所界定者為準。 又 【圖式簡單說明】 圖1、’、胃不習知的一種非揮發性記憶體的剖面圖。 視圖圖2A是本發明—實施例之—種非揮發性記憶體的上 回 疋/口圖2A的剖面線I _ I，之剖面圖。 ΐ 另:實施例之非揮發性記憶體的剖面圖。 団至圖3E為本發明一實施例的一種非 體的製造流程剖面圖。 &性^己十思 圖4A至圖4B為本發明另一實施 憶體的製造流程剖面圖。 種非揮發性記 【主要元件符號說明】 100 ·秒基底 102 :隔離結構 104 ·•底氧化層 106 :氮化石夕層 108 :頂氧化層 110 ·多晶秒層 112 ·金屬石夕化物層 114 ·介電層 116、118 :指標 200 ··基底 14 Π74观 202 :墊層 204 :罩幕層 206 :溝渠 207 :主動區 208、214 :介電層 210 :電荷陷入層 212 :絕緣層 216 :導體層 X、y :方向 I - I ’ ：剖面線In the method for manufacturing a non-volatile memory provided by the present invention, since the charge trapping layer 2 is disposed in the trench high, the layer of the trench height can buffer the stress applied to the substrate 200 by the subsequently formed insulating layer 212. The substrate 200 generates a lattice defect and causes a junction leakage problem. Moreover, since the insulating layer 212 is not damaged during the formation process, the post-production process does not cause a thinning of the underlying oxide layer. Another feature of the invention is the simplification of the manufacturing process. The dielectric layer 208 is a tunneling dielectric layer (Lmer) which is a non-volatile memory of the present invention. In the present invention, since the tunnel dielectric layer and the liner are formed in the same step, the manufacturing process is simplified and the cost is reduced. The present invention has been described above by way of a preferred embodiment, and is not intended to be limited to the scope of the present invention. When a few changes and refinements are made, the invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1,] A cross-sectional view of a non-volatile memory which is not known in the stomach. 2A is a cross-sectional view of a hatching line I _ I of FIG. 2A of the non-volatile memory of the present invention. ΐ Another: A cross-sectional view of the non-volatile memory of the examples. 3E is a cross-sectional view showing a manufacturing process of a non-body according to an embodiment of the present invention. & Sexuality Figure 4A to Figure 4B are cross-sectional views showing the manufacturing process of another embodiment of the present invention. Non-volatile notes [Main component symbol description] 100 · second substrate 102 : isolation structure 104 · bottom oxide layer 106 : nitride layer 108 : top oxide layer 110 · polycrystalline layer 112 · metal layer l 114 Dielectric layer 116, 118: index 200 · substrate 14 Π 74 view 202: pad 204: mask layer 206: trench 207: active region 208, 214: dielectric layer 210: charge trapping layer 212: insulating layer 216: Conductor layer X, y: direction I - I ' : hatching