1292939 17869twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種接觸窗與非揮發性記憶體的製造方法。 【先前技術】 在各種非揮發性記憶體產品中，具有可進行多次資料 之存入、讀取、抹除等動作，且存入之資料在斷電後也不 會消失之優點的可電抹除且可程式唯讀記憶體 (EEPROM)，已成為個人電腦和電子設備所廣泛採用的一 種記憶體元件。 在習知的EEPROM技術中，有採用電荷儲存層取代 傳統的多晶矽浮置閘極的設計，此電荷儲存層之材質例如 是氮化矽。這種氮化矽電荷儲存層上下通常各有一層氧化 石夕’而形成氧化石夕/氮化石夕/氧化石夕(〇xide-ni壮ide-oxide，簡 稱ΟΝΟ)複合層。此種元件通稱為矽/氧化石夕/氮化石夕/氧化 矽/石夕(SONOS)元件，具有分離閘極結構的s〇N〇s元件也 以經被揭露出來，如美國專利US5930631號案。 然而，上述具有分離閘極結構的S0N0S元件，由於 設置分離閘極結構需要較大的分離閘極區域而具有較大的 s己憶胞尺寸，因此其記憶胞尺寸較具有堆疊閘極之可電抹 除且可程式唯讀記憶體之記憶胞尺寸大，而產生無法增加 元件集積度之問題。 曰 為了解決此問題，一種SONOS記憶體結構已經被發 展出來’其製造流程剖面圖繪示於圖1A至圖1D。 1292939 17869twf.doc/g 首先，請參照圖1A，提供基底100,並於基底100上 形成數個記憶胞102a。記憶胞102a自基底100而上依序 是複合層106a、閘極108a、頂蓋層110及頂蓋層112。然 後，於記憶胞102a的側壁上形成間隙壁114。129. The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a contact window and a non-volatile memory. [Prior Art] Among various non-volatile memory products, there is an electric power that can perform operations such as depositing, reading, erasing, etc. of multiple data, and the stored data does not disappear after power-off. Erasing and programmable read-only memory (EEPROM) has become a memory component widely used in personal computers and electronic devices. In the conventional EEPROM technology, there is a design in which a charge storage layer is used in place of a conventional polysilicon floating gate, and the material of the charge storage layer is, for example, tantalum nitride. The tantalum nitride charge storage layer usually has a layer of oxidized stone on the upper and lower sides to form a composite layer of oxidized stone/nitridite/oxidized ide-oxide (abbreviated ΟΝΟ-oxide). Such a component is commonly referred to as a bismuth/oxide oxide/nitridite/osmium oxide/SONOS element, and a s〇N〇s element having a separate gate structure is also disclosed, as in US Patent No. 5,930,631. . However, the above-mentioned S0N0S element having a separate gate structure has a larger separation gate region and a larger size of the memory cell, so that the memory cell size is more electric than that of the stacked gate. The memory cell size of the erased and programmable read-only memory is large, and there is a problem that the component accumulation cannot be increased.曰 In order to solve this problem, a SONOS memory structure has been developed. A cross-sectional view of the manufacturing process is shown in Figs. 1A to 1D. 1292939 17869twf.doc/g First, referring to FIG. 1A, a substrate 100 is provided, and a plurality of memory cells 102a are formed on the substrate 100. The memory cell 102a is sequentially from the substrate 100 to a composite layer 106a, a gate 108a, a cap layer 110, and a cap layer 112. Then, a spacer 114 is formed on the sidewall of the memory cell 102a.
接著’請參照圖1B，於記憶胞102a之間形成記憶胞 l〇2b。記憶胞102b自基底100與記憶胞l〇2a起依序為複 合層106b與閘極108b。記憶胞l〇2a係透過間隙壁114與 記憶胞102b相間隔。由於形成記憶胞i〇2b時，回钱刻製 程易於損傷頂蓋層11〇，而於標記115處產生頂蓋層ι1〇 的缺陷。 之後，請參照圖1C，以移除一個記憶胞1〇2b，以於 一對記憶胞102a之間形成一開口 ι16。接著，於開口 U6 底部的基底100中形成源極/汲極區118。繼之，於基底1〇〇 上形成一層共形的襯層120,以覆蓋記憶胞102a、1〇2b及 開口 116表面。然後於襯層12〇上形成一層介電層122。 介電層122填滿開口 116。其中，移除一個記憶胞獅的 步驟、其後的総去除過程與清洗製程也會損傷頂蓋層 110,因此使標記II5處的頂蓋層110的缺陷惡化。 隨後’請參照圖1D，依序移除開口 116上的介電層 122及襯層120 ’以形成接觸窗開口 124。然後，再於此接 觸窗開口 m中形成導電插塞126，以電性連接源臟極 區118。其中’移除開σ116上的介電層122及概層12〇 =步，、其相光阻去除過程與清洗製程會再擴大標記 115處的缺陷。Next, referring to Fig. 1B, a memory cell 〇2b is formed between the memory cells 102a. The memory cell 102b is sequentially a composite layer 106b and a gate 108b from the substrate 100 and the memory cell 110a. The memory cell 〇2a is spaced apart from the memory cell 102b through the spacer 114. When the memory cell i〇2b is formed, the return engraving process tends to damage the cap layer 11〇, and the defect of the cap layer ι1〇 is generated at the mark 115. Thereafter, referring to Fig. 1C, a memory cell 1〇2b is removed to form an opening ι16 between the pair of memory cells 102a. Next, a source/drain region 118 is formed in the substrate 100 at the bottom of the opening U6. Next, a conformal liner 120 is formed on the substrate 1 to cover the surfaces of the memory cells 102a, 1〇2b and the opening 116. A dielectric layer 122 is then formed over the liner 12A. Dielectric layer 122 fills opening 116. Among them, the step of removing one memory lion, the subsequent enamel removal process and the cleaning process may also damage the cap layer 110, thereby deteriorating the defects of the cap layer 110 at the mark II5. Subsequently, referring to FIG. 1D, the dielectric layer 122 and the liner 120' on the opening 116 are sequentially removed to form the contact opening 124. Then, a conductive plug 126 is formed in the contact window opening m to electrically connect the source dirty region 118. Wherein the removal of the dielectric layer 122 and the layer 12 〇 = step on the σ 116, the phase photoresist removal process and the cleaning process further enlarge the defect at the mark 115.
底 摻 1292939 17869twf.doc/g ^上述的缺陷在較嚴重的情況下，會造成部分記憶胞失 效。以圖1D所繪示的情形為例，由於頂蓋層11〇在標記 115$的缺陷過大，加上標記115附近的襯層12〇被移除， 使私圮115的缺陷外露，因此造成插塞126連接閘極 l〇8a，而造成短路。此情形會降低記憶體的良率。 【發明内容】 本發明的再一目的是提供一種接觸窗的製造方法，以 增加包括記憶體的半導體元件的良率。 本發明的目的ϋ是在提供—種非揮發性記憶體的製 造方法，以避免插塞連接多晶矽閘極。 本發明再提供-種_窗的製造方法，包括提供基 此基底上已形成至少二個堆疊閘極結構，這些堆疊問 極結構自基底而上至少包括第—介電層、導體肢至少一 了頁盖2這二個堆㈣極結構上_蓋層外側具有數個缺 二;=於堆疊閑極結構之側壁上形成數個間隙壁。間 Ϊ土真滿缺口。接著，於二_壁之間的基底上形成接觸 的較佳實施例所述之接觸窗的製造方 :氣化^例如是複合層’此複合層的材質例如 夕氧切堆疊層，的材質例如是 依據本發明的較佳實施 法，其中間隙壁之材質&之接觸_的製1^方 擇性。 /、、盍層之材質具有不同的蝕刻選 1292939 17869twfdoc/g 、依據本^發明的較佳實施例所述之接觸窗的製造方 法’其中至少1蓋層例如包括第一頂蓋層及覆蓋第一頂 蓋層的，二職層。此外，缺口位於第—頂蓋層。另外， 第頂蓋層之材質與第二頂蓋層之材質具有不同的餘刻選 擇〖生另方面，第一頂蓋層的材質例如是氧化矽，第二 頂蓋層的材質例如是氮化矽。The bottom is doped with 1292939 17869twf.doc/g ^ The above defects will cause some memory cells to fail in more severe cases. Taking the situation illustrated in FIG. 1D as an example, since the defect of the top cover layer 11 at the mark 115$ is too large, and the lining 12 附近 near the mark 115 is removed, the defect of the private raft 115 is exposed, thereby causing the insertion. The plug 126 connects the gate l 8a and causes a short circuit. This situation will reduce the yield of the memory. SUMMARY OF THE INVENTION It is still another object of the present invention to provide a method of manufacturing a contact window to increase the yield of a semiconductor element including a memory. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a non-volatile memory to avoid plugging a polysilicon gate. The invention further provides a method for manufacturing a window, comprising providing at least two stacked gate structures formed on the substrate, the stacked gate structures comprising at least a first dielectric layer and at least one conductor leg from the substrate The two cover (four) pole structures of the page cover 2 have a plurality of gaps on the outer side of the cover layer; = several spacers are formed on the side walls of the stacked idler structure. The soil is really full of gaps. Next, the manufacturing method of the contact window described in the preferred embodiment is formed by forming a contact on the substrate between the two walls: gasification is, for example, a composite layer, such as a material of the composite layer, such as a material of a stack of layers, for example, According to a preferred embodiment of the present invention, the material of the spacers & The material of the 盍 layer has different etching options 1292939 17869 twfdoc/g, and the manufacturing method of the contact window according to the preferred embodiment of the present invention, wherein at least one of the cap layers includes, for example, a first cap layer and a covering layer A capped layer, the second floor. In addition, the gap is located in the first cap layer. In addition, the material of the first cap layer and the material of the second cap layer have different residual options. In other aspects, the material of the first cap layer is, for example, yttrium oxide, and the material of the second cap layer is, for example, nitriding. Hey.
依據本發明的較佳實施例所述之接觸窗的製造方 形成方法包括於基底上形成第二介電層 刻製程’以移除第二介電層的一部分，直到二t= ，之間的基底。其中於形綱;前=== 二形;第：層。此外，第二介電層二= 化夕#二；|電層的材質例如是氧化石夕。 :二本，明的較佳實施例所述之接 迕 ===步驟包括於基底上形成共形二 介介電層上形成第五 的部分第五介電層。接著，^移除間隙壁之間 電層，以形成接觸窗開口，並^之間的部分第四介 開口中形成導電插塞。1中第底。繼之，於接觸窗 層之材質具有不同的餘刻選擇性:此=質，四介電 質例如是氮化梦，第五介電居 帛電層的材 依據本發明的較佳實施例所述矽。 法，其中間隙壁的材質例如是氮化^之接觸固的製造方 1292939 17869twf.doc/g 本發明先在頂蓋層中形成缺口，並使間隙壁填滿此缺' …也在後續备項勉刻製II製程以及光阻剝除時，1 本發明可以避免頂蓋層與盟篮璧名览產_生^ 接觸窗與閘極結構中的導體層隔絕，而增加元妓的良奉。 本發明提供一種非揮發性記憶體的製造方法，包括提 供基底，並於基底上形成數個第一記憶胞。第一記憶胞自 基底而上依序為第一複合層、第一導體層、第一頂蓋層與 . 、第一頂蓋層。其中於第一記憶胞上的第一頂蓋層外側形成 有數個缺口。然後，於各第一記憶胞的側壁上形成數個間 隙壁，這些間隙壁填滿缺口。之後，於各第一記憶胞之間 形成數個弟一記憶胞，這些第二記憶胞自基底與間隙壁的 側壁起依序為第二複合層與第二導體層。接著，移除這些 第二記憶胞的其中之一，以形成第一開口。此第一開口暴 露基底。繼之，於暴露的基底中形成源極/汲極區，並於源 極/没極區上形成接觸窗。 依據本發明的較佳實施例所述之非揮發性記憶體的 製造方法，其中間隙壁之材質與第一頂蓋層之材質具有不 同的蝕刻選擇性。間隙壁的材質例如是氮化矽，第一頂蓋 層的材質例如是氧化石夕。 ，依據本發明的較佳實施例所述之非揮發性記憶體的 製造方法，其中第一記憶胞的形成方法包括於基底上依序 形成第一複合層、第一導體層、第一頂蓋層與第二頂蓋層。 然後’圖案化第二頂蓋層與第-頂蓋層，以形成多數個第 二開口，第二開口暴露出部分第一導體層。之後，移除部 1292939 17869twf.doc/g - 分第一頂蓋層，以形成這些缺口。繼之，以第二頂蓋層為 . 罩幕，進行蝕刻製程，以移除部分第一導體層與第一複: • 層，並暴露基底。其中第一頂蓋層之材質與第二頂蓋層之 材質具有不同的触刻選擇性。 曰 • ,依據本發明的較佳實施例所述之非揮發性記憶體的 製造方法，其中第一記憶胞的形成方法包括於基底上^序 形成第一複合層、第一導體層、第一頂蓋層與第二頂蓋^。 φ 然後，圖案化第二頂蓋層、第一頂蓋層、第一導體層與第 一複合層，以形成暴露基底的數個第二開口。繼之，移除 f分第二頂蓋層，以形成缺口。其中第一頂蓋層之材質與 第二頂蓋層之材質具有不同的蝕刻選擇性。 …、 q生依據本發明的較佳實施例所述之非揮發性記憶體的 ^造方法，其中第一頂蓋層的材質例如是氧化矽，第二頂 蓋層的材質例如是氮化矽。 一、 依據本發明的較佳實施例所述之非揮發性記憶體的 •製造方法，其中間隙壁的形成方法包括於基底上形^繁 層4滿這些缺口。之後，進行非等向性= = 除第—介電層的—部分，直縣露第-記憶胞之間的 土&。其中於形成第一記憶胞後，及形成間隙壁前， 括於各第-導體層表面形成第二介電層。另外，第 層的材質例如是氣化⑦，第二介電層的材質例如是氧化石夕。 3本發日㈣較佳實闕所述之非揮發性記憶體的 法，其中形成接觸窗的步驟包括於基底上形成妓形 的第三介電層，覆蓋第一開口表面。然後，於第三介Ϊ層 1292939 17869twf.doc/g 上形成一層第四介電層，填滿第一開口。接著，移除開口 上的部分第四介電層，再移除部分第三介電層，以形成接 觸窗開口（Contact Window)，並暴露源極/汲極區。繼之， 於接觸ή開口中形成導電插塞(Plug)。其中第四介電層之 材質與第三介電層之材質具有不同的蝕刻選擇性。此外， 第二介電層的材質例如是氮化石夕，第四介電層的材質例如 是氧化石夕。 ^ 依據本發明的較佳實施例所述之非揮發性記憶體的 製造方法，其中第一複合層與第二複合層的材質例如是氧 化矽/氮化矽/氧化矽堆疊層，第一導體層與第二導體層的 材質例如是摻雜多晶矽。 本發明先在頂蓋層中形成缺口，並使間隙壁填滿此缺 口，因此在後續各項蝕刻製程、清洗製程以及光阻剝除時， 本發明可以避免頂蓋層與間隙壁之間產生缺陷，使後續的 接觸1¾與5己憶胞中的導體層隔絕，而增加記憶體的良率。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【貫施方式】 而圖2A至圖2G是依據本發明一實施例所繪示的接觸 囪的製造方法流程剖面圖，此製造方法以一 s〇N〇s記憶 體元件為例進行說明，但不以此為限。 #清參照圖2A，提供基底2〇〇,基底2〇〇例如是矽基底。 接著’於基底200上依序形成複合層2〇4、導體層2〇6、頂 1292939 17869twf.doc/g 蓋層208與頂蓋層210。複合層204的材質例如是氧化石夕/ 氮化石夕/氧化矽堆疊層，複合層204的形成方法例如是先以 熱氧化法於基底200上形成一層氧化矽層，再以化學氣相 沈積法於此氧化矽層上形成氮化矽層，然後以化學氣相沈 積法形成另一層氧化矽層。導體層206的材質例如是摻雜 多晶石夕’導體層206的形成方法例如是利用化學氣相沈積 法形成一層未摻雜多晶矽層後，進行離子植入步驟以形成 之，或者也可以採用臨場植入摻質之方式，以化學氣相沈 積法形成之。頂蓋層208的材質例如是氧化矽，頂蓋層2〇8 ， 的形成方法例如是化學氣相沈積法。頂蓋層210的材質例 如是氮化矽。頂蓋層210的形成方法例如是化學氣相沈積 法。 然後’ 5月參,¾圖2B ’圖案化頂蓋層21 〇與頂蓋層208， 以形成頂蓋層2〇8a、頂蓋層210a、以及數個暴露導體層 206之一部分的開口（未繪示）。之後，移除這些開口側壁上 的頂蓋層208a的-部分，以於開口側壁上形成缺口 212 ; 以頂蓋層210a為罩幕，進行第一餘刻製程，以移除部分導 體層206與複合層綱，以形成導體層綱&與複合層 2〇4a’並暴露基底200而形成記憶胞2〇2。其中，缺口 212 的形成方法例如是祕刻製程，此祕刻製程義刻液例 如疋氫氣酸與氟化氨的混合溶液。另外，頂蓋層2〇8a之材 質與頂蓋層21Ga之材質例如具有不同的㈣選擇性。 在另一種記憶胞202的形成方法中，可以將缺口 212 的形成步驟排在最後’換言之，先形成導體層顺、與複合 1292939 17869twf.doc/g 層204a ’再於開口側壁上形成姑 j 土上办成缺口 212，而形成記憶胞 202。在此方法中，其他各製程步驟與前述方法大致相同。 、接著，請參照圖2C，例如進行快速熱回火製程，以 於導體層206表面形成介電層214。之後，於基底上A method of fabricating a contact window according to a preferred embodiment of the present invention includes forming a second dielectric layer engraving process on a substrate to remove a portion of the second dielectric layer until two t=, Substrate. Wherein the shape; the former === dimorphic; the first: the layer. In addition, the second dielectric layer 2 = Hua Xi #2; | the material of the electrical layer is, for example, oxidized stone. The second embodiment of the preferred embodiment of the invention includes a portion of the fifth dielectric layer formed on the substrate to form a fifth portion of the conformal dielectric layer. Next, the electrical layer between the spacers is removed to form a contact opening, and a conductive plug is formed in a portion of the fourth dielectric opening. The first in the middle. Then, the material of the contact window layer has different residual selectivity: the quality of the fourth dielectric is, for example, a nitride, and the material of the fifth dielectric layer is in accordance with a preferred embodiment of the present invention. Speaking. The method in which the material of the spacer is, for example, the contact of the nitride is manufactured by the manufacturer 1292939 17869 twf.doc/g. The invention first forms a gap in the cap layer and fills the gap with the gap. In the engraving system II process and the photoresist stripping, the invention can avoid the isolation of the top cover layer and the conductor layer of the gate structure and the gate structure, and increase the goodness of the Lantern Festival. The present invention provides a method of fabricating a non-volatile memory comprising providing a substrate and forming a plurality of first memory cells on the substrate. The first memory cell is sequentially from the substrate to the first composite layer, the first conductor layer, the first cap layer and the first cap layer. There are several notches formed on the outside of the first cap layer on the first memory cell. Then, a plurality of gap walls are formed on the sidewalls of the respective first memory cells, and the spacers fill the gaps. Thereafter, a plurality of memory cells are formed between the first memory cells, and the second memory cells are sequentially the second composite layer and the second conductor layer from the sidewalls of the substrate and the spacer. Next, one of the second memory cells is removed to form a first opening. This first opening exposes the substrate. A source/drain region is then formed in the exposed substrate and a contact window is formed on the source/no-polar region. A method of fabricating a non-volatile memory according to a preferred embodiment of the present invention, wherein the material of the spacer has a different etch selectivity from the material of the first cap layer. The material of the spacer is, for example, tantalum nitride, and the material of the first top cover layer is, for example, oxidized stone. According to a preferred embodiment of the present invention, a method of fabricating a non-volatile memory, wherein a method of forming a first memory cell includes sequentially forming a first composite layer, a first conductor layer, and a first cap on a substrate The layer and the second cap layer. The second cap layer and the first cap layer are then patterned to form a plurality of second openings that expose a portion of the first conductor layer. Thereafter, the removal portion 1292939 17869twf.doc/g - is divided into first top cover layers to form the gaps. Then, the second cap layer is used as a mask to perform an etching process to remove portions of the first conductor layer and the first layer: and expose the substrate. The material of the first cap layer and the material of the second cap layer have different etch selectivity. According to a preferred embodiment of the present invention, a method of fabricating a non-volatile memory, wherein a method of forming a first memory cell includes forming a first composite layer, a first conductor layer, and a first The top cover layer and the second top cover ^. φ Then, the second cap layer, the first cap layer, the first conductor layer and the first clad layer are patterned to form a plurality of second openings exposing the substrate. Next, f is removed to divide the second cap layer to form a gap. The material of the first cap layer and the material of the second cap layer have different etching selectivity. The method for manufacturing a non-volatile memory according to the preferred embodiment of the present invention, wherein the material of the first cap layer is, for example, yttrium oxide, and the material of the second cap layer is, for example, tantalum nitride. . A method of manufacturing a non-volatile memory according to a preferred embodiment of the present invention, wherein the method of forming a spacer comprises forming a layer 4 on the substrate to fill the gap. After that, the anisotropy = = except for the part of the first dielectric layer, the soil between the straight and the memory cells. The second dielectric layer is formed on the surface of each of the first conductor layers after forming the first memory cell and before forming the spacer. Further, the material of the first layer is, for example, vaporization 7, and the material of the second dielectric layer is, for example, oxidized stone. The method of forming a contact window, comprising forming a contact-shaped third dielectric layer covering the first opening surface, is formed by the method of forming a contact window. Then, a fourth dielectric layer is formed on the third dielectric layer 1292939 17869twf.doc/g to fill the first opening. Next, a portion of the fourth dielectric layer on the opening is removed, and a portion of the third dielectric layer is removed to form a contact window and expose the source/drain regions. Next, a conductive plug is formed in the contact opening. The material of the fourth dielectric layer and the material of the third dielectric layer have different etching selectivity. Further, the material of the second dielectric layer is, for example, nitride nitride, and the material of the fourth dielectric layer is, for example, oxidized oxide. The method for manufacturing a non-volatile memory according to the preferred embodiment of the present invention, wherein the material of the first composite layer and the second composite layer is, for example, a yttria/tantalum nitride/yttria stack layer, a first conductor The material of the layer and the second conductor layer is, for example, doped polysilicon. The present invention first forms a notch in the cap layer and fills the gap between the cap layers, so that the present invention can avoid the occurrence of between the cap layer and the spacer during subsequent etching processes, cleaning processes, and photoresist stripping. The defect causes the subsequent contact 13⁄4 to be isolated from the conductor layer in the 5 cells, thereby increasing the yield of the memory. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 2A to 2G are cross-sectional views showing a method of manufacturing a contact baffle according to an embodiment of the present invention. The manufacturing method is described by taking a s〇N〇s memory device as an example, but Not limited to this. #清 Refer to FIG. 2A, a substrate 2 is provided, and the substrate 2 is, for example, a crucible substrate. Next, a composite layer 2〇4, a conductor layer 2〇6, a top 1292939 17869 twf.doc/g cap layer 208 and a cap layer 210 are sequentially formed on the substrate 200. The material of the composite layer 204 is, for example, a oxidized oxide/Nitrix cerium/cerium oxide stacked layer. The composite layer 204 is formed by, for example, thermally forming a layer of ruthenium oxide on the substrate 200 by chemical vapor deposition. A tantalum nitride layer is formed on the tantalum oxide layer, and then another layer of tantalum oxide is formed by chemical vapor deposition. The material of the conductive layer 206 is, for example, a method of forming the doped polycrystalline stone conductor layer 206, for example, after forming an undoped polysilicon layer by chemical vapor deposition, performing an ion implantation step to form, or may be employed. The method of implanting the dopant in the field is formed by chemical vapor deposition. The material of the cap layer 208 is, for example, cerium oxide, and the cap layer 2 〇 8 is formed by, for example, chemical vapor deposition. The material of the cap layer 210 is, for example, tantalum nitride. The method of forming the cap layer 210 is, for example, a chemical vapor deposition method. Then, 'May, Ref. 2B', patterned cap layer 21 and cap layer 208 to form openings for cap layer 2〇8a, cap layer 210a, and portions of several exposed conductor layers 206 (not Painted). Thereafter, portions of the cap layer 208a on the sidewalls of the openings are removed to form a notch 212 on the sidewalls of the opening; and a capping layer 210a is used as a mask to perform a first process to remove a portion of the conductor layer 206 and The composite layer is formed to form a conductor layer & and the composite layer 2〇4a' and expose the substrate 200 to form a memory cell 2〇2. The method for forming the notch 212 is, for example, a secret engraving process, such as a mixed solution of hydrogen peroxide and ammonium fluoride. Further, the material of the cap layer 2A8a and the material of the cap layer 21Ga have, for example, different (four) selectivity. In another method of forming the memory cell 202, the formation step of the notch 212 may be arranged at the end. In other words, the conductor layer is formed first, and the composite 1292939 17869 twf.doc/g layer 204a' is formed on the sidewall of the opening. The gap 212 is formed to form the memory cell 202. In this method, the other process steps are substantially the same as those described above. Next, referring to FIG. 2C, for example, a rapid thermal tempering process is performed to form a dielectric layer 214 on the surface of the conductor layer 206. After, on the substrate
形成-層介電層（未_)，並移除此介電層的—部分，直 到暴露記憶胞2G2之間的基底·，而於記憶胞搬的側 壁上形成間隙壁216。間隙壁216填滿缺口 212。其中間隙 、壁216之材質與介電層214之材質例如具有不同^侧選 擇性’以保護導體層2G6。此外，此構成間隙壁216的介 電層的材質例如是氮化矽，介電膚214的材質例如是氧化 矽。間隙壁216之材質與頂蓋層2〇8之材質具有不同的蝕 刻選擇性，特別是以氮化矽間隙壁216填滿氧化矽頂蓋層 208上的缺口 212，使頂蓋層2〇8在後續各項蝕刻製程、清 洗製程以及光阻剝除時，均不會產生損傷或缺陷。A dielectric layer (not _) is formed, and a portion of the dielectric layer is removed until the substrate between the memory cells 2G2 is exposed, and a spacer 216 is formed on the side wall of the memory cell. The spacer 216 fills the notch 212. The material of the gap, the wall 216 and the material of the dielectric layer 214 have, for example, different side selectivity to protect the conductor layer 2G6. Further, the material of the dielectric layer constituting the spacer 216 is, for example, tantalum nitride, and the material of the dielectric skin 214 is, for example, ruthenium oxide. The material of the spacer 216 has different etching selectivity from the material of the cap layer 2〇8, in particular, the gap 212 of the ceria capping layer 208 is filled with the tantalum nitride spacer 216, so that the cap layer 2〇8 No damage or defects will occur during subsequent etching processes, cleaning processes, and photoresist stripping.
之後，請參照圖2D，於記憶胞202之間形成記憶胞 218,記憶胞218自基底2〇〇與間隙壁216的側壁起依序為 複合層220與導體層222。複合層220的材質例如是氧化 矽/氮化矽/氧化矽堆疊層，導體層222的材質例如是摻雜 多晶石夕。記憶胞218的形成方法例如是先於基底20〇上依 序形成一層共形的複合層與導體層（未繪示），然後以回蝕 刻的方式去除此複合層與此導體層的一部分，直到暴露記 憶胞202。由於此SONOS記憶體具有間隙壁216填滿缺口 212的設計，因此可以在上述的回蝕刻製程中保護導體層 206,避免導體層206因頂蓋層208在後續各項蝕刻製程、 13 1292939 17869twf.doc/g 清洗製程以及光阻剝除時所產生損傷或缺陷而外露。 繼之，請參照圖2E，移除記憶胞218的其中之一，以 形成開口 224，開口 224暴露基底200。因為此SONOS記 憶體具有間隙壁216填滿缺口 212的設計，所以可在移除 記憶胞218的各蝕刻製程中保護導體層206，避免導體層 206因頂蓋層208在後績各項姓刻製程、清洗製程以及光 阻剝除時所產生的缺陷而外露。然後，於暴露的基底200 中形成源極/汲極區226,源極/汲極區226的形成方法例如 是離子植入法。 之後，請參照圖2F，於基底200上依序形成共形的介 電層228與介電層230,介電層228覆蓋開口 224的表面， 介電層230填滿開口 224。介電層228的材質例如是氮化 矽，介電層230的材質例如是氧化矽。接著，例如以微影 蝕刻製程，移除開口 224上方的介電層230。然後，例如 =溼蝕刻來移除開口 224上方的介電層228，以形成接觸 窗開口 232。介電層230之材質與介電層228之材質例如 具有不同的蝕刻選擇性，其中在移除介電層23〇時，、介電 層228是做為襯層，因此，接觸窗開口 232能夠自行對 源極/没極區226 ;在移除介電層228時，因為此_ 記憶體具有_壁216填滿缺口 212的設彳，因此可 移除介電層228時保護導體層施而避免導體層2 繼之，請參照圖2G，於接觸窗開口 232中形 插塞234，並於接觸窗開口 232及導電插塞说之間= 擴散阻障層235。導電插塞234之材質例如是鹤，而擴散 1292939 17869twf.doc/g 阻障層235之材質例如是氮化鈦。導電插塞234斑擴 =如的形成方法已為習知技藝者所熟知，故；;此不再 綜上所述，本發明先在頂蓋層中形成缺口，並 壁填滿此缺CT ’因此在後續各棚程、清洗製程以及 光阻剝除時，本發明可以避免頂蓋層與間_之間產生缺Thereafter, referring to FIG. 2D, a memory cell 218 is formed between the memory cells 202. The memory cell 218 is sequentially a composite layer 220 and a conductor layer 222 from the sidewalls of the substrate 2 and the spacer 216. The material of the composite layer 220 is, for example, a hafnium oxide/tantalum nitride/yttria stacked layer, and the material of the conductor layer 222 is, for example, doped polycrystalline. The memory cell 218 is formed by, for example, sequentially forming a conformal composite layer and a conductor layer (not shown) on the substrate 20, and then removing the composite layer and a portion of the conductor layer by etchback. Memory cell 202 is exposed. Since the SONOS memory has a design in which the spacer 216 fills the notch 212, the conductor layer 206 can be protected in the above-described etch back process, and the conductor layer 206 is prevented from being subjected to the subsequent etching process by the cap layer 208, 13 1292939 17869 twf. The doc/g cleaning process and the damage or defects generated during the photoresist stripping are exposed. Next, referring to FIG. 2E, one of the memory cells 218 is removed to form an opening 224 that exposes the substrate 200. Because the SONOS memory has a design in which the spacers 216 fill the notches 212, the conductor layer 206 can be protected in each etching process for removing the memory cells 218, so as to avoid the conductor layer 206 being inferior to the top layer 208. Processes, cleaning processes, and defects caused by photoresist stripping are exposed. Then, a source/drain region 226 is formed in the exposed substrate 200, and a source/drain region 226 is formed by, for example, ion implantation. Thereafter, referring to FIG. 2F, a conformal dielectric layer 228 and a dielectric layer 230 are sequentially formed on the substrate 200. The dielectric layer 228 covers the surface of the opening 224, and the dielectric layer 230 fills the opening 224. The material of the dielectric layer 228 is, for example, tantalum nitride, and the material of the dielectric layer 230 is, for example, tantalum oxide. Next, the dielectric layer 230 over the opening 224 is removed, for example, by a photolithographic etching process. The dielectric layer 228 over the opening 224 is then removed, for example, by wet etching to form the contact opening 232. The material of the dielectric layer 230 and the material of the dielectric layer 228 have different etching selectivity, for example, wherein the dielectric layer 228 is used as a liner when the dielectric layer 23 is removed, so that the contact opening 232 can The source/drain region 226 is self-contained; when the dielectric layer 228 is removed, since the memory _ has a wall 216 filled with the recess 212, the protective layer can be removed when the dielectric layer 228 is removed. Avoiding the conductor layer 2, referring to FIG. 2G, a plug 234 is formed in the contact window opening 232, and between the contact window opening 232 and the conductive plug is said to be a diffusion barrier layer 235. The material of the conductive plug 234 is, for example, a crane, and the material of the diffusion 1292939 17869 twf.doc/g barrier layer 235 is, for example, titanium nitride. The method of forming the conductive plug 234 is well known to those skilled in the art; therefore, the present invention no longer forms a gap in the cap layer, and the wall fills the missing CT ' Therefore, in the subsequent scaffolding, cleaning process, and photoresist stripping, the present invention can avoid the shortage between the cap layer and the interlayer.
陷’使後續的接觸窗與閘極結構或記憶胞中的導體、 絕，而增加元件的良率。 曰闲 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 摩έ圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1Α至圖1D疋依照習知的一種s〇n〇S記憶體所繪 示的製造流程剖面圖。 θ 圖2Α至圖2G是依據本發明一實施例所繪示的接觸 窗的製造方法流程剖面圖。 【主要元件符號說明】 100、200 :基底 102a、102b、202、218 :記憶胞 106a、106b、204、204a、220 :複合層 108a、108b :閘極 110、112、208、208a、210、210a :頂蓋層 114 :間隙壁 15 1292939 17869twf.doc/g 115 :標記 116、224 :開口 118、226 :源極/汲極區 120 :襯層 122、214、228、230 :介電層 124、232 :接觸窗開口 126、234 ·•導電插塞 206、206a、222 :導體層 212 :缺口 216 :間隙壁 235 :擴散阻障層 16The trapping causes the subsequent contact window to be connected to the gate structure or the conductor in the memory cell, thereby increasing the yield of the component. Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The protection of the present invention is defined by the scope of the patent application appended hereto. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process in accordance with a conventional s〇n〇S memory. θ FIG. 2A to FIG. 2G are cross-sectional views showing a flow of a method of manufacturing a contact window according to an embodiment of the invention. [Description of main component symbols] 100, 200: substrates 102a, 102b, 202, 218: memory cells 106a, 106b, 204, 204a, 220: composite layers 108a, 108b: gates 110, 112, 208, 208a, 210, 210a : cap layer 114 : spacer 15 1292939 17869twf.doc / g 115 : mark 116 , 224 : opening 118 , 226 : source / drain region 120 : lining 122 , 214 , 228 , 230 : dielectric layer 124 , 232: contact window openings 126, 234 · conductive plugs 206, 206a, 222: conductor layer 212: notch 216: spacer 235: diffusion barrier layer 16