1258213 16045twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體元件及其製造方法，且特 別是有關於一種可降低字元線阻值的記憶體元件及其製造 方法。 【先前技術】 記憶體元件是用以儲存資料或數據的半導體元件。舉1258213 16045twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a memory element and a method of fabricating the same, and more particularly to a memory element capable of reducing the resistance of a word line and Its manufacturing method. [Prior Art] A memory element is a semiconductor element for storing data or data. Lift
例來說，目前有一種記憶體元件的結構是由呈陣列排列之 記憶胞所構成，其中有配置在基底中的數條、埋入式位元 線、垂直於埋入式位元線並配置在基底上的數條字元線、 在基底與字元線之間的閘氧化層。此外，在兩相鄰的字元 線之間還設置有介電層，藉此互相作電性隔離。 近來，半導體元件不斷地朝小型化發展，記憶體元件 也隨著積體電路積集度之提高而逐漸縮小。因此，記憶體 元件中之子元線的寬度也將隨之縮減。然而n線的寬 度k窄會造成其阻值上升，使得記憶胞的電流變小。 【發明内容】 本發明的目的就是在提供一種記憶體元件，可提 流亚降低字元線阻值，進而增加元件之操作速度。 法，可目的是提供一種記憶體元件的製造方 易衣侍子兀線阻值較低的記憶體元件。 字4發:=—種記憶體元件，是由-基底、隔嶋^ 成。:中、間隙壁、導體塊與曝層所構 中_結構沿—第—方向設置於基底上，字元缘 6 1258213 16045twf.doc/g 則沿-第二方向橫跨於隔離結構上。再者，有數個間隙壁 位於字元線之側壁，而導體塊則位於基底與字元線及間隙 壁之間’且導體塊還位於隔離結構之間。此外，間氧化層 是位於基底與各導體塊之間，埋入式位元線則位於隔離^ 構底下的基底内。 依照本發明的較佳實施例所述記憶體元件，上述 隙壁的材質包括介電質。 依照本發明的較佳實施例所述記憶體元件，更包括一 硬罩幕，其錄各字元線_面。此外，上料體塊的頂 面可低於隔離結構的頂面。 、 依照本發明的較佳實施例所述記憶體元件，上述之 離結，包括高密度_(high density ρ1_，卿)氧二 層、字元線包括多晶矽層，且導體塊包括多晶矽層。 —本發=再提出一種記憶體元件的製造方法，包括提供 -基底’這個基底上形成有沿第一方向交替排列的 構與數條第-導體層，而在第一導體層與基底之間形 成有一閘氧化層，且在隔離結構底下的基底内具有數停埋 ，於基底上形成一第二導體層覆蓋隔離 、。冓二弟:V體層，其中第二導體層例如包括多晶矽層。 再於第二導體層上形成沿第二方向排列的數條硬罩幕。曰 ，二J用硬罩幕作為钱刻罩幕，去除第二導體層，以形成 丈如字7G線，再於字元線的侧壁形成數個間隙壁。然後， 利用硬罩幕與間隙壁作為細罩幕，去除第For example, there is currently a memory device structure consisting of memory cells arranged in an array, wherein there are several, buried bit lines arranged in the substrate, perpendicular to the buried bit lines and configured A plurality of word lines on the substrate, a gate oxide layer between the substrate and the word lines. In addition, a dielectric layer is disposed between two adjacent word lines to electrically isolate each other. Recently, semiconductor elements have been continuously miniaturized, and memory elements have been gradually reduced as the degree of integration of integrated circuits has increased. Therefore, the width of the sub-line in the memory component will also decrease. However, the narrowness k of the n-line causes its resistance to rise, making the current of the memory cell small. SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device that can reduce the resistance of a word line and thereby increase the operating speed of the device. The method can be used to provide a memory element in which the memory element is manufactured with a low resistance value. Word 4: = - a kind of memory component, which is made up of - substrate and barrier. The middle, the spacer, the conductor block and the exposed layer are disposed on the substrate along the first-direction, and the character edge 6 1258213 16045twf.doc/g is traversed on the isolation structure in the second direction. Furthermore, there are a plurality of spacers located on the sidewalls of the word lines, and the conductor blocks are located between the substrate and the word lines and the spacers and the conductor blocks are also located between the isolation structures. In addition, the inter-oxide layer is located between the substrate and each of the conductor blocks, and the buried bit line is located within the substrate under the isolation structure. According to the memory device of the preferred embodiment of the present invention, the material of the spacer includes a dielectric. The memory device in accordance with a preferred embodiment of the present invention further includes a hard mask that records each word line. In addition, the top surface of the body block can be lower than the top surface of the isolation structure. In accordance with a preferred embodiment of the present invention, the memory device includes a high density high (high density ρ1_) oxygen layer, a word line including a polysilicon layer, and the conductor block includes a polysilicon layer. - The present invention further proposes a method of fabricating a memory device comprising: providing a substrate - a substrate having alternating formations in a first direction and a plurality of first conductor layers, and between the first conductor layer and the substrate A gate oxide layer is formed, and the substrate is buried in the substrate under the isolation structure, and a second conductor layer is formed on the substrate to cover the isolation. Second brother: V body layer, wherein the second conductor layer includes, for example, a polysilicon layer. A plurality of hard masks arranged in the second direction are formed on the second conductor layer.曰, IIJ uses a hard mask as a money mask to remove the second conductor layer to form a 7G line, and then form a plurality of spacers on the sidewall of the word line. Then, using the hard mask and the spacer as a thin mask to remove the
形成數個導體塊。 U 1258213 16045twf.doc/g 、依照本發明的另一實施例所述記憶體元件的製造方 法，上述之提供基底之步驟包括先在基底上形成一間氧化 層^再於，氧化層上形成一多晶石夕層。接著，於多晶石夕層 上形成以第一方向排列的數條氮化矽層，再以氮化矽層作 為，刻罩幕，去除多晶矽層直到暴露出基底，以形成上述 導體層。之後，讀㈣層作為罩幕，對基底進行 —離子植人製程，以於基底_成上述埋人式位元線，再 ⑩ 於基底上形成一高密度電漿氧化層，以覆蓋埋入式位元 ^氮化⑪層與第—導體層。織，等向性侧高密度電 桌氧化層，直到暴露出氮化矽層的頂邊。最後去除氮化矽 層而遠下的鬲密度電漿氧化層即為上述隔離結構。 、依照本發明的另一實施例所述記憶體元件的製造方 • ^上述形成沿第二方向排列的硬罩幕之步驟包括於第二 導體層上形成一氮化石夕層，再於氮化石夕層上形成一圖案化 光阻層，然後利用圖案化光阻層作為蝕刻罩幕，去除氮化 層、’> 以形成這些硬罩幕。而且，之後更包括直接移除圖 〃化光阻層；或是待形成字元線之步驟後再移除圖案化光 阻層。 、依照本發明的另一實施例所述記憶體元件的製造方 法，上述形成字元線之步驟包括利用前述隔離結構作為蝕 刻終止層。 、依照本發明的另一實施例所述記憶體元件的製造方 法’/上述於字元線的側壁形成間隙壁之步驟包括先於基底 乂成’I電層覆盍字元線與第一導體層，再回飯刻介電 8 1258213 16045twf.doc/g 層，直到暴露出第一導體層。 本發明由於可藉由字元線及其側壁上的間隙壁作為钱 刻罩幕，使得字元線底下之導體塊的寬度增加，因此可藉 此提升記憶胞的電流，進而降低字元線之阻值。同時 為間隙壁的原因而可縮減兩兩導體塊之間的距離，所以不 需耗費多於空間即可達到提升記憶胞電流並降低字元線阻 值，進而增加元件操作速度的功效。此外，由於本發明的 I 製造方法能結合現有製程，所以可輕易製得字元線阻值較 低的記憶體元件。 、 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖1疋依照本發明之第一實施例之記憶體元件的立體 透視圖。請參照圖1，本實施例之記憶體元件1〇是由一美 ^ 底100、隔離結構102、字元線1〇4、埋入式位元線1〇6: 間隙壁108、導體塊11〇與閘氧化層ία所構成。其中， 隔離結構102沿一第一方向設置於基底1〇〇上，且隔離結 構102例如包括高密度電漿氧化層或其它介電質。:字^ 線104是沿一第二方向横跨於隔離結構1〇2上，其中字元 線104例如包括多晶矽層。再者，間隙壁1〇8是仅於 線104之側壁，且其材質例如包括介電質。另外， Π0是位於基底1〇〇與字元線1〇4及間隙壁1〇8之間組並 位於兩兩隔離結構102之間，其中導體塊11〇的頂面可: 9 1258213 16045twf.doc/g 於隔離結構1Q2 _面且導體塊UQ例如包括多晶石夕層。 此外’閘氧化層112是位於基底⑽與各導體塊⑴之間， 埋入式位兀線106則位於隔離結構1〇2底下的基底謂 内。此外’在字元線1()4的頂面還可包括—層硬罩幕(hard mask) 114。 件的=、!^圖2E是依照本發明之第二實施例之記憶體天 件的衣程俯視與剖面圖。A plurality of conductor blocks are formed. According to another embodiment of the present invention, in the method of fabricating a memory device, the step of providing a substrate includes first forming an oxide layer on the substrate and then forming a layer on the oxide layer. Polycrystalline stone layer. Next, a plurality of tantalum nitride layers arranged in a first direction are formed on the polycrystalline layer, and a tantalum nitride layer is used as a mask to remove the polysilicon layer until the substrate is exposed to form the conductor layer. Thereafter, the (four) layer is read as a mask, and the substrate is subjected to an ion implantation process to form a high-density plasma oxide layer on the substrate to cover the buried type. The bit element is nitrided 11 layer and the first conductor layer. The isotropic side high density plasma oxide layer is exposed until the top edge of the tantalum nitride layer is exposed. Finally, the tantalum nitride layer is removed and the tantalum density plasma oxide layer is the above isolation structure. According to another embodiment of the present invention, a method of fabricating a memory device includes the steps of forming a hard mask arranged in a second direction, comprising forming a layer of nitride on the second conductor layer, and then depositing a nitride layer on the second conductor layer. A patterned photoresist layer is formed on the layer, and then the patterned photoresist layer is used as an etching mask to remove the nitride layer, '> to form the hard mask. Moreover, it is further included to directly remove the patterned photoresist layer; or to remove the patterned photoresist layer after the step of forming the word line. According to another embodiment of the invention, in the method of fabricating a memory device, the step of forming a word line includes using the foregoing isolation structure as an etch stop layer. The method for fabricating a memory device according to another embodiment of the present invention includes the step of forming a spacer on a sidewall of the word line, comprising: forming an 'I electrical layer overlying the word line and the first conductor before the substrate Layer, and then return to the meal 8 1258213 16045twf.doc / g layer until the first conductor layer is exposed. In the present invention, since the width of the conductor block under the word line is increased by the spacer on the word line and the sidewall thereof, the current of the memory cell can be increased, thereby reducing the word line. Resistance value. At the same time, the distance between the two conductor blocks can be reduced for the reason of the gap wall, so that it is possible to increase the memory current and reduce the word line resistance without using more space, thereby increasing the operation speed of the component. Further, since the manufacturing method of the present invention can be combined with the existing process, a memory element having a low word line resistance can be easily obtained. The above and other objects, features, and advantages of the present invention will become more fully understood from [Embodiment] Fig. 1 is a perspective perspective view of a memory element in accordance with a first embodiment of the present invention. Referring to FIG. 1, the memory device 1 of the present embodiment is composed of a bottom 100, an isolation structure 102, a word line 1〇4, and a buried bit line 1〇6: a spacer 108 and a conductor block 11 〇 and gate oxide layer ία. The isolation structure 102 is disposed on the substrate 1A along a first direction, and the isolation structure 102 includes, for example, a high density plasma oxide layer or other dielectric. The word line 104 is traversed over the isolation structure 1〇2 in a second direction, wherein the word line 104 includes, for example, a polysilicon layer. Further, the spacers 1 〇 8 are only on the side walls of the line 104, and the material thereof includes, for example, a dielectric. In addition, Π0 is located between the substrate 1〇〇 and the word line 1〇4 and the spacer 1〇8 and is located between the two isolation structures 102, wherein the top surface of the conductor block 11〇 can be: 9 1258213 16045twf.doc/ g is in the isolation structure 1Q2 _ plane and the conductor block UQ includes, for example, a polycrystalline layer. Further, the gate oxide layer 112 is located between the substrate (10) and each of the conductor blocks (1), and the buried germanium line 106 is located within the substrate under the isolation structure 1〇2. Further, the top surface of the word line 1() 4 may further include a layer hard mask 114. Fig. 2E is a plan view and a cross-sectional view of the memory of the memory device according to the second embodiment of the present invention.
請參照圖2A，其中的ί是俯視圖、π是工部分的^ ^段之剖面圖。本實施例U提供—基底，這個基底 J欠ΐ:成有沿第一方向交替排列的數條隔離結構202與 =導體層204 ’而在第一導體層2〇4與基底之 日n i :閘氧化層2°6 ’且在隔離結構2°2底下的基底 200内具有數條埋入式位元線2〇8。 接著，凊苓照圖2Β，其中的I是俯視圖、π是！部分 ” Β-Β:線段之剖面圖。於基底上先形成一第二導體層 10覆盍隔離結構202與第一導體層204。然後，於第二 體^!則ΐ形成沿第二方向排列的數條硬罩幕，其步驟例 如疋先在第二導體層21G上形成一氮化 圖2C之步驟。 丹接， 請參照圖2C，其中的ί是俯視圖、π是j部分的c_c 2之剖面圖’而Πί是I部分的C’ -C，、線段之剖面圖。 j ’於亂化石夕層（請見圖2β之212)上形成一圖案化光阻 g 214’再利用圖案化光阻層214作為钱刻軍幕，去除氮 化石夕層以开》成數條硬罩幕212a。而且，之後可選擇直接Please refer to FIG. 2A, where ί is a top view, and π is a cross-sectional view of the ^ ^ section. The present embodiment U provides a substrate which is under-supplied with a plurality of isolation structures 202 and = conductor layers 204' alternately arranged in the first direction and on the first conductor layer 2〇4 and the substrate The oxide layer is 2° 6 ′ and has a plurality of buried bit lines 2 〇 8 in the substrate 200 under the isolation structure 2° 2 . Next, see Figure 2Β, where I is the top view, π is! Partially Β-Β: a cross-sectional view of the line segment. A second conductor layer 10 is formed on the substrate to cover the isolation structure 202 and the first conductor layer 204. Then, in the second body, the ΐ formation is arranged in the second direction. The steps of a plurality of hard masks, for example, first forming a nitride pattern 2C on the second conductor layer 21G. Referring to FIG. 2C, where ί is a top view, π is a portion of c_c 2 The cross-section ' and Πί is the C'-C of the I part, and the cross-section of the line segment. j ' forms a patterned photoresist g 214' on the chaotic layer (see Figure 2 β 212) and reuses the patterned light. The resist layer 214 is used as a military engraving machine to remove the nitride layer to open a plurality of hard masks 212a.
1258213 16045twf.doc/g 移除圖案化光阻層214，或是 作後續侧製程之罩幕，稱後再將i餅層214留下當 罩幕接二㉗(圖二r罩幕2i2a作〜 开綠9切山 層（请見圖^之210)，以形成數你」 4線施’此時可前述 木子 層。而III部分則楚-道碰&、 z作為蝕刻終止 構202與第-導體層’2G4。_ g被去除而只剩下隔離結 j曲圖，而III疋I部分的jy ' :=、：凡線，的側壁形成數個間隙壁216，二 (未曰絡干^^步驟例如是先於基底2GG上形成-介電層 3、，，日不）復1子元線1〇4與第一導體層2〇4， 昭 介電層也會覆蓋隔離結構2〇2。然後，贿刻介電層、里= 到暴，出第一導體層204，即完成間隙壁216的製作。 最後，請參照圖2E，其中的I是俯視圖、π是丨部八 的Ε—Ε線段之剖面圖，而III是I部分的ε，—Ε，線段: 剖，圖。利用硬罩幕212a與間隙壁216作為蝕刻罩幕，去 除第一導體層（請見圖2D之204)，以形成數個導體塊2〇4a。 、、除此之外圖2a中提供基底2〇〇之步驟可採用一般的 半導體微影與蝕刻製程；或者如本實施例是利用如圖3A 至圖3所示的例子。 請參照圖3A至圖3D，其為第二實施例的圖2A之結構 的較佳製造流程剖面圖。於圖3A中，先在基底2〇〇上形成 間氧化層206，再於閘氧化層206上形成一多晶矽層。接 11 1258213 16045twf.doc/g 著，於多晶矽層上形成以第一方向（如圖2A所示）排列的數 條氮化矽層302，再以氮化矽層302作為蝕刻罩幕，去除 多晶矽層直到暴露出基底2〇〇，以形成圖2A的第一導體声 204 。 、曰 之後，請參照圖3B，以氮化矽層302作為罩幕，對基 底200進行一離子植入製程，以於基底200内形成埋入式 位兀線208，再於基底2〇〇上形成一高密度電漿（HDp)氧化 層304 ’以覆盍埋入式位元線2〇8、氮化矽層go〗與第一導 體層204。 〃 \ 然後，請參照圖3C，等向性蝕刻高密度電漿氧化層 304，直到暴露出氮化矽層3〇2的頂邊3〇3。 最後，請參照圖3D，去除氮化矽層（請見圖3C的3〇2)， 而留下的向密度電漿氧化層即為圖2A的隔離結構2〇2。 綜上所述，本發明之特點在於： 可藉由字元線及其側壁上的間隙壁作為蝕刻罩幕， ，付字το線底下之蝕刻後的導體塊之寬度比字元線的寬度 見，因此可藉此提升記憶胞的電流，進而降低字元線之阻 值。 、7 ^為間隙壁的原因，可不顧微影製程的限制來縮減 ¥體塊之間的距離。因此，不需額外空間即可達到 憶胞電流鱗低字元線阻值，進而增加元件操作速度的功 效。 3.由於本發明的製造方法能結合現有製程，譬如 至圖3D利用！ i f卜〇f f製程，所以可輕易製得字元線阻值 12 1258213 16045twf.doc/g 較低的記憶體元件。 —雖然本發明已以較佳實施例揭露如上，然其並非用以 限^本發明’任何熟習此技藝者，在不脫離本發明之精神 =範圍内’當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是依照本發明之第一實施例之記憶體元件的立體 透視圖。 圖2A至圖2E是依照本發明之第二實施例之記憶體元 件的製造流程俯視與剖面圖。 ' 圖3A至圖3D為第二實施例的圖2A之結構的較佳萝诰 流程剖面圖。 & 【主要元件符號說明】 10 :記憶體元件 100、200 :基底 102、202 ·隔離結構 104、210a ·字元線 106、208 ··埋入式位元線 108、216 :間隙壁 110、204a :導體塊 112、206 :閘氧化層 114、212a :硬罩幕 204、210 :導體層 212、302 :氮化石夕層 214·圖案化光阻層 303 :頂邊 304 ·南密度電聚氧化層 131258213 16045twf.doc/g Remove the patterned photoresist layer 214, or as a mask for the subsequent side process, and then leave the i-cake layer 214 as a mask to connect two 27 (Figure 2 r mask 2i2a for ~ Open the green 9-cut layer (see Figure 210) to form the number you "4 line Shi" can now be the aforementioned wood sub-layer. The III part is Chu-channel touch & z, as the etching termination structure 202 and the - The conductor layer '2G4. _ g is removed and only the isolation junction j curve is left, and the III 疋I part of jy ' :=,: the line, the sidewalls form a plurality of spacers 216, two (not 曰 干 ^ ^ The step is, for example, forming a dielectric layer 3 on the substrate 2GG, and a sub-member line 1〇4 and a first conductor layer 2〇4, and the dielectric layer also covers the isolation structure 2〇2. Then, bribe the dielectric layer, the inner=to the storm, and the first conductor layer 204, that is, the fabrication of the spacer 216. Finally, please refer to FIG. 2E, where I is a top view, and π is the top of the Ε- A cross-sectional view of the Ε line segment, and III is ε of the I portion, Ε, line segment: section, figure. The first conductor layer is removed by using the hard mask 212a and the spacer 216 as an etching mask (see Figure 2D, 204). To shape a plurality of conductor blocks 2〇4a, and, in addition, the step of providing the substrate 2〇〇 in FIG. 2a may employ a general semiconductor lithography and etching process; or as in this embodiment, as shown in FIGS. 3A to 3 3A to 3D, which are cross-sectional views showing a preferred manufacturing process of the structure of Fig. 2A of the second embodiment. In Fig. 3A, an inter-oxide layer 206 is formed on the substrate 2, and then A polysilicon layer is formed on the gate oxide layer 206. A plurality of tantalum nitride layers 302 arranged in a first direction (as shown in FIG. 2A) are formed on the polysilicon layer to be nitrided. The germanium layer 302 serves as an etching mask to remove the polysilicon layer until the substrate 2 is exposed to form the first conductor sound 204 of FIG. 2A. After 曰, please refer to FIG. 3B, and the tantalum nitride layer 302 is used as a mask. The substrate 200 is subjected to an ion implantation process to form a buried germanium line 208 in the substrate 200, and a high density plasma (HDp) oxide layer 304' is formed on the substrate 2 to cover the buried bit. The element line 2〇8, the tantalum nitride layer go and the first conductor layer 204. 〃 \ Then, please refer to FIG. C, isotropically etch the high-density plasma oxide layer 304 until the top edge 3〇3 of the tantalum nitride layer 3〇2 is exposed. Finally, please refer to FIG. 3D to remove the tantalum nitride layer (see FIG. 3C for 3). 〇 2), and the remaining density plasma oxide layer is the isolation structure 2〇2 of Fig. 2A. In summary, the invention is characterized in that: by the word line and the spacer on the side wall thereof The etching mask, the width of the etched conductor block under the line το line is wider than the width of the word line, so that the current of the memory cell can be increased, thereby reducing the resistance of the word line. , 7 ^ is the reason for the gap wall, regardless of the limitation of the lithography process to reduce the distance between the body blocks. Therefore, no additional space is required to achieve the resistance of the low current word line of the cell current scale, thereby increasing the efficiency of the component operation speed. 3. Since the manufacturing method of the present invention can be combined with existing processes, for example, to Figure 3D! i f 〇 f f process, so you can easily produce word line resistance 12 1258213 16045twf.doc / g lower memory components. The present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the invention to those skilled in the art without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective perspective view of a memory element in accordance with a first embodiment of the present invention. 2A to 2E are a plan view and a cross-sectional view showing a manufacturing process of a memory device in accordance with a second embodiment of the present invention. 3A to 3D are cross-sectional views showing a preferred process of the structure of Fig. 2A of the second embodiment. & [Major component symbol description] 10: Memory component 100, 200: Substrate 102, 202 · Isolation structure 104, 210a · Word line 106, 208 · Buried bit line 108, 216: Clearance wall 110, 204a: conductor block 112, 206: gate oxide layer 114, 212a: hard mask 204, 210: conductor layer 212, 302: nitride layer 214 · patterned photoresist layer 303: top edge 304 · south density electropolymerization oxidation Layer 13