SU640219A1 - Binary-quantized signal train detector - Google Patents

Description

The bits for which the clock input is given are the first clock pulses, the input of which is connected to the corresponding inputs of the second: the addition and subtraction siphnals, the output of the first elements, and the second and second f: 0rmirovl S | u, on. addition, and 1HYTH: ita1N1I1Ya are connected to the corresponding1 in hell | M of the first element OR, and the outputs of the second, И elements of AND the first. and iBToporo for1R | M; The rovers of the sipnal are added and subtracted are connected to the corresponding inputs of the second element. OR, the outputs of the first and 1 automatic: the OR element are connected to the corresponding inputs of ipeBeipiOHBHioro of the counter, to the other inputs of which are connected the outputs of the switching unit, to the control 1P. which is connected to one of the outputs of the control unit, the other outputs of which are connected to the U1 | U11 OWNER: M INPUT-M KONTROLUzHioro of the counter, the other input to the SJ-1 connection is connected to the shift register input and the NI bits, the output of the 10-meter counter d m respective UPI-th input switching unit .On the clock inputs of the control unit and .First and second AND elemento1V BTopOiro shaper signals, addition and subtraction filed third clock pulses.

The drawing shows a structural electrical circuit. The detector of a pack of binary-twisted sipnal.

The detector will maintain the register / shift for L bits, the input 2 of which is connected to: The first inputs 1Mi of the first elements NOT 3 and AND 4 of the first .fIRMINATER 5 siitalov addition and subtraction, and the output with the first inputs The second elements are NOT 5 and AND 7 of the first form of the add and subtractor signal 5 slots, the inputs are still and 8 are connected to the corresponding output and reverse and BiHo of the counter 9, and .master / .shift / on N bits and decipher.ato | ra 5 served le) time clock pulses 10, iBTOpbie clock | Pulses // served on the second inputs. first and the second elements AND 4, 7 of the first .former 5 add and subtract signals; to the third inputs of which. are connected respectively the outputs .BTOiporo and nepBioro of HE €, J. elements of the first former 5 add and subtracted signals, as well as register 12 Shifting i: iia bits, second form. 13 ohpol-adding and 1 subtracting. NI: I, identical to the first driver, 5 sig.t. addition and subtraction, .first and second elements OR 14 15 "control unit to 16, the switching unit 17, the control unit 18 of the control 1I. the cells, and the el.9.9NT 19, while the output register ./ Oduig for N bits it is connected through an additional electronic element NOT 19 to the input of the register 12. sdv, yoke to yVo 1p.a.zr: av, na ta1to.vy input which is supplied. 1n © the clock pulses 10, the input and output of which p.od.klyuch are connected to the. corresponding inputs. the second worldview of the driver 13

the signals of addition and subtraction, the outputs of the first el. ements in And 4 of the first 5 and second 13 fm. amplifiers of signals and Addition and subtraction of P are admitted to the corresponding inputs of the first element OR 14, and the outputs of the second elements And 7 and second J3 formulas. The signals of addition and subtraction are connected to the corresponding inputs 1M of the second electric element OR 15, outputs

.o.og.o and iBTo.pOiro elements.OR 14, 15 are connected to the corresponding input of the reversible counter 9, to the other inputs of which are switched on the outputs of the / 7 switching unit, to the control input of which

One of the outputs of the control unit 18 is connected, the other outputs of which are connected to the control inputs of the control counter 16, another one. The input of the last one is connected to the input. 2 of the 1 shift register NI dazrs, the outputs of the control counter of the detector 16. Are connected to other suitable gateways. block 17 switches to the clock inputs of the block of 18 controls of the first and second, second elements And 4, 7 of the second driver 13

Comparison and 1HIFTAUT.SED.NAYS, Third tactical pulses 20. Output 21 is the output of the armature.

The detector works as the next.

The input is a deterministic stream of rectangular pulses S (K), where / C is the number of the Interval with a duration T, and there is no stream in the output of the register / other stream delayed by the rectangular clock cycles

Y.puls.01v S (K-NI), 1 at the output of the additional oln.natelnogo element HE 19 - flow (In. Rev. certified pulses S (K.-NI), and at the output register 12-stream delayed. on

cycles of flat square S pulses (K-

-L / i -nq) where. The delay is effected by the clock pulse pulses 10.

At the moment of cash flow, the second clock pulse // sipial "1 enters the input of the addition of a revsied counter 9 from the output

the signals of the addition of the throttle 5 (your input of the first BoBro of the element AND 4) through the first input element of OR 14 are only n; pu 5 (/ (), S (K-NI) O, and the input to the subtraction input is 5 counters - from the output.

subtracting the form factor 5 (output of the second electric motor) and 7) through the second element OR / 5 only three 5 (/ С) 0, S (KN:) 1, since due to the inverting effect of the first and second NOT items

3b on the inputs of the corresponding .pop. O and the second elements And 4, 7 there is a signal. 1 ". As a result, the reversible counter 9 contains in each time interval a term equal to the number "1 in the interval, as each impulse entering the interval" 1 increases, and each impulse leaving the interval reduces by one the reading of the reversible counter 9 and simultaneously incoming

and the output pulses "1 or" O of the readings of the reversible counter 9 do not change. Similarly, images in; mombnt, ichi of the third motor impulse 20, the signal "1 is set to the input of the addition of a reversible counter 9 from the output of the analogs of the addition of the forma. 13 (BIODE of the first element AND 4) through the first element OR il4 only S (/ C-L) l, 5 (/ C-.V ,-yVo) 0 and .to the input of the subtraction of the roar of the SURGE: Nogo counter 9 from the output. С1И Г | element AND 7) through the second element OR 15 only at 5 (/ C-yV,) 0, S (K Ni-No). Therefore, in the reversible: new meter of the counter 9, for each instant of time there is a term equal to the number of zeros of the next one: the flow (| thanks to T1 and 11); in the NoT interval preceding the interval L / iT. The decoder 5 at the time of availability of the first TaiKTOBOiro IM | Gulsa 10 generates a decision on the detection of a wheelbarrow if the number of the reverse: the count of 9 is greater or the p.asHo nopODOiBOiMy number. The third 20 and second 11 clocks are distributed in time to exclude simultaneous signals: to the revisive counter 9. The detector works in the ring mode and on each gate defined by the first clock: pulse. M | AND JO, compute 1 the sum of the number of units in the NiT interval and the number of iB in the iB preceding it in the NdY interval compares it with the threshold number, for which ir-Eushevia is formulated by the decision About B | H ar phenia p.ach.ki. The control counter K1 | K 16 counts the number “1” and “About the input signal in the interval mode. -Pr. And this block 18 Provides for him the work according to the algorithm: setting to zero, lodging the number of variables in the interval, 1 counting the number of units in the interval, and dividing the number of control counts: of whom the counter is 16 with. Using the block 17 in the 1st counter 1 counter 9 Next, the process is repeated. This ensures that the reversing counter 9 is activated in case of its failure. F o rumula and 3 o f e e 1. - The detector of a packet of binary quantized signals containing a shift register for NI bits, the input of which is connected to the first inputs of the first NOT and AND elements of the first adder and subtracting, and the output with the first inputs of the second NOT and AND elements of the first imager of the addition and subtraction signals, the inputs of the decoder are connected to the center (the reverse output of the counter, etc., and the clock inputs of the shift register :: - ia L | bits and the decoder subals first clock, second clock The first pulses of 1 are applied to the second inputs of the first and second elements AND the first driver of the addition and subtraction signals, to the third inputs of which the outputs of the second and the first elements of the first driver of the addition and subtraction, respectively, are different, with the purpose of increasing the accuracy detecting a bundle of binary-quantized signals with an unknown MOQ of her arrival, containing a slider from L | edpnits and preceding it a slush from L0 zeros, a shift register and NQ bits was entered into it, the second generator signal Add and subtract, identical to the first compiler of the addition and subtraction ciphers, the first and second elements IL: I, the control counter, the switching unit, the control unit and the ADDITIONAL element NOT, and this is the output of the register Sdv: yoke for L bits Connected through the optional element NOT To the input of the shift register "a bit, to the clock input of which the first clock pulses are fed, the input and output of which are connected to the corresponding steps of the second addition and subtraction signals, the outputs of the first elements of the first and the iBTOp Oro of the addition and subtraction signal formers are connected to the corresponding inputs of the first element OR, and the outputs (the second AND elements of the first: and second addition signal formers and (subtraction are connected) To the corresponding inputs of the second OR element, the outputs of the first and second elements OR are connected to the corresponding inputs of the reversal of the counter , To other INPUTS: M of which is disconnected 1 OUTPUTS of the switching unit, to the etching input — which one of the outputs of the control unit is switched on, the other outputs of which are connected to The controller entered the control counter, the other input of the latter was connected to the input of the shift register for Al bits, the outputs of the control counter for the other inputs of the lerexc block, the clock inputs of the control block and the first and second elements of the second signal generator the third clock pulses are applied The source information of the information applied to the examination during the examination: 1. V. Likharev. Digital methods and devices in radar :. .. “Soviet Radio, 1973. p. 108