SU1406759A1 - Differential digital pulse-width modulator - Google Patents

Abstract

The invention can be used in digital systems of automatic regulation and control. The digital differential pulse-width modulator (CCLLM) contains synchronization blocks 1.2, input buses, 7 clock pulses generator, 3 pulses counter, digital comparator 13, reversible counters 14, 15 pulses, elements 8-11, trigger 12 , elements OR 4-6, switches 16,17. CCLIM has an increased accuracy and an extended range of adjustment of the output signal duty ratio by eliminating the loss of input pulses. 1 il (L

Description

Entrance. L

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The invention relates to a pulse technique and can be used in digital systems of automatic regulation and control,

The aim of the invention is to improve the accuracy and quench the range of adjusting the duty cycle of the output signal by eliminating the loss of input pulses and setting the output trigger by the front of the clock pulse coming from the same clock generator output.

The drawing shows a functional diagram of the device. .

Digital differential pulse-width modulator contains synchronization blocks 1 and 2, a counter of 3 pulses, elements OR 4-6, a generator of 7 clocks, elements 8-11 of coincidence, trigger 12, digital comparator 13, reversible counters 14 and 15 of HMuyjijjCOB, switches 16 and 17, while the third output of the clock generator 7 is connected to the first inputs of the coincidence elements 8 and 9 and the input of the pulse counter 3, and its second and first outputs are connected to the corresponding inputs of the synchronization blocks 1 and 2, the first inputs of which are connected to the input. buses of the device, and the outputs - with the working inputs of the switches 16 and 17, respectively, the first outputs of which are connected respectively to the sum

and the subtracting inputs of the reversible counter 14 pulses, the direct outputs of which are connected to the inputs of the element OR 4 and the first inputs of the digital comparator 13, the output of which is connected to the second input of the coincidence element 8, and the second inputs to the outputs of the counter of 3 pulses, the inverse outputs of which are connected with the inputs of the coincidence element 11, the output of which is connected to the second input of the coincidence element 9, the third input of which is connected to the output of the element OR 4 and the first control inputs of the switches 16 and 17, the second control inputs to 14 pulses are connected to the inverted output of the higher bit of the reversible counter and the third input of the coincidence element 8 is connected to the first input-i input of the trigger 12, the second input of which is connected to the output of the 9 coincidence element and the outputs to the output buses of the device. This second

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five

Q 5 Q

the outputs of the switches 16 and 17 are connected to the inputs of the element OR 5, the third outputs are connected to the inputs of the element OR 6. The outputs of the elements OR 5 and 6 are connected to the summing and subtracting inputs of the reversing counter 15 pulses, the inverse outputs of which are connected to the inputs of the coincidence element 10, the output of which connected to the third control inputs of the switches 16 and 17.

The clock generator 7 continuously generates short pulses with a period t at the first output C. These pulses, delayed by the time 2G / 3 and 2C / 3, are in the second D and the third E outputs of the generator 7 "

The pulse arriving at the input A of the synchronization unit 1 is stored in it and arrives at its output simultaneously with the next impulse from the output C of the generator 7. Similarly, the impulse arriving at the input B of the synchronization unit 2 arrives at the output simultaneously with the impulse from the output O of the generator 7 The intervals between the pulses at each of the inputs A and B must be no less, otherwise some of the input pulses will be lost. Synchronization blocks eliminate the possibility of device malfunction, for example, when the pulses at inputs A and Bo coincide in time

Pulse counter 3 is an n-bit binary accumulating counter, triggered by a falling edge of the input pulses.

The trigger 12 is a conventional trigger with separate inputs, triggered on the leading edge of the pulses.

The digital comparator 13 has a single signal at the output only if the contents of the N counter of 3 pulses are equal to the contents of R (the reversible counter of 14 pulses, that is, if the condition is satisfied)

R., N

(one)

A reversible counter of 14 pulses has one bit more than a counter of 3 pulses, and is triggered by a falling edge of the input pulses. The reversible pulse counter 15 also triggers on the falling edge of the input 1-pulse, it serves as a drive for the input pulses of the device, arriving at the time when its output signal reaches saturation.

The impulse arriving at the operating input of the switch 16 from the output of the synchronization unit 1 goes to one of its three outputs depending on the signals at the control inputs: for all single signals - to the first, with a zero signal on the third G and single ones on the other second, with zero signal on the second F and single ones on the rest - on the first, with zero signals on the first H and third G and one on the second - on the second, with zero signals on the first and second and one on the third - on the third. The impulse delivered to the working input of the switch 17 from the output of the synchronization unit 2 goes to one of its three outputs depending on the signals at the control inputs: for all single signals - to the first, with zero signal to the third and single ones to the others. the first, with the zero signal on the second and the unit ones on the rest - on the second, with the zero signals on the first and third and the unit on the second - on the third, with the zero signals on the first and second and the unit on the third - on the second.

The digital differential pulse width modulator operates as follows

In the initial state, the counter 3, the trigger 12 and the reversible counter 15 are set to O, the reversible counter 14 is set to the state R, M / 2, where M 2 is H 1, so the outputs of blocks I and 2 of the synchronization are connected through switches 16 and 17 to the summing and subtracting inputs of the reversing counter 14,

First, let the pulses at the inputs A and B of the device be absent, i.e. there are no pulses at the inputs of the reversible counter 14. The pulses from the output E of the generator 7 fill the counter 3. The first of the bottom passes through element 9, since its other inputs 1 and sets the trigger 12 to 1. When after the M / 2 pulses is reached the implementation of equality (l), turns on a single signal at the output of the digital comparator 13, so (taking into account

the fact that G 1) the next impulse from the output E of the generator 7 will pass through the element 8 and will return the trigger 12 in about. After another M / 2 input pulses, the counter 3 will return to P, and the described process will be repeated periodically. The result of the operation of the device will be a periodic signal of a rectangular shape (at the output

trigger 12) with a period of T., M

and and

pulse duration T, i.e. with a duty cycle of oi 0,5.

Let now comes the momentum on

5 input A. It is added to the contents of the counter 14 by a pulse from the output C of the generator 7. If this happened before reaching equality (O, then the indicated equality will be achieved on

0 time f is later than in the previous case, i.e. the pulse duration at the output of the trigger I2 is increased by the same time, the duty ratio is reduced accordingly. If the pulse arrives at input A after reaching equality (1), a corresponding increase in the duration of the output pulse of the device occurs in the next period of the output signal.

0 If the pulse arrives not at the input A, but at the input B of the device, then synchronously with the output pulse O of the generator 7, it is subtracted from the contents of the counter 14, i.e. Equality (l) is reached at a time about earlier than in the absence of the specified pulse, and, therefore, the duration of the output pulse of the device decreases by the same time, and the duty cycle increases accordingly.

The device works similarly when pulses are received both at input A and at input B (we denote the number of these pulses by Nd and Ng, and their difference (mismatch) by Lm Md - Ng). Then, the installation of the trigger 12 in O is performed either a time later than in the absence of input pulses, if, or at the same time earlier, if o, and the installation of the trigger 12 in 1 is still performed at the same moments by the next clock pulse from the output E of generator 7 after the return of the counter 3 to O, the duration of the output impulses5

owl device is always equal to TM R, C.

In the manner described, the device operates at (l / "cM / 2. Let. At

the achievement of equality & M / 2 we get R, M, i.e. F 1, G O, H 1. In this case, the element 8 is closed at the second input, so that the trigger 12 in O is not reset, which corresponds to the case of TU, MC, i.e. oi / o, the device is in positive saturation mode. If now a pulse arrives at input B, then it takes the device out of this mode, reducing R, by one and thereby providing oL 2. If pulses arrive at input A, they go to the drive — to the summing input of the reverse counter 15. If, at N Q, F 1, G O (positive Nascene mode, moreover) pulses arrive at input B, they are subtracted from the contents of counter 15, to compensate unused pulses received at input A.

If the equality L –I / 2 is reached (negative saturation mode, with R (0), a single signal disappears at the output of 1Sh 4, and the trigger 12 will not be set to 1; 9) is closed at the first input, which corresponds to the duty cycle 1 (T, 0).

Wherein ,, . The impulse arriving at input A takes the device out of the negative Nascene mode, providing ot I - 2 (TI,), and the impulses arriving at input B enter the drive (at the summing input of the reversing pinch 15). In this case, we obtain, G 0, G 1, so that the pulses from the input A are fed to the subtractive input of the reversible counter 15, the capacity of which must be sufficient to accumulate all the error pulses before they are worked out, compensated by the pulses fed to the input A negative, and the input B - in the case of a positive nakspotseny.

Thus, due to the inputted blocks and functional connections, the limits of adjustment of the device output signal durability (limiting values oi O and oi l are used) extend, the loss of input pulses is eliminated, and the formation of discrete values of the duty cycle is more accurate, since output trigger 12 always overturns

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the front edge of a clock pulse passing through one of the identical coincidence elements from the same clock generator output.

Claims (1)

Claim 1 A digital differential pulse width modulator containing the first and second synchronization blocks, the first inputs of which are connected to the device input buses, and the second and third inputs - respectively to the first and second outputs of the clock generator, the third output of which is connected to the input of the pulse counter The outputs of which are connected to the first inputs of a digital comparator, the second inputs of which are connected to the outputs of the first reversible pulse counter, and the output to the first input of the first element of the match, the output which is connected to the first input of the trigger, whose outputs are connected to the output buses of the device, the second and third elements of coincidence and the first element OR, distinguish li n and the fact that, in order to increase the accuracy and extend the range of adjustment of the output signal duty cycle, it is additionally entered the second and third elements OR, the fourth element of coincidence, the second reversible pulse counter, the first and second switches, the working inputs of which are connected respectively to the outputs of the first and second synchronization blocks, and For the first time, the outputs are with summing and subtracting; the connecting inputs of the first reversible pulse counter, the forward outputs of which are connected to the inputs of the first OR element, the code of which is connected to the first input of the second coincidence element and the first control inputs of both switches, the second control inputs of which are connected to the second input of the first element of coincidence and the inverse output of the high bit of the first reversible pulse counter, the second outputs - with the inputs of the second element OR, and the third outputs - with the inputs of the third element AND LI, the outputs of which are connected respectively with the summing and subtracting inputs of the second reversible pulse counter, the inverse outputs of which are connected to the inputs of the third element 14067598 the coincidence, the output of which is connected by the second input of the second element is connected with the third control inputs of the drops, the output of which is connected to both switches, while inverse-, the second input of the trigger, and the third the outputs of the pulse counter connect-input - with the third input of the first elec with the inputs of the fourth element of the coincidence match and the input of the counter falls, the output of which is connected by simpuls.